Including Nitride (e.g., Algan) (epo) Patents (Class 257/E33.028)
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Patent number: 12136670Abstract: A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.Type: GrantFiled: May 25, 2022Date of Patent: November 5, 2024Assignee: Infineon Technologies AGInventors: Markus Zundel, Andreas Meiser, Hans-Peter Lang, Thorsten Meyer, Peter Irsigler
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Patent number: 11984533Abstract: A light emitting device according to an embodiment of the present disclosure includes: a first layer including Alx2Inx1Ga(1-x1-x2) N (0<x1<1, 0?x2<1); a second layer that is provided on the first layer and includes Aly2Iny1Ga(1-y1-y2) N (0<y1<1, 0?y2<1) that is lattice relaxed with respect to the first layer; and a third layer that is provided on the second layer, includes Alz2Inz1Ga(1-z1-z2) N (0<z1<1, 0?z2<1) that is lattice relaxed with respect to the second layer, and includes an active layer. A lattice constant aGAN of GaN in an in-plane direction, a lattice constant al of the first layer in an in-plane direction, a lattice constant a2 of the second layer in an in-plane direction, and a lattice constant a3 of the third layer in an in-plane direction have a relationship of aGAN<a2<a1, a3.Type: GrantFiled: July 1, 2019Date of Patent: May 14, 2024Assignee: Sony CorporationInventors: Kunihiko Tasai, Hiroshi Nakajima, Hidekazu Kawanishi, Katsunori Yanashima
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Patent number: 11978627Abstract: A substrate for epitaxial growth includes a central region that has a center of the substrate and that serves as a non-modified region, and a peripheral region that surrounds the central region in a manner to be spaced apart from the center of the substrate by a distance and that serves as a modified region having a plurality of modified points. A method for manufacturing a substrate for epitaxial growth includes providing a substrate and forming a plurality of modified points in an interior of the substrate in position corresponding to the modified region. A semiconductor device including the substrate and a method for manufacturing the semiconductor device are also disclosed.Type: GrantFiled: June 28, 2021Date of Patent: May 7, 2024Assignee: Fujian Jing'an Optoelectronics Co., Ltd.Inventors: Juiping Li, Bohsiang Tseng, Jiahao Zhang, Mingxin Chen, Binbin Li, Yao Huo
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Patent number: 11942560Abstract: A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer.Type: GrantFiled: August 13, 2020Date of Patent: March 26, 2024Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventor: Anbang Zhang
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Patent number: 11502221Abstract: A semiconductor light-emitting device includes a buffer structure, a first-type semiconductor layer on the buffer structure, an active layer on the first-type semiconductor layer, and a second-type semiconductor layer on the active layer. The buffer structure includes a nucleation layer, a first dislocation-removing structure on the nucleation layer, and a buffer layer on the first dislocation-removing structure. The first dislocation-removing structure includes a first material layer on the nucleation layer and a second material layer on the first material layer. The second material layer has a lattice constant different from a lattice constant of the first material layer. A roughness of a top surface of the first material layer is higher than a roughness of a top surface of the nucleation layer and higher than a roughness of a top surface of the second material layer.Type: GrantFiled: December 10, 2020Date of Patent: November 15, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaiwon Jean, Joongseo Kang, Namsung Kim, Daemyung Chun
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Patent number: 11444222Abstract: A nitride semiconductor light-emitting element includes an n-type cladding layer including n-type AlGaN and having a first Al composition ratio, and a multiple quantum well layer in which a plurality (number N) of barrier layers including AlGaN having a second Al composition ratio more than the first Al composition ratio and a plural (number N) well layers having an Al composition ratio less than the second Al composition ratio are stacked alternately in this order, wherein the second Al composition ratio of the plurality of barrier layers of the multiple quantum well layer increases at a predetermined increase rate from an n-type cladding layer side toward an opposite side to the n-type cladding layer side.Type: GrantFiled: July 31, 2018Date of Patent: September 13, 2022Assignee: Nikkiso Co., Ltd.Inventors: Yuta Furusawa, Mitsugu Wada, Yusuke Matsukura, Cyril Pernot
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Patent number: 9023721Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.Type: GrantFiled: November 23, 2011Date of Patent: May 5, 2015Assignee: SoitecInventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
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Patent number: 9006779Abstract: Disclosed are a nitride semiconductor light-emitting element and a method for manufacturing the same. The nitride semiconductor light-emitting element according to the present invention comprises: a current blocking part disposed between a substrate and an n-type nitride layer; an activation layer disposed on the top surface of the n-type nitride layer; and a p-type nitride layer disposed on the top surface of the activation layer, wherein the current blocking part is an AlxGa(1-x)N layer, and the Al content x times layer thickness (?m) is in the range of 0.01-0.06. Accordingly, the nitride semiconductor light-emitting element can increase the luminous efficiency by having a current blocking part which prevents current leakage from occurring.Type: GrantFiled: August 2, 2012Date of Patent: April 14, 2015Assignee: Iljin Led Co., Ltd.Inventors: Won-Jin Choi, Jung-Won Park
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Method of growing GaN whiskers from a gallium-containing solvent at low pressure and low temperature
Patent number: 8999060Abstract: Millimeter-scale GaN single crystals in filamentary form, also known as GaN whiskers, grown from solution and a process for preparing the same at moderate temperatures and near atmospheric pressures are provided. GaN whiskers can be grown from a GaN source in a reaction vessel subjected to a temperature gradient at nitrogen pressure. The GaN source can be formed in situ as part of an exchange reaction or can be preexisting GaN material. The GaN source is dissolved in a solvent and precipitates out of the solution as millimeter-scale single crystal filaments as a result of the applied temperature gradient.Type: GrantFiled: March 12, 2013Date of Patent: April 7, 2015Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Jennifer K. Hite, Francis J. Kub, Charles R. Eddy, Jr. -
Patent number: 8987026Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: GrantFiled: September 25, 2014Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
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Patent number: 8946775Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.Type: GrantFiled: August 22, 2012Date of Patent: February 3, 2015Assignee: Industrial Technology Research InstituteInventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
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Patent number: 8941136Abstract: A semiconductor light emitting element includes a semiconductor stack part that includes a light emitting layer, a diffractive face that light emitted from the light emitting layer is incident to, convex portions or concave portions formed in a period which is longer than an optical wavelength of the light and is shorter than a coherent length of the light, wherein the diffractive face reflects incident light in multimode according to Bragg's condition of diffraction and transmits the incident light in multimode according to the Bragg's condition of diffraction, and a reflective face which reflects multimode light diffracted at the diffractive face and let the multimode light be incident to the diffractive face again. The semiconductor stack part is formed on the diffractive face.Type: GrantFiled: August 23, 2010Date of Patent: January 27, 2015Assignee: El-Seed CorporationInventors: Satoshi Kamiyama, Motoaki Iwaya, Hiroshi Amano, Isamu Akasaki, Toshiyuki Kondo, Fumiharu Teramae, Tsukasa Kitano, Atsushi Suzuki
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Patent number: 8928017Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.Type: GrantFiled: January 4, 2011Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Su-hee Chae, Young-soo Park, Bok-ki Min, Jun-youn Kim, Hyun-gi Hong
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Patent number: 8907321Abstract: A III-nitride based device provides improved current injection efficiency by reducing thermionic carrier escape at high current density. The device includes a quantum well active layer and a pair of multi-layer barrier layers arranged symmetrically about the active layer. Each multi-layer barrier layer includes an inner layer abutting the active layer; and an outer layer abutting the inner layer. The inner barrier layer has a bandgap greater than that of the outer barrier layer. Both the inner and the outer barrier layer have bandgaps greater than that of the active layer. InGaN may be employed in the active layer, AlInN, AlInGaN or AlGaN may be employed in the inner barrier layer, and GaN may be employed in the outer barrier layer. Preferably, the inner layer is thin relative to the other layers. In one embodiment the inner barrier and active layers are 15 ? and 24 ? thick, respectively.Type: GrantFiled: December 14, 2010Date of Patent: December 9, 2014Assignee: Lehigh UniveristyInventors: Nelson Tansu, Hongping Zhao, Guangyu Liu, Ronald Arif
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Patent number: 8890195Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.Type: GrantFiled: January 23, 2013Date of Patent: November 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue
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Patent number: 8872227Abstract: A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.Type: GrantFiled: February 22, 2012Date of Patent: October 28, 2014Assignee: Panasonic CorporationInventors: Hidekazu Umeda, Yoshiharu Anda, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
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Patent number: 8866173Abstract: A light emitting device according to the embodiment may include a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer; an electrode on the light emitting structure; a protection layer under a peripheral region of the light emitting structure; and an electrode layer under the light emitting structure, wherein the protection layer comprises a first layer, a second layer, and a third layer, wherein the first layer comprises a first metallic material, and wherein the second layer is disposed between the first layer and the third layer, the second layer has an insulating material or a conductive material.Type: GrantFiled: July 18, 2012Date of Patent: October 21, 2014Assignee: LG Innotek Co., Ltd.Inventor: Hwan Hee Jeong
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Patent number: 8841691Abstract: A method of fabricating a Light Emitting Diode with improved light extraction efficiency, comprising depositing a plurality of Zinc Oxide (ZnO) nanorods on one or more surfaces of a III-Nitride based LED, by growing the ZnO nanorods from an aqueous solution, wherein the surfaces are different from c-plane surfaces of III-Nitride and transmit light generated by the LED.Type: GrantFiled: August 19, 2013Date of Patent: September 23, 2014Assignee: The Regents of the University of CaliforniaInventors: Jacob J. Richardson, Daniel B. Thompson, Ingrid Koslow, Jun-Seok Ha, Frederick F. Lange, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8829652Abstract: A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device.Type: GrantFiled: July 17, 2012Date of Patent: September 9, 2014Assignee: National Chiao Tung UniversityInventors: Chao-Hsun Wang, Hao-Chung Kuo
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Patent number: 8823047Abstract: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type clad layer having a composition ratio of aluminum increased at a predetermined rate, an active layer on the first conductive type clad layer, and a second conductive type semiconductor layer on the active layer.Type: GrantFiled: January 14, 2009Date of Patent: September 2, 2014Assignee: LG Innotek Co., Ltd.Inventor: Sang Hoon Han
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Patent number: 8823016Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.Type: GrantFiled: February 24, 2012Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Maki Sugai, Shinya Nunoue
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Patent number: 8823033Abstract: A nitride semiconductor ultraviolet light-emitting device includes at least one first conductivity-type nitride semiconductor layer, a nitride semiconductor emission layer, at least one second conductivity-type nitride semiconductor layer and a transparent conductive film of crystallized Mgx1Zn1-x1O (0<x1<1) that can transmit 75% or more of light emitted from the emission layer, sequentially stacked in this order on a support substrate.Type: GrantFiled: November 29, 2012Date of Patent: September 2, 2014Assignee: Sharp Kabushiki KaishaInventors: Shuichiro Yamamoto, Shuichi Hirukawa, Masataka Ohta
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Patent number: 8809901Abstract: The invention provides a nanowire light emitting device and a manufacturing method thereof. In the light emitting device, first and second conductivity type clad layers are formed and an active layer is interposed therebetween. At least one of the first and second conductivity type clad layers and the active layer is a semiconductor nanowire layer obtained by preparing a layer of a mixture composed of a semiconductor nanowire and an organic binder and removing the organic binder therefrom.Type: GrantFiled: March 30, 2010Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Won Ha Moon, Dong Woohn Kim, Jong Pa Hong
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Patent number: 8791473Abstract: An illuminating device according to the present invention includes at least a first nitride-based semiconductor light-emitting element and a second nitride-based semiconductor light-emitting element, in which: the first nitride-based semiconductor light-emitting element and the second nitride-based semiconductor light-emitting element each include a semiconductor chip; the semiconductor chip includes a nitride-based semiconductor multilayer structure 45 formed from an AlxInyGazN (x+y+z=1, x?0, y?0, z?0) semiconductor, and the nitride-based semiconductor multilayer structure 20 includes an active layer region 24 having an m-plane as an interface; the first nitride-based semiconductor light-emitting element and the second nitride-based semiconductor light-emitting element each emit polarized light from the active layer region 24; and, when the polarized light emitted from the first nitride-based semiconductor light-emitting element and the polarized light emitted from the second nitride-based semiconductor lighType: GrantFiled: July 9, 2009Date of Patent: July 29, 2014Assignee: Panasonic CorporationInventors: Toshiya Yokogawa, Akira Inoue, Masaki Fujikane, Mitsuaki Oya, Atsushi Yamada, Tadashi Yano
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Patent number: 8785965Abstract: A nitride-based semiconductor light-emitting device according to the present invention has a nitride-based semiconductor multilayer structure 50. The nitride-based semiconductor multilayer structure 50 includes: an active layer 32 including an AlaInbGacN crystal layer (where a+b+c=1, a?0, b?0 and c?0); an AldGaeN overflow suppressing layer 36 (where d+e=1, d>0, and e?0); and an AlfGagN layer 38 (where f+g=1, f?0, g?0 and f<d). The AldGaeN overflow suppressing layer 36 is arranged between the active layer 32 and the AlfGagN layer 38. And the AldGaeN overflow suppressing layer 36 includes an In-doped layer that is doped with In at a concentration of 1×1016 atms/cm3 to 1×1019 atms/cm3.Type: GrantFiled: September 7, 2009Date of Patent: July 22, 2014Assignee: Panasonic CorporationInventors: Toshiya Yokogawa, Ryou Kato
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Patent number: 8765509Abstract: A method for producing a Group III nitride semiconductor light-emitting device includes an n-type layer, a light-emitting layer, and a p-type layer, each of the layers being formed of Group III nitride semiconductor, being sequentially deposited via a buffer layer on a textured sapphire substrate. A buried layer is formed of Group III nitride semiconductor on the buffer layer, at a temperature lower by 20° C. to 80° C. than the temperature of 1000° C. to 1200° C. when the n-type layer is deposited on the buried layer. The texture provided on the sapphire substrate may have a depth of 1 ?m to 2 ?m and a side surface inclined by 40° to 80°. A preventing layer may be formed of GaN at 600° C. to 1050° C. so as to cover the entire top surface of the buffer layer.Type: GrantFiled: September 23, 2011Date of Patent: July 1, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Daisuke Shinoda, Shugo Nitta, Yoshiki Saito
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Patent number: 8748913Abstract: An LED module includes a base, a circuit layer formed on the base and multiple LEDs each having an LED die connecting to the circuit layer. The circuit layer includes multiple connecting sections. Each connecting section includes a first connecting part and a second connecting part electrically insulating and spaced from each other. Each LED includes an electrode layer having a first section and a second section electrically insulated from the first section and respectively electrically connecting the first and second connecting parts of a corresponding connecting section. The LED die is electrically connected to the second section. A transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. An electrically insulating layer is located between the LED die and surrounding the LED die except where the transparent electrically conductive layer connects.Type: GrantFiled: November 29, 2011Date of Patent: June 10, 2014Assignee: Advanced Optoelectronics Technology, Inc.Inventors: Shih-Cheng Huang, Po-Min Tu
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Patent number: 8729575Abstract: The semiconductor light emitting device according to an embodiment includes an N-type nitride semiconductor layer, a nitride semiconductor active layer disposed on the N-type nitride semiconductor layer, and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor layer includes an aluminum gallium nitride layer. The indium concentration in the aluminum gallium nitride layer is between 1E18 atoms/cm3 and 1E20 atoms/cm3 inclusive. The carbon concentration is equal to or less than 6E17 atoms/cm3. Where the magnesium concentration is denoted by X and the acceptor concentration is denoted by Y, Y>{(?5.35e19)2?(X?2.70e19)2}1/2?4.63e19 holds.Type: GrantFiled: August 23, 2011Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jongil Hwang, Hung Hung, Yasushi Hattori, Rei Hashimoto, Shinji Saito, Masaki Tohyama, Shinya Nunoue
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Patent number: 8728236Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.Type: GrantFiled: January 17, 2011Date of Patent: May 20, 2014Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo
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Patent number: 8716694Abstract: A semiconductor light emitting device includes: n-type and p-type semiconductor layers; and an active layer disposed between the n-type and p-type semiconductor layers. The active layer has a structure in which a plurality of quantum well layers and a plurality of quantum barrier layers are alternately disposed, wherein the plurality of quantum well layers are made of AlxInyGa1-x-yN (0?x<1, 0<y?1) and each of the plurality of quantum well layers contains a different indium (In) content. And, among the plurality of quantum barrier layers, a quantum barrier layer adjacent to a quantum well layer having a higher indium (In) content is thicker than a quantum barrier layer adjacent to a quantum well layer having a lower indium (In) content.Type: GrantFiled: December 6, 2012Date of Patent: May 6, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Heon Han, Jeong Wook Lee, Jae Sung Hyun, Jin Young Lim, Dong Joon Kim, Young Sun Kim
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Publication number: 20140097442Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: Industrial Technology Research InstituteInventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
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Publication number: 20140097443Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Hsiang Fang, Rong Xuan, Chen-Zi Liao, Yi-Keng Fu, Chih-Wei Hu, Chien-Pin Lu, Hsun-Chih Liu
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Patent number: 8686450Abstract: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound layer through the epitaxial lateral over-growth process and sequentially forming an active layer and a p-type GaN layer on the n-type GaN layer; forming a structure supporting layer on the p-type GaN layer; sequentially removing the substrate and the GaN layer formed on the substrate after forming the structure supporting layer; removing the patterned compound layer exposed after removing the GaN layer so as to form an n-type GaN layer patterned in a concave shape; and forming an n-type electrode on the n-type GaN layer patterned in a concave shape.Type: GrantFiled: August 23, 2007Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Hoon Lee, Hee Seok Choi, Jeong Tak Oh, Su Yeol Lee
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Patent number: 8685762Abstract: A light emitting device comprises: an LED chip having a quantum well structure and a light emitting layer made of a gallium nitride compound semiconductor; a first transparent material covering the LED chip; a second transparent material for protecting the LED chip and the first transparent material; and a phosphor for absorbing a part of the light from the LED chip and emitting a light having a wavelength different from the light from the LED chip; wherein the phosphor is included in second transparent material, and the light from the LED chip and the light from said phosphor are mixed to make a white light.Type: GrantFiled: August 15, 2011Date of Patent: April 1, 2014Assignee: Nichia CorporationInventors: Yoshinori Shimizu, Kensho Sakano, Yasunobu Noguchi, Toshio Moriguchi
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Patent number: 8686455Abstract: A composite substrate for the formation of a light-emitting device, ensuring that a high-quality nitride-based light-emitting diode can be easily formed on its top surface and the obtained substrate-attached light-emitting diode functions as a light-emitting device capable of emitting light for an arbitrary color such as white, is provided.Type: GrantFiled: March 2, 2010Date of Patent: April 1, 2014Assignees: Ube Industries, Ltd., RikenInventors: Yasuyuki Ichizono, Hideki Hirayama
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Patent number: 8680537Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: GrantFiled: September 4, 2012Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8680571Abstract: A light emitting diode (LED) capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1?x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.Type: GrantFiled: July 11, 2013Date of Patent: March 25, 2014Assignee: LG Innotek Co., Ltd.Inventor: Seong Jae Kim
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Patent number: 8679248Abstract: Millimeter-scale GaN single crystals in filamentary form, also known as GaN whiskers, grown from solution and a process for preparing the same at moderate temperatures and near atmospheric pressures are provided. GaN whiskers can be grown from a GaN source in a reaction vessel subjected to a temperature gradient at nitrogen pressure. The GaN source can be formed in situ as part of an exchange reaction or can be preexisting GaN material. The GaN source is dissolved in a solvent and precipitates out of the solution as millimeter-scale single crystal filaments as a result of the applied temperature gradient.Type: GrantFiled: November 23, 2010Date of Patent: March 25, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Jennifer K. Hite, Francis J. Kub, Charles R. Eddy, Jr.
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Publication number: 20140077153Abstract: The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Zhen-Yu Li, Tzu-Te Yang, Hon-Way Lin, Chung-Pao Lin, Kuan-Chun Chen, Ching-Yu Chen, You-Da Lin, Hao-Chung Kuo
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Patent number: 8674337Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1?x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.Type: GrantFiled: June 27, 2011Date of Patent: March 18, 2014Assignee: LG Innotek Co., Ltd.Inventor: Seong Jae Kim
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Patent number: 8674381Abstract: A nitride semiconductor light emitting device is provided with a substrate, an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, an n-side pad electrode, a translucent electrode and a p-side pad electrode, wherein the translucent electrode is formed from an electrically conductive oxide, the n-side pad electrode adjoins the periphery of the translucent electrode and the p-side pad electrode is disposed so as to satisfy the following relationships: 0.3L?X?0.5L and 0.2L?Y?0.5L where X is the distance between ends of the p-side pad electrode and the n-side pad electrode, Y is the distance between the end of the p-side pad electrode and the periphery of the translucent electrode, L is the length of the translucent electrode on the line connecting the centroids of the p-side pad electrode and the n-side pad electrode minus the outer diameter d of the p-side pad electrode.Type: GrantFiled: January 3, 2011Date of Patent: March 18, 2014Assignee: Nichia CorporationInventors: Takahiko Sakamoto, Yasutaka Hamaguchi
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Patent number: 8663389Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.Type: GrantFiled: May 21, 2011Date of Patent: March 4, 2014Inventor: Andrew Peter Clarke
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Patent number: 8664693Abstract: The present invention relates to a light emitting diode having an AlxGa1-xN buffer layer and a method of fabricating the same, and more particularly, to a light emitting diode having an AlxGa1-xN buffer layer, wherein between a substrate and a GaN-based semiconductor layer, the Al x Ga 1-x N (O?x?1) buffer layer having the composition ratio x of Al decreasing from the substrate to the GaN-based semiconductor layer is interposed to reduce lattice mismatch between the substrate and the GaN-based semiconductor layer, and a method of fabricating the same. To this end, the present invention provides a light emitting diode comprising a substrate; a first conductive semiconductor layer positioned on the substrate; and an AlxGa1-xN (O?x?1) buffer layer interposed between the substrate and the first conductive semiconductor layer and having a composition ratio x of Al decreasing from the substrate to the first conductive semiconductor layer.Type: GrantFiled: March 9, 2007Date of Patent: March 4, 2014Assignee: Seoul Opto Device Co., Ltd.Inventor: Ki Bum Nam
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Patent number: 8658440Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.Type: GrantFiled: December 6, 2011Date of Patent: February 25, 2014Assignee: Stanley Electric Co., Ltd.Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
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Patent number: 8648350Abstract: Provided is a gallium nitride-based compound semiconductor light-emitting element, in which the concentration of Mg which is a p-type dopant in a p-GaN layer in which the (10-10) m-plane of a hexagonal wurtzite structure grows is adjusted in a range from 1.0×1018 cm?3 to 9.0×1018 cm?3.Type: GrantFiled: February 17, 2012Date of Patent: February 11, 2014Assignee: Panasonic CorporationInventors: Ryou Kato, Masaki Fujikane, Akira Inoue, Toshiya Yokogawa
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Patent number: 8637960Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.Type: GrantFiled: October 2, 2012Date of Patent: January 28, 2014Assignee: Covalent Material CorporationInventors: Yoshihisa Abe, Jun Komiyama, Hiroshi Oishi, Akira Yoshida, Kenichi Eriguchi, Shunichi Suzuki
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Patent number: 8613802Abstract: Affords nitride semiconductor crystal manufacturing apparatuses that are durable and that are for manufacturing nitride semiconductor crystal in which the immixing of impurities from outside the crucible is kept under control, and makes methods for manufacturing such nitride semiconductor crystal, and the nitride semiconductor crystal itself, available. A nitride semiconductor crystal manufacturing apparatus (100) is furnished with a crucible (101), a heating unit (125), and a covering component (110). The crucible (101) is where, interiorly, source material (17) is disposed. The heating unit (125) is disposed about the outer periphery of the crucible (101), where it heats the crucible (101) interior. The covering component (110) is arranged in between the crucible (101) and the heating unit (125).Type: GrantFiled: January 20, 2010Date of Patent: December 24, 2013Assignee: Sumitomo Electric Industies, Ltd.Inventors: Issei Satoh, Michimasa Miyanaga, Yoshiyuki Yamamoto, Hideaki Nakahata
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Patent number: 8598599Abstract: The present invention provides a Group III nitride semiconductor light-emitting device whose main surface is a plane which provides an internal electric field of zero, and which exhibits improved emission performance. The light-emitting device includes a sapphire substrate which has, in a surface thereof, a plurality of dents which are arranged in a stripe pattern as viewed from above; an n-contact layer formed on the dented surface of the sapphire substrate; a light-emitting layer formed on the n-contact layer; an electron blocking layer formed on the light-emitting layer; a p-contact layer formed on the electron blocking layer; a p-electrode; and an n-electrode. The electron blocking layer has a thickness of 2 to 8 nm and is formed of Mg-doped AlGaN having an Al compositional proportion of 20 to 30%.Type: GrantFiled: March 25, 2011Date of Patent: December 3, 2013Assignee: Toyoda Gosei Co., Ltd.Inventors: Yoshiki Saito, Koji Okuno, Yasuhisa Ushida
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Patent number: 8591652Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the material for forming the mask layer consists at least partially of tungsten silicide nitride or tungsten silicide and wherein the semiconductor substrate self-separates from the starting substrate without further process steps.Type: GrantFiled: August 24, 2006Date of Patent: November 26, 2013Assignee: Freiberger Compound Materials GmbHInventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
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Patent number: 8574935Abstract: A manufacturing method of a solid state light emitting element is provided. A plurality of protrusion structures separated to each other are formed on a first substrate. A buffer layer is formed on the protrusion structures and fills the gaps between protrusion structures. An epitaxial growth layer is formed on the buffer layer to form a first semiconductor stacking structure. The first semiconductor stacking structure is inverted to a second substrate, so that the first semiconductor epitaxial layer and the second substrate are connected to form a second semiconductor stacking structure. The buffer layer is etched by a first etchant solution to form a third semiconductor stacking structure. A second etchant solution is used to permeate through the gaps between the protrusion structures, so that the protrusion structures are etched completely. The first substrate is removed from the third semiconductor stacking structure to form a fourth semiconductor stacking structure.Type: GrantFiled: April 10, 2012Date of Patent: November 5, 2013Assignee: Lextar Electronics CorporationInventors: Chang-Chin Yu, Mong-Ea Lin