Comprising Only Group Iii-v Compound (epo) Patents (Class 257/E33.023)
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Patent number: 11600746Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.Type: GrantFiled: April 2, 2021Date of Patent: March 7, 2023Assignee: EPISTAR CORPORATIONInventors: Chia-Ming Liu, Chang-Hua Hsieh, Yung-Chung Pan, Chang-Yu Tsai, Ching-Chung Hu, Ming-Pao Chen, Chi Shen, Wei-Chieh Lien
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Patent number: 11508871Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The electron blocking layer is located between the active region and the p-type contact layer. In an embodiment, the electron blocking layer can include a plurality of sublayers that vary in composition.Type: GrantFiled: October 1, 2020Date of Patent: November 22, 2022Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
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Patent number: 11339327Abstract: A method of producing nanoparticles comprises effecting conversion of a molecular cluster compound to the material of the nanoparticles. The molecular cluster compound comprises a first ion and a second ion to be incorporated into the growing nanoparticles. The conversion can be effected in the presence of a second molecular cluster compound comprising a third ion and a fourth ion to be incorporated into the growing nanoparticles, under conditions permitting seeding and growth of the nanoparticles via consumption of a first molecular cluster compound.Type: GrantFiled: December 6, 2018Date of Patent: May 24, 2022Assignee: Nanoco Technologies Ltd.Inventors: Paul O'Brien, Nigel Pickett
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Patent number: 9034676Abstract: The present invention provides a method of fabricating a vertical type light-emitting diode and a method of separating layers from each other. Crystalline rods are provided on a lower layer or a lower substrate. The crystalline rods comprise ZnO. A layer which constitutes light-emitting diode or a light-emitting diode structure is formed on the crystalline rods, and the lower substrate is separated therefrom. The crystalline rods are dissolved during the separation. The formation of the crystalline rods is achieved by the formation of a seed layer and selective growth based on the seed layer.Type: GrantFiled: July 22, 2010Date of Patent: May 19, 2015Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Ki-Seok Kim, Gun-Young Jung
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Patent number: 9024331Abstract: Disclosed is a semiconductor light emitting element (LC) provided with a substrate (110) having one surface on which plural hexagonal-pyramid-shaped protrusions (110b) are provided, a base layer (130) provided so as to be in contact with the surface on which the protrusions (110b) are provided, an n-type semiconductor layer (140) provided so as to be in contact with the base layer (130), a light emitting layer (150) provided so as to be in contact with the n-type semiconductor layer (140), and a p-type semiconductor layer (160) provided so as to be in contact with the light emitting layer (150). Each protrusion (110b) scatters light in lateral and oblique directions within the semiconductor light emitting element (LC). The protrusions are densely arranged on a substrate on which semiconductor layers are laminated, so that the light extraction efficiency is improved.Type: GrantFiled: December 13, 2010Date of Patent: May 5, 2015Assignee: Toyoda Gosei Co., Ltd.Inventor: Yohei Sakano
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Patent number: 8993993Abstract: Provided are a semiconductor light emitting device and a method for fabricating the same. The semiconductor light emitting device includes a light emitting structure and a pattern. The light emitting structure includes a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer. The pattern is formed on at least one light emitting surface among the surfaces of the light emitting structure. The pattern has a plurality of convex or concave parts that are similar in shape. The light emitting surface with the pattern formed thereon has a plurality of virtual reference regions that are equal in size and are arranged in a regular manner. The convex or concave part is disposed in the reference regions such that a part of the edge thereof is in contact with the outline of one of the plurality of virtual reference regions.Type: GrantFiled: May 10, 2011Date of Patent: March 31, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung Duk Ko, Jung Ja Yang, Yu Seung Kim, Youn Joon Sung, Soo Jin Jung, Dae Cheon Kim, Byung Kwun Lee
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Patent number: 8952419Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.Type: GrantFiled: September 19, 2011Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
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Patent number: 8928017Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.Type: GrantFiled: January 4, 2011Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Su-hee Chae, Young-soo Park, Bok-ki Min, Jun-youn Kim, Hyun-gi Hong
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Patent number: 8911518Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally, the present disclosure provides techniques resulting in an optical device comprising a substrate having a dislocation bundle center being used as a conductive region for a contact.Type: GrantFiled: June 7, 2012Date of Patent: December 16, 2014Assignee: Soraa, Inc.Inventors: Arpan Chakraborty, Michael R. Krames, Tal Margalith, Rafael Aldaz
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Patent number: 8895337Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.Type: GrantFiled: January 17, 2013Date of Patent: November 25, 2014Assignee: Sandia CorporationInventors: George T. Wang, Qiming Li
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Patent number: 8890195Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.Type: GrantFiled: January 23, 2013Date of Patent: November 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue
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Patent number: 8878243Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.Type: GrantFiled: May 4, 2010Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 8866173Abstract: A light emitting device according to the embodiment may include a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer; an electrode on the light emitting structure; a protection layer under a peripheral region of the light emitting structure; and an electrode layer under the light emitting structure, wherein the protection layer comprises a first layer, a second layer, and a third layer, wherein the first layer comprises a first metallic material, and wherein the second layer is disposed between the first layer and the third layer, the second layer has an insulating material or a conductive material.Type: GrantFiled: July 18, 2012Date of Patent: October 21, 2014Assignee: LG Innotek Co., Ltd.Inventor: Hwan Hee Jeong
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Patent number: 8866186Abstract: The present invention aims to enhance the light extraction efficiency of the Group III nitride semiconductor light-emitting device. The inventive Group III nitride semiconductor light-emitting device comprises a substrate; and a Group III nitride semiconductor layer including a light-emitting layer, stacked on the substrate, wherein the side face of the Group III nitride semiconductor layer is tilted with respect to the normal line of the major surface of the substrate.Type: GrantFiled: September 20, 2006Date of Patent: October 21, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Gaku Oriji, Koji Kamei, Hisayuki Miki, Akihiro Matsuse
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Patent number: 8859314Abstract: There is provided a method of manufacturing a semiconductor light emitting device, the method including: sequentially growing a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a semiconductor growth substrate to form a light emitting part; forming a support part on the second conductivity type semiconductor layer to be coupled to the light emitting part; separating the semiconductor growth substrate from the light emitting part; and applying an etching gas to the semiconductor growth substrate to remove a residue of the first conductivity type semiconductor layer from a surface of the semiconductor growth substrate.Type: GrantFiled: June 14, 2012Date of Patent: October 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Sun Maeng, Ki Ho Park, Bum Joon Kim, Hyun Seok Ryu, Jung Hyun Lee, Boung Kyun Kim, Ki Sung Kim, Suk Ho Yoon
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Patent number: 8841756Abstract: Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be patterned to expose a portion of the substrate and to form a substrate-dielectric film boundary substantially parallel to a <110> direction. A {110} type sidewall facet can then be formed by epitaxially growing a semiconductor layer on the exposed portion of the substrate and the dielectric film.Type: GrantFiled: August 28, 2008Date of Patent: September 23, 2014Assignee: STC.UNMInventors: Seung-Chang Lee, Steven R. J. Brueck
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Patent number: 8829488Abstract: Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.Type: GrantFiled: August 27, 2012Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
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Patent number: 8823142Abstract: A GaN single crystal substrate has a main surface with an area of not less than 10 cm2, the main surface has a plane orientation inclined by not less than 65° and not more than 85° with respect to one of a (0001) plane and a (000-1) plane, and the substrate has at least one of a substantially uniform distribution of a carrier concentration in the main surface, a substantially uniform distribution of a dislocation density in the main surface, and a photoelasticity distortion value of not more than 5×10?5, the photoelasticity distortion value being measured by photoelasticity at an arbitrary point in the main surface when light is applied perpendicularly to the main surface at an ambient temperature of 25° C. Thus, the GaN single crystal substrate suitable for manufacture of a GaN-based semiconductor device having a small variation of characteristics can be obtained.Type: GrantFiled: November 8, 2013Date of Patent: September 2, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shinsuke Fujiwara, Koji Uematsu, Hideki Osada, Seiji Nakahata
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Patent number: 8822247Abstract: An optical semiconductor element and a manufacturing method thereof that can improve the light extraction efficiency with maintaining the yield. The manufacturing method includes forming a plurality of recesses arranged at equal intervals along a crystal axis of a semiconductor film in a surface of the semiconductor film; and performing an etching process on the surface of the semiconductor film, thereby forming a plurality of protrusions arranged according to the arrangement form of the plurality of recesses and deriving from the crystal structure of the semiconductor film in the surface of the semiconductor film.Type: GrantFiled: March 5, 2012Date of Patent: September 2, 2014Assignee: Stanley Electric Co., Ltd.Inventor: Tatsuma Saito
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Patent number: 8809868Abstract: Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×1017 cm?3, and a ratio (Noxg/Npd) of the oxygen concentration Noxg to a p-type dopant concentration Npd of the first p-type gallium nitride based semiconductor layer is not more than 1/10.Type: GrantFiled: November 4, 2011Date of Patent: August 19, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yohei Enya, Takashi Kyono, Takamichi Sumitomo, Yusuke Yoshizumi, Koji Nishizuka
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Publication number: 20140203287Abstract: A nitride light emitting device comprises a current blocking Schottky junction zone formed below the p-electrode and above the active region so that current injection from the p-electrode to the area of the active region that is vertically shaded by the p-electrode is blocked by the Schottky junction zone. A method for fabricating the same is also provided.Type: ApplicationFiled: July 21, 2012Publication date: July 24, 2014Applicant: INVENLUX LIMITEDInventors: JIANPING ZHANG, MARIO SAENGER, WILLIAM SO, FANGHAI ZHAO, CHUNHUI YAN
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Patent number: 8766281Abstract: A light emitting diode chip includes a substrate, an epitaxial layer, two inclined plane units, and two electrode units. The substrate has top and bottom surfaces. The epitaxial layer is disposed on the top surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer toward the bottom surface of the substrate, and includes an inclined sidewall formed on the epitaxial layer, and a substrate inclined wall formed on the substrate. Each of the electrode units includes an electrode disposed on the epitaxial layer, and a conductive portion extending from the electrode to the substrate inclined wall along corresponding one of the inclined plane units.Type: GrantFiled: December 13, 2012Date of Patent: July 1, 2014Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.Inventor: Chih-Chiang Kao
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Patent number: 8765505Abstract: The present invention relates to a multi-luminous element and a method for manufacturing the same. The present invention provides the multi-luminous element comprising: a buffer layer disposed on a substrate; a first type semiconductor layer disposed on the buffer layer; a first active layer which is disposed on the first type semiconductor layer and is patterned to expose a part of the first type semiconductor layer; a second active layer disposed on the first type semiconductor layer which is exposed by the first active layer; and a second type semiconductor layer disposed on the first active layer and the second active layer, the first and second active layers being repeatedly disposed in the horizontal direction, and the method for manufacturing the same.Type: GrantFiled: March 15, 2011Date of Patent: July 1, 2014Assignee: Korea Photonics Technology InstituteInventors: Seong Ran Jeon, Jae Bum Kim, Seung Jae Lee
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Patent number: 8754523Abstract: A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip.Type: GrantFiled: March 11, 2011Date of Patent: June 17, 2014Assignee: STMicroelectronics (Grenoble 2) SASInventor: Romain Coffy
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Patent number: 8735927Abstract: The invention provides a Group III nitride semiconductor light-emitting device which has a light extraction face at the n-layer side and which provides high light emission efficiency. The light-emitting device is produced through the laser lift-off technique. The surface of the n-GaN layer of the light-emitting device is roughened. On the n-GaN layer, a transparent film is formed. The transparent film satisfies the following relationship: 0.28?n×d1×2/??0.42 or 0.63?n×d1×2/??0.77, wherein n represents the refractive index of the transparent film, d1 represents the thickness of the transparent film in the direction orthogonal to an inclined face thereof, and ? represents the wavelength of the light emitted from the MQW layer.Type: GrantFiled: December 21, 2012Date of Patent: May 27, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Yuhei Ikemoto, Naoki Arazoe
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Patent number: 8723222Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: GrantFiled: July 13, 2012Date of Patent: May 13, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Bum Bae, Eun Soo Nam, Jae Kyoung Mun, Sung Bock Kim, Hae Cheon Kim, Chull Won Ju, Sang Choon Ko, Jong-Won Lim, Ho Kyun Ahn, Woo Jin Chang, Young Rak Park
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Patent number: 8716049Abstract: Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.Type: GrantFiled: February 11, 2011Date of Patent: May 6, 2014Assignee: Applied Materials, Inc.Inventors: Jie Su, Olga Kryliouk
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Patent number: 8698182Abstract: A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency.Type: GrantFiled: June 7, 2013Date of Patent: April 15, 2014Assignee: National Tsing Hua UniversityInventors: Shiuh Chao, Hao-Min Ku, Chen-Yang Huang
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Patent number: 8697462Abstract: A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency. The manufacturing method of the light emitting device having auto-cloning photonic crystal structures is presented here.Type: GrantFiled: June 7, 2013Date of Patent: April 15, 2014Assignee: National Tsing Hua UniversityInventors: Shiuh Chao, Hao-Min Ku, Chen-Yang Huang
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Patent number: 8680548Abstract: A semiconductor light emitting device has a support substrate, a light emitting element, and underfill material. The light emitting element includes a nitride-based group III-V compound semiconductor layer contacted via a bump on the support substrate. The underfill material is disposed between the support substrate and the light emitting element, the underfill material comprising a rib portion disposed outside of an end face of the light emitting element to surround the end surface of the light emitting element.Type: GrantFiled: September 2, 2010Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toru Gotoda, Hajime Nago, Toshiyuki Oka, Kotaro Zaima, Shinya Nunoue
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Patent number: 8680571Abstract: A light emitting diode (LED) capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1?x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.Type: GrantFiled: July 11, 2013Date of Patent: March 25, 2014Assignee: LG Innotek Co., Ltd.Inventor: Seong Jae Kim
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Patent number: 8680534Abstract: A vertical light-emitting diode (VLED) includes a metal substrate, a p-electrode coupled to the metal substrate, a p-contact coupled to the p-electrode, a p-GaN portion coupled to the p-electrode, an active region coupled to the p-GaN portion, an n-GaN portion coupled to the active region, and a phosphor layer coupled to the n-GaN portion.Type: GrantFiled: September 7, 2011Date of Patent: March 25, 2014Assignee: Semileds CorporationInventors: Chuong A Tran, Trung Tri Doan
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Patent number: 8674398Abstract: There are provided a group III nitride semiconductor light emitting device which is constituted of a substrate, an intermediate layer formed thereon having a favorable level of orientation properties, and a group III nitride semiconductor formed thereon having a favorable level of crystallinity, and having excellent levels of light emitting properties and productivity; a production method thereof; and a lamp, the group III nitride semiconductor light emitting device configured so that at least an intermediate layer 12 composed of a group III nitride compound is laminated on a substrate 11, and an n-type semiconductor layer 14 having a base layer 14a, a light emitting layer 15 and a p-type semiconductor layer 16 are sequentially laminated on the intermediate layer 12, wherein when components are separated, based on a peak separation technique using an X-ray rocking curve of the intermediate layer 12, into a broad component having the full width at half maximum of 720 arcsec or more and a narrow component,Type: GrantFiled: July 3, 2008Date of Patent: March 18, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Hiroaki Kaji, Hisayuki Miki
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Patent number: 8676002Abstract: Method of producing a photonic device including at least one light source and at least one photodetector on a structure including a waveguide layer, this method comprising the following steps: a) growing successively on a substrate (10), a photodetection structure (11) and a light source structure (12), the photodetection structure and the light source structure being made of a stack of layers, the light source layers being stacked on top of the photodetector layers and both structures sharing one of these layers.Type: GrantFiled: February 1, 2010Date of Patent: March 18, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Laurent Grenouillet, Jean-Marc Fedeli, Liu Liu, Regis Orobtchouk, Philippe Regreny, Gunther Roelkens, Pedro Rojo-Romeo, Dries Van Thourhout
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Patent number: 8674375Abstract: A light emitting diode (LED) includes a p-type layer of material, an n-type layer of material and an active layer between the p-type layer and the n-type layer. A roughened layer of transparent material is adjacent one of the p-type layer of material and the n-type layer of material. The roughened layer of transparent material has a refractive index close to or substantially the same as the refractive index of the material adjacent the layer of transparent material, and may be a transparent oxide material or a transparent conducting material. An additional layer of conductive material may be between the roughened layer and the n-type or p-type layer.Type: GrantFiled: July 21, 2005Date of Patent: March 18, 2014Assignee: Cree, Inc.Inventors: Steven P. Denbaars, James Ibbetson, Shuji Nakamura
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Patent number: 8659039Abstract: A highly-efficient semiconductor light emitting diode with improved light extraction efficiency comprising at least a substrate having a plurality of crystal planes, a first conductivity-type barrier layer, an active layer serving as a light emitting layer and a second conductivity-type barrier layer stacked on the substrate. The semiconductor light emitting diode comprises a ridge structure configured from one flat surface and at least two inclining surfaces in the in-plane direction. The width (W) of the flat surface of the ridge structure is 2? (?: light emission wavelength) or less.Type: GrantFiled: February 8, 2010Date of Patent: February 25, 2014Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Xuelun Wang, Mutsuo Ogura
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Patent number: 8659029Abstract: A low contact resistance semiconductor structure includes a substrate, a semiconductor stacked layer, a low contact resistance layer and a transparent conductive layer. The low contact resistance layer is formed on one side of a P-type GaN layer of the semiconductor stacked layer. The low contact resistance layer is formed at a thickness smaller than 100 Angstroms and made of a material selected from the group consisting of aluminum, gallium, indium, and combinations thereof. Through the low contact resistance layer, the resistance between the P-type GaN layer and transparent conductive layer can be reduced and light emission efficiency can be improved when being used on LEDs. The method of fabricating the low contact resistance semiconductor structure of the invention forms a thin and consistent low contact resistance layer through a Metal Organic Chemical Vapor Deposition (MOCVD) method to enhance matching degree among various layers.Type: GrantFiled: November 21, 2011Date of Patent: February 25, 2014Assignee: Lextar Electronics CorporationInventors: Te-Chung Wang, Fu-Bang Chen, Hsiu-Mu Tang
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Patent number: 8648378Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.Type: GrantFiled: December 7, 2012Date of Patent: February 11, 2014Assignee: Panasonic CorporationInventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Ryou Kato
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Patent number: 8647901Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.Type: GrantFiled: June 11, 2008Date of Patent: February 11, 2014Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
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Patent number: 8642992Abstract: A Group III nitride compound semiconductor light emitting device is provided which has: an n-type semiconductor layer (12); an active layer (13) of a multiple quantum well structure laminated on the n-type semiconductor layer (12); a first p-type semiconductor layer (14) that is a layer of a superlattice structure in which an undoped film (14a) that has a composition AlxGa1-xN (x indicating composition ratio, being within a range 0<x?0.4) and that contains no dopant, and a doped film (14b) that has a composition AlyGa1-yN (y indicating composition ratio, being within a range 0?y<0.4) and that contains a dopant, are alternately laminated a plurality of times, and a surface thereof on the active layer side (13) is constituted by the undoped film (14a); and a second p-type semiconductor layer (15) laminated on the first p-type semiconductor layer (14).Type: GrantFiled: November 6, 2009Date of Patent: February 4, 2014Assignee: Toyoda Gosei Co., Ltd.Inventor: Hisayuki Miki
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Patent number: 8643023Abstract: A light-emitting diode having a high output, high efficiency, and a long service life under a high-humidity environment is provided. The light-emitting diode (1) includes a compound semiconductor layer (2) having a light-emitting section (7), ohmic electrodes (4, 5) provided on the main light extraction surface of the compound semiconductor layer (2), and an electrode protection layer (6) for protecting the ohmic electrodes (4, 5), wherein the Al concentrations of the surfaces (2a, 2b) of the compound semiconductor layer (2), which include the main light extraction surface, are 20% or less and the As concentration of the surfaces (2a, 2b) is less than 1%, and the electrode protection layer (6) has a two-layer structure composed of a first protective film (12) provided so as to cover the ohmic electrodes (4, 5) and a second protective film (13) provided so as to cover at least an end portion of the first protective film (12).Type: GrantFiled: May 13, 2010Date of Patent: February 4, 2014Assignee: Showa Denko K.K.Inventors: Wataru Nabekura, Ryouichi Takeuchi
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Patent number: 8643022Abstract: An LED comprises an electrode layer comprising a first a second sections electrically insulated from each other; an electrically conductive layer on the second section, an electrically conductive pole protruding from the electrically conductive layer; an LED die comprising an electrically insulating substrate on the electrically conductive layer, and a P-N junction on the electrically insulating substrate, the P-N junction comprising a first electrode and a second electrode, the electrically conductive pole extending through the electrically insulating substrate to electrically connect the first electrode to the second section; a transparent electrically conducting layer on the LED die, the transparent electrically conducting layer electrically connecting the second electrode to the first section; and an electrically insulating layer between the LED die, the electrically conductive layer, and the transparent electrically conducting layer, wherein the electrically insulating layer insulates the transparent eleType: GrantFiled: November 21, 2011Date of Patent: February 4, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Po-Min Tu, Shih-Cheng Huang, Ya-Wen Lin
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Patent number: 8637960Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.Type: GrantFiled: October 2, 2012Date of Patent: January 28, 2014Assignee: Covalent Material CorporationInventors: Yoshihisa Abe, Jun Komiyama, Hiroshi Oishi, Akira Yoshida, Kenichi Eriguchi, Shunichi Suzuki
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Patent number: 8637895Abstract: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The first thin insulating layer is formed on the active layer. The second conductive type semiconductor layer is formed on the thin insulating layer.Type: GrantFiled: July 17, 2012Date of Patent: January 28, 2014Assignee: LG Innotek Co., Ltd.Inventors: Dae Sung Kang, Hyo Kun Son
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Patent number: 8637901Abstract: A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.Type: GrantFiled: August 7, 2012Date of Patent: January 28, 2014Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Tsvetanka Zheleva, Shah Pankaj, Michael Derenge
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Patent number: 8629468Abstract: A method for manufacturing a light emitting device, includes: preparing a first substrate by slicing a single crystal ingot pulled in a pulling direction tilted with respect to a first plane orientation, the slicing being in a direction substantially perpendicular to the pulling direction; preparing a second substrate including a major surface having a plane orientation substantially parallel to a plane orientation of a major surface of the first substrate; growing a stacked unit as a crystal on the major surface of the second substrate, the stacked unit including a light emitting layer; and removing the second substrate after bonding the stacked unit and the major surface of the first substrate by heating them in a joined state.Type: GrantFiled: January 20, 2010Date of Patent: January 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Isomoto, Chisato Furukawa
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Patent number: 8624220Abstract: To provide a high-quality nitride semiconductor ensuring high emission efficiency of a light-emitting element fabricated. In the present invention, when obtaining a nitride semiconductor by sequentially stacking a one conductivity type nitride semiconductor part, a quantum well active layer structure part, and a another conductivity type nitride semiconductor part opposite the one conductivity type, the crystal is grown on a base having a nonpolar principal nitride surface, the one conductivity type nitride semiconductor part is formed by sequentially stacking a first nitride semiconductor layer and a second nitride semiconductor layer, and the second nitride semiconductor layer has a thickness of 400 nm to 20 ?m and has a nonpolar outermost surface. By virtue of selecting the above-described base for crystal growth, an electron and a hole, which are contributing to light emission, can be prevented from spatial separation based on the QCSE effect and efficient radiation is realized.Type: GrantFiled: May 20, 2011Date of Patent: January 7, 2014Assignee: Mitsubishi Chemical CorporationInventors: Hideyoshi Horie, Kaori Kurihara
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Patent number: 8618564Abstract: The present disclosure relates to high efficiency light emitting diode devices and methods for fabricating the same. In accordance with one or more embodiments, a light emitting diode device includes a substrate having one or more recessed features formed on a surface thereof and one or more omni-directional reflectors formed to overlie the one or more recessed features. A light emitting diode layer is formed on the surface of the substrate to overlie the omni-directional reflector. The one or more omni-directional reflectors are adapted to efficiently reflect light.Type: GrantFiled: October 5, 2010Date of Patent: December 31, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Jung-Tang Chu, Hsing-Kuo Hsia, Ching-Hua Chiu
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Patent number: 8610167Abstract: An n-type layer of a light-emitting device has a structure in which a first n-type layer, a second n-type layer and a third n-type layer are sequentially laminated in this order on a sapphire substrate, and an n-electrode composed of V/Al is formed on the second n-type layer. The first n-type layer and the second n-type layer are n-GaN, and the third n-type layer is n-InGaN. The n-type impurity concentration of the second n-type layer is higher than that of the first n-type layer and the third n-type layer.Type: GrantFiled: September 29, 2009Date of Patent: December 17, 2013Assignee: Toyoda Gosei Co., Ltd.Inventors: Miki Moriyama, Koichi Goshonoo
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Patent number: 8597967Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally the present disclosure provide techniques resulting in a optical device comprising a substrate having three or more corners, where at least one of the corners is defined by a dislocation bundle characterized by a diameter of less than 100 microns, the gallium and nitrogen containing substrate having a predefined portion free from dislocation bundle centers, an active region containing one or more active layers, the active region being positioned within the predefined region; and a conductive region formed within the predefined region.Type: GrantFiled: November 17, 2011Date of Patent: December 3, 2013Assignee: Soraa, Inc.Inventors: Michael R. Krames, Tai Margalith, Rafael Aldaz