With Heterojunction (e.g., Algaas/gaas) (epo) Patents (Class 257/E33.032)
  • Patent number: 11694619
    Abstract: A display apparatus includes a substrate which includes a first pixel area and a second pixel area. A third pixel area is spaced apart from the second pixel area. A notch peripheral area is adjacent to the first, second and third pixel areas. A plurality of pixels are provided in the first, second and third pixel areas. A first scan line is disposed on the substrate. The first scan line includes a first portion disposed in the second pixel area, a second portion disposed in the third pixel area, and a third portion which connects the first portion to the second portion. The third portion is disposed in the notch peripheral area. A second scan line is disposed on the substrate in the first pixel area. A surface area of the first scan line is from about 90% to about 110% of a surface area of the second scan line.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Hyun Ka, Taehoon Kwon, Kimyeong Eom
  • Patent number: 9000414
    Abstract: An object of the present invention is to provide a light emitting diode having a heterogeneous material structure and a method of manufacturing thereof, in which efficiency of extracting light to outside is improved by forming depressions and prominences configured of heterogeneous materials different from each other before or in the middle of forming a semiconductor material on a substrate in order to improve the light extraction efficiency.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 7, 2015
    Assignee: Korea Photonics Technology Institute
    Inventors: Sang-Mook Kim, Jong-Hyeob Baek
  • Patent number: 8927960
    Abstract: A light emitting device including a substrate, a first conductive type semiconductor layer on the substrate, at least one InxGa1?xN layer (0<x<0.2) on the first conductive type semiconductor layer, at least one GaN layer directly on the at least one InxGa1?N layer (0<x<0.2), an active layer on the at least one GaN layer, a second conductive type semiconductor layer on the active layer, and a transparent ITO (Indium-Tin-Oxide) layer on the second conductive type semiconductor layer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 6, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Seong Jae Kim
  • Patent number: 8928017
    Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-hee Chae, Young-soo Park, Bok-ki Min, Jun-youn Kim, Hyun-gi Hong
  • Patent number: 8907359
    Abstract: An optoelectronic semiconductor component comprising a semiconductor layer sequence (3) based on a nitride compound semiconductor and containing an n-doped region (4), a p-doped region (8) and an active zone (5) arranged between the n-doped region (4) and the p-doped region (8) is specified. The p-doped region (8) comprises a p-type contact layer (7) composed of InxAlyGa1-x-yN where 0?x?1, 0?y?1 and x+y?1. The p-type contact layer (7) adjoins a connection layer (9) composed of a metal, a metal alloy or a transparent conductive oxide, wherein the p-type contact layer (7) has first domains (1) having a Ga-face orientation and second domains (2) having an N-face orientation at an interface with the connection layer (9).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Martin Strassburg, Lutz Höppel, Matthias Peter, Ulrich Zehnder, Tetsuya Taki, Andreas Leber, Rainer Butendeich, Thomas Bauer
  • Patent number: 8890196
    Abstract: A solid-state light source has light emitting diodes embedded in a thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element has optically translucent thermal filler and at least one luminescent element in a matrix material. A leadframe is electrically connected to the light emitting diodes. The leadframe distributes heat from the light emitting diodes to the thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element distributes heat from light emitting diodes and the thermally conductive translucent luminescent element.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 18, 2014
    Assignee: Goldeneye, Inc.
    Inventors: Scott M. Zimmerman, William R. Livesay, Richard L. Ross, Eduardo DeAnda
  • Patent number: 8878216
    Abstract: A light emitting diode (LED) module includes a substrate, an LED disposed on the substrate, a phosphor layer disposed on the LED, and a lens disposed on the substrate. The substrate has a recess defined therein. The lens is fastened to the substrate through the recess. A manufacturing method for the LED includes forming the recess in the substrate, mounting the LED on the substrate, forming the phosphor layer on the LED, and forming the lens directly on the substrate such that the lens is fastened to the substrate through the recess.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Sung You
  • Patent number: 8748930
    Abstract: The manufacturing method of the light-emitting device is provided in which an auxiliary electrode in contact with an electrode formed using a transparent conductive film of a light-emitting element is formed using a mask, and direct contact between the auxiliary electrode and an EL layer is prevented by oxidizing the auxiliary electrode. Further, the light-emitting device manufactured according to the method and the lighting device including the light-emitting device are provided.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Kohei Yokoyama, Satoshi Seo
  • Patent number: 8729598
    Abstract: The present invention provides a light-emitting diode that includes two electrodes provided on a light-emitting surface, and exhibits high light extraction efficiency and high-brightness.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: May 20, 2014
    Assignee: Showa Denko K.K.
    Inventors: Wataru Nabekura, Ryouichi Takeuchi
  • Patent number: 8680509
    Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1-xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
  • Publication number: 20140077234
    Abstract: An apparatus comprises a substrate, a first buried layer formed over the substrate, the first buried layer comprising one or more raised mesa structures, a second buried layer formed over the first buried layer, an active layer formed over the second buried layer, and a capping layer formed over the active layer. The apparatus may further comprise a third buried layer formed over the active layer, the third buried layer comprising one or more raised mesa structures, and a fourth buried layer formed over the third buried layer. The one or more raised mesa structures of the first buried layer may be offset from the one or more raised mesa structures of the third buried layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: LSI Corporation
    Inventor: Joseph M. Freund
  • Patent number: 8558246
    Abstract: A light emitting diode includes: a light emitting diode chip including a substrate and a light emission structure disposed on the substrate; and a phosphor layer formed to cover at least one surface of a diode upper surface and a diode lower surface, when a surface formed by the light emitting diode chip, when viewed from above the light emission structure, is defined as the diode upper surface and a surface formed by the light emitting diode chip, when viewed from below the substrate is defined as the diode lower surface. The phosphor layer is formed in a manner such that the phosphor layer does not deviate from the diode upper surface or the diode lower surface and has a flat surface parallel to the diode upper surface or the diode lower surface and a curved surface connecting the flat surface to corners of the diode upper surface or the diode lower surface.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Ha Kim, Kyu Sang Kim, Jae Yoo Jeong, Chung Bae Jeon
  • Patent number: 8546156
    Abstract: A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the second contact metal layer; a diffusion barrier layer deposed on the bonding layer, wherein the permanent substrate, the bonding layer and the diffusion barrier layer are electrically conductive; a reflective metal layer deposed on the diffusion barrier layer; a transparent conductive oxide layer deposed on the reflective metal layer; an illuminant epitaxial structure deposed on the transparent conductive oxide layer, wherein the illuminant epitaxial structure includes a first surface and a second surface opposite to the first surface; and a second conductivity type compound electrode pad deposed on the second surface of the illuminant epitaxial structure.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: October 1, 2013
    Assignee: Epistar Corporation
    Inventor: Schang-Jing Hon
  • Patent number: 8530257
    Abstract: Methods for improving the temperature performance of AlInGaP based light emitters. Nitrogen is added to the quantum wells in small quantities. Nitrogen is added in a range of about 0.5 percent to 2 percent. The addition of nitrogen increases the conduction band offset and increases the separation of the indirect conduction band. To keep the emission wavelength in a particular range, the concentration of In in the quantum wells may be decreased or the concentration of Al in the quantum wells may be increased. The net result is an increase in the conduction band offset and an increase in the separation of the indirect conduction band.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 10, 2013
    Assignee: Finisar Corporation
    Inventor: Ralph Herbert Johnson
  • Patent number: 8507929
    Abstract: One or more regions of graded composition are included in a III-P light emitting device, to reduce the Vf associated with interfaces in the device. In accordance with embodiments of the invention, a semiconductor structure comprises a III-P light emitting layer disposed between an n-type region and a p-type region. A graded region is disposed between the p-type region and a GaP window layer. The aluminum composition is graded in the graded region. The graded region may have a thickness of at least 150 nm. In some embodiments, in addition to or instead of a graded region between the p-type region and the GaP window layer, the aluminum composition is graded in a graded region disposed between an etch stop layer and the n-type region.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: August 13, 2013
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Patrick N. Grillot, Rafael I. Aldaz, Eugene I. Chen, Sateria Salim
  • Patent number: 8476649
    Abstract: Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 8441037
    Abstract: An objective is to provide a semiconductor device capable of utilizing properties of a high-mobility electron transport layer with a thin film stacked structure having large ?Ec, high electron mobility, and simplified element fabrication process even when the substrate material and the electron transport layer greatly differ in lattice constant. The semiconductor device includes: a semiconductor substrate (1); a first barrier layer (2) on the substrate (1); an electron transport layer (3) on the first barrier layer (2); and a second barrier layer (4) on the electron transport layer (3). The first barrier layer (2) has an InxAl1-xAs layer. At least one of the first barrier layer (2) and the second barrier layer (4) has a stacked structure having an AlyGa1-yAszSb1-z layer in contact with the electron transport layer (3) and an InxAl1-xAs layer in contact with the AlyGa1-yAszSb1-z layer. The stacked structure is doped with a donor impurity.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 14, 2013
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Hirotaka Geka
  • Publication number: 20130100978
    Abstract: An (Al,In,B,Ga)N based device including a plurality of (Al,In,B,Ga)N layers overlying a semi-polar or non-polar GaN substrate, wherein the (Al,In,B,Ga)N layers include at least a defected layer, a blocking layer, and an active region, the blocking layer is between the active region and the defected layer of the device, and the blocking layer has a larger band gap than surrounding layers to prevent carriers from escaping the active region to the defected layer. One or more (AlInGaN) device layers are above and/or below the (Al,In,B,Ga)N layers. Also described is a nonpolar or semipolar (Al,In,B,Ga)N based optoelectronic device including at least an active region, wherein stress relaxation (Misfit Dislocation formation) is at heterointerfaces above and/or below the active region.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 25, 2013
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: The Regents of the University of California
  • Patent number: 8373174
    Abstract: The present III-nitride semiconductor light-emitting device comprises: a first III-nitride semiconductor layer having a first conductivity type; a second III-nitride semiconductor layer having a second conductivity type different from the first conductivity type; an active layer disposed between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer and generating light by recombination of electrons and holes; and a depletion barrier layer brought into contact with the active layer and having a first conductivity type.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 12, 2013
    Assignee: Semicon Light Co., LTD
    Inventors: Soo Kun Jeon, Eun Hyun Park, Jun Chun Park
  • Publication number: 20130015492
    Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.
    Type: Application
    Filed: September 6, 2012
    Publication date: January 17, 2013
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
  • Patent number: 8354689
    Abstract: Light emitting devices described herein include dopant front loaded tunnel barrier layers (TBLs). A front loaded TBL includes a first surface closer to the active region of the light emitting device and a second surface farther from the active region. The dopant concentration in the TBL is higher near the first surface of the TBL when compared to the dopant concentration near the second surface of the TBL. The front loaded region near the first surface of the TBL is formed during fabrication of the device by pausing the growth of the light emitting device before the TBL is formed and flowing dopant into the reaction chamber. After the dopant flows in the reaction chamber during the pause, the TBL is grown.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: January 15, 2013
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Zhihong Yang
  • Patent number: 8323994
    Abstract: A method for producing a Group III nitride semiconductor light-emitting device with a face-up configuration including a p-type layer and a transparent electrode composed of ITO is provided in which a p-pad electrode on the transparent electrode and an n-electrode on an n-type layer are simultaneously formed. The p-pad electrode and the n-electrode are composed of Ni/Au. The resultant structure is heat treated at 570° C. and good contact can be established in the p-pad electrode and the n-electrode. The heat treatment also provides a region in the transparent electrode immediately below the p-pad electrode, the region and the p-type layer having a higher contact resistance than that of the other region of the transparent electrode and the p-type layer. Thus, a region of an active layer below the provided region does not emit light and hence the light-emitting efficiency of the light-emitting device can be increased.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masao Kamiya, Takashi Hatano
  • Patent number: 8299480
    Abstract: A semiconductor light emitting device includes: an upper growth layer including a light emitting layer; a transparent substrate through which a radiant light from the light emitting layer passes; and a foundation layer provided between the upper growth layer and the transparent substrate, the foundation layer having a surface-controlling layer and a bonding layer bonded with the transparent substrate. The surface-controlling layer is made of compound semiconductor including at least Ga and As. The upper growth layer is formed on an upper surface of the surface-controlling layer. A lattice constant difference at an interface between the surface-controlling layer and the upper growth layer is smaller than that at an interface between the bonding layer and the transparent substrate.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryo Saeki, Katsufumi Kondo, Yasuo Idei
  • Patent number: 8294179
    Abstract: An optical device has a structured active region configured for selected wavelengths of light emissions.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: October 23, 2012
    Assignee: Soraa, Inc.
    Inventor: James W. Raring
  • Patent number: 8269236
    Abstract: A light-emitting diode (10) has a light-extracting surface and includes a transparent substrate (14), a compound semiconductor layer (13) bonded to the transparent substrate, a light-emitting part (12) contained in the compound semiconductor layer, a light-emitting layer (133) contained in the light-emitting part and formed of (AlXGa1-X)YIn1-YP(0?X?1, 0<Y?1), first and second electrodes (15, 16) of different polarities provided on a surface of the light-emitting diode opposite the light-extracting surface, and a reflecting metal film (17) formed on the first electrode. The transparent substrate has a first side face (142) virtually perpendicular to a light-emitting surface of the light-emitting layer on a side near the light-emitting layer and a second side face (143) oblique to the light-emitting surface on a side distant from the light-emitting layer. The first and second electrodes are mounted respectively on electrode terminals (43, 44).
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: September 18, 2012
    Assignee: Showa Denko K.K.
    Inventor: Masao Arimitsu
  • Publication number: 20120175589
    Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1?xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.
    Type: Application
    Filed: August 23, 2010
    Publication date: July 12, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
  • Patent number: 8124993
    Abstract: A method of texturing a surface within or immediately adjacent to a template layer of a LED is described. The method uses a texturing laser directed through a substrate to decompose and pit a semiconductor material at the surface to be textured. By texturing the surface, light trapping within the template layer is reduced. Furthermore, by patterning the arrangement of pits, metal coating each pit can be arranged to spread current through the template layer and thus through the n-doped region of a LED.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: February 28, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: David P Bour, Clifford F Knollenberg, Christopher L Chua
  • Patent number: 8076685
    Abstract: A nitride semiconductor device includes an active layer formed between an n-type cladding layer and a p-type cladding layer, and a current confining layer having a conductive area through which a current flows to the active layer. The current confining layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed on and in contact with the first semiconductor layer and has a smaller lattice constant than that of the first semiconductor layer. The third semiconductor layer is formed on and in contact with the second semiconductor layer and has a lattice constant that is smaller than that of the first semiconductor layer and larger than that of the second semiconductor layer.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: December 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Satoshi Tamura, Ryo Kajitani
  • Patent number: 8071409
    Abstract: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T1, and the barrier layers are formed at a growth temperature T2, where T1<T2. Then, a second type doped semiconductor layer is formed on the light emitting layer.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: December 6, 2011
    Assignee: Lextar Electronics Corp.
    Inventors: Te-Chung Wang, Chun-Jong Chang, Kun-Fu Huang
  • Publication number: 20110284890
    Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 24, 2011
    Applicants: PHILIPS LUMILEDS LIGHTING COMPANY, LLC, KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Andrew Y. KIM, Patrick N. GRILLOT
  • Publication number: 20110233516
    Abstract: In an optical semiconductor device including a support body, semiconductor layers made of (AlzGa1-z)1-xInxP (0?z?1, 0?x?1) having a light emitting layer provided above the support body, a first ohmic electrode layer provided on the semiconductor layers on the side of the support body, and a second ohmic electrode layer provided on the semiconductor layers, one of the semiconductor layers on the side of the second ohmic electrode layer has a protrusion structure including a plurality of parallelogram cells whose protrusion edges are connected to form ridges in a mesh shape. The first and second ohmic electrode layers have first and second line-shaped portions, respectively, in parallel with each other and distant from each other viewed from a thickness direction of the semiconductor layers. A longer diagonal line of each of the parallelogram cells is perpendicular to the first and second line-shaped portions of the first and second ohmic electrode layers.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventor: Takuya KAZAMA
  • Patent number: 8013323
    Abstract: A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: September 6, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sung Chul Choi
  • Patent number: 7982205
    Abstract: A III-V group compound semiconductor light-emitting diode, containing a substrate 1 having plural crystal planes, and a grown layer formed on the substrate by epitaxial growth, the grown layer at least including a barrier layer 2 and 3 and an active layer 8, wherein at least the active layer of the grown layer has plural crystal planes each having a different bandgap energy in the in-plane direction, and an Ohmic electrode 4 for current injection is formed on a crystal plane (3) having a higher bandgap energy among the plural crystal planes.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 19, 2011
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Xue-Lun Wang
  • Patent number: 7935974
    Abstract: The invention relates to a monolithic white light emitting device using wafer bonding or metal bonding. In the invention, a conductive submount substrate is provided. A first light emitter is bonded onto the conductive submount substrate by a metal layer. In the first light emitter, a p-type nitride semiconductor layer, a first active layer, an n-type nitride semiconductor layer and a conductive substrate are stacked sequentially from bottom to top. In addition, a second light emitter is formed on a partial area of the conductive substrate. In the second light emitter, a p-type AlGaInP-based semiconductor layer, an active layer and an n-type AlGaInP-based semiconductor layer are stacked sequentially from bottom to top. Further, a p-electrode is formed on an underside of the conductive submount substrate and an n-electrode is formed on a top surface of the n-type AlGaInP-based semiconductor layer.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 3, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Min Ho Kim, Masayoshi Koike, Kyeong Ik Min, Myong Soo Cho
  • Patent number: 7928448
    Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: April 19, 2011
    Inventors: Jonathan J. Wierer, Jr., John E. Epler
  • Publication number: 20110073870
    Abstract: The present III-nitride semiconductor light-emitting device comprises: a first III-nitride semiconductor layer having a first conductivity type; a second III-nitride semiconductor layer having a second conductivity type different from the first conductivity type; an active layer disposed between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer and generating light by recombination of electrons and holes; and a depletion barrier layer brought into contact with the active layer and having a first conductivity type.
    Type: Application
    Filed: March 29, 2010
    Publication date: March 31, 2011
    Applicant: SEMICON LIGHT CO., LTD
    Inventors: Soo Kun JEON, Eun Hyun PARK, Jun Chun PARK
  • Publication number: 20110062413
    Abstract: A light-emitting diode includes a substrate, a compound semiconductor layer including a p-n junction-type light-emitting part formed on the substrate, an electric conductor disposed on the compound semiconductor layer and formed of an electrically conductive material optically transparent to the light emitted from the light-emitting part and a high resistance layer possessing higher resistance than the electric conductor and provided in the middle between the compound semiconductor layer and the electric conductor. In the configuration of a light-emitting diode lamp, the electric conductor and the electrode disposed on the semiconductor layer on the side opposite to the electric conductor across the light-emitting layer are made to assume an equal electric potential by means of wire bonding. The light-emitting diode abounds in luminance and excels in electrostatic breakdown voltage.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: SHOWA DENKO K.K.
    Inventors: Ryouichi TAKEUCHI, Atsushi MATSUMURA, Takashi WATANABE
  • Patent number: 7880187
    Abstract: Radiation occurs when current is injected into an active layer from electrodes. A pair of clad layers is disposed sandwiching the active layer, the clad layer having a band gap wider than a band gap of the active layer. An optical absorption layer is disposed outside at least one clad layer of the pair of clad layers. The optical absorption layer has a band gap wider than the band gap of the active layer and narrower than the band gap of the clad layer. A spread of a spectrum of radiated light can be narrowed.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: February 1, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ken Sasakura, Keizo Kawaguchi, Hanako Ono
  • Patent number: 7842531
    Abstract: A gallium nitride-based device has a first GaN layer and a type II quantum well active region over the GaN layer. The type II quantum well active region comprises at least one InGaN layer and at least one GaNAs layer comprising 1.5 to 8% As concentration. The type II quantum well emits in the 400 to 700 nm region with reduced polarization affect.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: November 30, 2010
    Assignee: Lehigh University
    Inventors: Nelson Tansu, Ronald A. Arif, Yik Khoon Ee
  • Patent number: 7834343
    Abstract: A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: November 16, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sung Chul Choi
  • Publication number: 20100285626
    Abstract: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T1, and the barrier layers are formed at a growth temperature T2, where T1<T2. Then, a second type doped semiconductor layer is formed on the light emitting layer.
    Type: Application
    Filed: August 18, 2009
    Publication date: November 11, 2010
    Applicant: LEXTAR ELECTRONICS CORP.
    Inventors: Te-Chung Wang, Chun-Jong Chang, Kun-Fu Huang
  • Publication number: 20100276709
    Abstract: A method for manufacturing a compound semiconductor substrate includes at least the processes of epitaxially growing a quaternary light emitting layer composed of AlGaInP on a GaAs substrate; vapor-phase growing a p-type GaP window layer on a first main surface of the quaternary light emitting layer, the first main surface being opposite to the GaAs substrate; removing the GaAs substrate; and epitaxially growing an n-type GaP window layer on a second main surface of the light emitting layer, the second main surface being located at a side where the GaAs substrate is removed. The method includes the process of performing a heat treatment under a hydrogen atmosphere containing ammonia after the process of removing the GaAs substrate and before the process of epitaxially growing the n-type GaP window layer.
    Type: Application
    Filed: January 14, 2009
    Publication date: November 4, 2010
    Applicant: SHIN-ETSU HANDOTAI, CO. LTD.
    Inventors: Yukari Suzuki, Jun Ikeda, Masataka Watanabe
  • Patent number: 7811838
    Abstract: A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the second contact metal layer; a diffusion barrier layer deposed on the bonding layer, wherein the permanent substrate, the bonding layer and the diffusion barrier layer are electrically conductive; a reflective metal layer deposed on the diffusion barrier layer; a transparent conductive oxide layer deposed on the reflective metal layer; an illuminant epitaxial structure deposed on the transparent conductive oxide layer, wherein the illuminant epitaxial structure includes a first surface and a second surface opposite to the first surface; and a second conductivity type compound electrode pad deposed on the second surface of the illuminant epitaxial structure.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 12, 2010
    Assignee: Epistar Corporation
    Inventor: Schang-Jing Hon
  • Patent number: 7795631
    Abstract: A light-emitting device, including a compound semiconductor layer disposed on a substrate, includes a light-emitting layer, and a dielectric constant change structure formed in a part of the compound semiconductor layer including a main surface as a light extraction surface of the compound semiconductor layer. The dielectric constant change structure is devoid of revolution symmetry provided by randomly changing a periodicity of a dielectric constant in a two-dimensional lattice pattern, with respect to a photonic crystal structure in which more than two kinds of materials having different dielectric constants are periodically and alternately disposed on the main surface in the two-dimensional lattice pattern.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: September 14, 2010
    Assignee: Hitachi Cable, Ltd.
    Inventor: Katsuya Akimoto
  • Patent number: 7781245
    Abstract: A process for the semiconductor laser diode is disclosed, which prevents the abnormal growth occurred at the second growth for the burying region of the buried hetero structure. The ICP (Induction-Coupled Plasma) CVD apparatus forms a silicon oxide file with a thickness of above 2 ?m as adjusting the bias power PBIAS. Patterning the silicon oxide mask and dry-etching the semiconductor layers, a mesa structure including the active layer may be formed. As leaving the patterned silicon oxide film, the second growth for the burying region buries the mesa structure. The residual stress of the silicon oxide film is ?250 to ?150 MPa at a room temperature, while, it is ?200 to 100 MPa at temperatures from 500 to 700° C.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: August 24, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeshi Kishi, Tetsuya Hattori, Kazunori Fujimoto
  • Publication number: 20100135349
    Abstract: Semiconductor structures and devices based thereon include an aluminum nitride single-crystal substrate and at least one layer epitaxially grown thereover. The epitaxial layer may comprise at least one of AlN, GaN, InN, or any binary or tertiary alloy combination thereof, and have an average dislocation density within the semiconductor heterostructure is less than about 106 cm?2.
    Type: Application
    Filed: November 12, 2009
    Publication date: June 3, 2010
    Applicant: Crystal IS, Inc.
    Inventors: Leo J. Schowalter, Joseph A. Smart, Shiwen Liu, Kenneth E. Morgan, Robert T. Bondokov, Timothy J. Bettles, Glen A. Slack
  • Publication number: 20100123118
    Abstract: A LED epitaxial-Chip with patterned GaN based substrate is provided. The LED epitaxial-Chip includes a substrate, a butter layer formed on the substrate, unintentional doped intrinsic GaN layer formed on the substrate, n-GaN layer formed on the substrate, InGaN active layer formed on the substrate, multiple quantum well formed on the substrate; and p-GaN layer formed on the sapphire substrate. The substrate has DBR reflection layer formed thereon. The DBR reflection layer is layered structure grown by two materials having different refractive index periodically alternate. The reflection layer forms at least two spaced patterned structures on the substrate. A manufacturing method of LED epitaxial-Chip with patterned GaN based substrate is also provided.
    Type: Application
    Filed: April 28, 2009
    Publication date: May 20, 2010
    Applicant: Shenzhen Century Epitech LEDs Co., Ltd.
    Inventors: Jiahui Hu, Kuo-Hsiung Chu, Hsuan-Liang Wu, Chih-Chiang Shen
  • Patent number: 7709287
    Abstract: A method of forming a multijunction solar cell includes providing a substrate, forming a first subcell by depositing a nucleation layer over the substrate and a buffer layer including gallium arsenide (GaAs) over the nucleation layer, forming a middle second subcell having a heterojunction base and emitter disposed over the first subcell and forming first and second tunnel junction layers between the first and second subcells. The first tunnel junction layer includes GaAs over the first subcell and the second tunnel junction layer includes aluminum gallium arsenide (AlGaAs) over the first tunnel junction layer. The method further includes forming a third subcell having a homojunction base and emitter disposed over the middle subcell.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: May 4, 2010
    Assignee: Emcore Solar Power, Inc.
    Inventors: Navid Fatemi, Daniel J. Aiken, Mark A. Stan
  • Publication number: 20100078660
    Abstract: An n-type layer of a light-emitting device has a structure in which a first n-type layer, a second n-type layer and a third n-type layer are sequentially laminated in this order on a sapphire substrate, and an n-electrode composed of V/Al is formed on the second n-type layer. The first n-type layer and the second n-type layer are n-GaN, and the third n-type layer is n-InGaN. The n-type impurity concentration of the second n-type layer is higher than that of the first n-type layer and the third n-type layer.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Miki Moriyama, Koichi Goshonoo
  • Patent number: 7678596
    Abstract: First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser. First and second ridges are formed in the first and second semiconductor lasers by dry etching, using a resist as a mask, and the dry etching is stopped when a second etching stopper layer is exposed at the second ridge. The second upper cladding layer remaining on a first etching stopper layer at the first ridge is selectively removed by wet etching, using the resist as a mask.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 16, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Nobuyuki Kasai