Electrical Contact Or Lead (e.g., Lead Frame) (epo) Patents (Class 257/E33.066)
  • Patent number: 8709838
    Abstract: There is provided a method for preparing a ?-SiAlON phosphor capable of be controlled to show characteristics such as high brightness and desired particle size distribution. The method for preparing a ?-SiAlON phosphor represented by Formula: Si(6-x)AlxOyN(8-y):Lnz (wherein, Ln is a rare earth element, and the following requirements are satisfied: 0<x?4.2, 0<y?4.2, and 0<z?1.0) includes: mixing starting materials to prepare a raw material mixture; and heating the raw material mixture in a nitrogen-containing atmospheric gas, wherein the starting materials includes a host raw material including a silicon raw material including metallic silicon, and at least one aluminum raw material selected from the group consisting of metallic aluminum and aluminum compound, and at least activator raw material selected from the rare earth elements for activating the host raw material.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hideo Suzuki, Chul Soo Yoon, Hyong Sik Won, Jeong Ho Ryu, Youn Gon Park, Sang Hyun Kim
  • Patent number: 8704265
    Abstract: In one embodiment, the light emitting device package includes a package body, electrodes attached to the package body, and at least two light emitting devices electrically connected to the electrodes. Each light emitting device emits light of a different color from the other light emitting devices. A protective layer is formed over the at least two light emitting devices, and a phosphor layer formed over the protective layer. Other embodiments include other structures such a individual phosphor layers on each light emitting device. And, a light apparatus including a package may include a single driver driving the light emitting devices of the package.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: April 22, 2014
    Assignee: LG Electronics Inc.
    Inventors: Bu Wan Seo, Sung Woo Kim, Hoon Hur, Yong Suk Kim
  • Patent number: 8698169
    Abstract: An organic light emitting diode (OLED) display includes a first electrode including a conductive black layer, a second electrode facing the first electrode, and an organic emission layer provided between the first electrode and the second electrode.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyun-Eok Shin
  • Patent number: 8698159
    Abstract: A panel structure includes a transistor including a gate electrode, a source electrode and a drain electrode, a power source line, a pixel electrode, and one or more contact plugs formed of a same material as the pixel electrode and electrically connecting the power source line and the source electrode.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Myung-kwan Ryu, Kee-chan Park, Jong-baek Seon
  • Patent number: 8698188
    Abstract: The object of the invention is to improve the visual inspection yield of a semiconductor light emitting device. To achieve the object, a semiconductor light emitting device includes a semiconductor layer, a pad electrode on the layer, and a protection film covering at least the layer. The device includes at least one stopper arranged on a peripheral part of the pad electrode surface away from the film. The stopper has a semicircular arc shape opening toward the center of the pad electrode. In electrical/optical property inspection, if sliding on the pad electrode, a probe needle can be guided into the concave surface of the semicircular arc shape. The stopper can reliably hold the needle. It is avoidable that the needle contacts the film. It is preferable that each of positive/negative electrodes have the pad electrode, and a pair of stoppers be arranged in positions on the electrodes facing each other.
    Type: Grant
    Filed: March 5, 2011
    Date of Patent: April 15, 2014
    Assignee: Nichia Corporation
    Inventors: Yasutaka Hamaguchi, Yoshiki Inoue, Takahiko Sakamoto
  • Patent number: 8698186
    Abstract: An LED device with improved circuit board LED support structure is presented. A top surface of a thermally-conductive substrate of this LED device comprises a thermally-conductive pillar. The pillar is not covered with a dielectric layer and an LED package is arranged directly on the pillar with the LED packages bottom thermally-conductive plate in direct contact with the pillar top surface.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: April 15, 2014
    Assignee: Cofan USA, Inc.
    Inventors: Lac Nguyen, Chang Han
  • Patent number: 8692284
    Abstract: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 8, 2014
    Inventors: Ying-Nan Wen, Chien-Hung Liu, Wei-Chung Yang
  • Patent number: 8692285
    Abstract: A semiconductor light emitting device has a multilayer epitaxial structure for emitting light by a light emitting layer located between a first conductive layer and a second conductive layer. The multilayer epitaxial structure can be grown directly on a base substrate. A reflective layer can be provided in the multilayer epitaxial structure between the base substrate and the first conductive layer. A distributive Bragg reflector can be positioned adjacent the substrate. A surface of the multilayer epitaxial structure can be conformed to provide improved light extraction. A phosphorus film encapsulates the multilayer epitaxial structure and its respective side surfaces.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventor: Hideo Nagai
  • Patent number: 8692277
    Abstract: Light emitting diodes include a diode region comprising a gallium nitride-based n-type layer, an active region and a gallium nitride-based p-type layer. A substrate is provided on the gallium nitride-based n-type layer and optically matched to the diode region. The substrate has a first face remote from the gallium nitride-based n-type layer, a second face adjacent the gallium nitride-based n-type layer and a sidewall therebetween. At least a portion of the sidewall is beveled, so as to extend oblique to the first and second faces. A reflector may be provided on the gallium nitride-based p-type layer opposite the substrate. Moreover, the diode region may be wider than the second face of the substrate and may include a mesa remote from the first face that is narrower than the first face and the second face.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 8, 2014
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Robert C. Glass, Charles M. Swoboda, Bernd Keller, James Ibbetson, Brian Thibeault, Eric J. Tarsa
  • Patent number: 8686453
    Abstract: Provided is a light emitting device. The light emitting device comprises: In one embodiment, a light emitting device includes: a light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a conductive support member under the light emitting structure. The conductive support member comprises a first conductive support member and a second conductive support member. The second conductive support member has a thermal conductivity higher than that of the first conductive support member.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 1, 2014
    Assignee: LG Innotek Co.,, Ltd.
    Inventors: Jung Hyeok Bae, Young Kyu Jeong, Kyung Wook Park, Duk Hyun Park
  • Patent number: 8680546
    Abstract: A light-emitting apparatus of the present invention has (i) a semiconductor device which emits light toward a higher position than a substrate and (ii) a plurality of external connection terminals, and includes: a light-reflecting layer, provided on the substrate, which reflects the light emitted by the semiconductor device; and a covering layer which covers at least the light-reflecting layer and which transmits the light reflected by the light-reflecting layer. Further, the semiconductor device is provided on the covering layer, and is electrically connected to the external connection terminals via connecting portions, and the semiconductor device and the connecting portions are sealed with a sealing resin so as to be covered. Therefore, the light-emitting apparatus has increased efficiency with which light is taken out, and can prevent a reflecting layer from being altered, deteriorating, and decreasing in reflectance.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: March 25, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Konishi, Masaki Kondo, Takaaki Horio, Takanobu Matsuo, Toshio Hata, Kiyohisa Ohta
  • Patent number: 8680541
    Abstract: Disclosed is a light-emitting diode structure comprises a substrate, a plurality of light-emitting diodes on the substrate, and a conductive layer laid on the surface thereof. Each light-emitting diode comprises at least an electrical coupling side close to another electrical coupling side of an adjacent light-emitting diode. Each light-emitting diode comprises at least a first and a second electrode on the surface along the electrical coupling side, so that two close first or second electrodes can be soldered at the same time in wire soldering process, so as to make the light-emitting diodes connect in parallel. One end of the conductive layer is connected to the first electrode of a light-emitting diode and the other end is close to the second electrode of another light-emitting diode, so that the second electrode and the conductive layer can be soldered at the same time in wire soldering process, so as to make the light-emitting diodes connect in series.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 25, 2014
    Assignee: Epistar Corporation
    Inventor: Chih-Chiang Lu
  • Patent number: 8674387
    Abstract: A light emitting device is provided with a base member, an interconnect pattern disposed on an upper surface of the base member, a light reflecting layer comprising a first layer disposed on a part of the interconnect pattern and formed from a metal material, and a second layer made of a dielectric multilayer reflecting film made with stacked layers of dielectric films having different refractive indices and covering an upper surface and side surfaces of the first layer, a light emitting element chip fixed so as to face at least a part of the light reflecting layer, and a light transmissive sealing member sealing the light reflecting layer and the light emitting element chip.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: March 18, 2014
    Assignee: Nichia Corporation
    Inventor: Daisuke Sanga
  • Patent number: 8674488
    Abstract: A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: March 18, 2014
    Assignee: Carsem (M) SDN. BHD.
    Inventors: Yong Lam Wai, Chan Boon Meng, Phang Hon Keat
  • Publication number: 20140061680
    Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Martin F. Schubert
  • Patent number: 8664684
    Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: March 4, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Martin F. Schubert
  • Patent number: 8659050
    Abstract: Disclosed herein is a slim LED package. The slim LED package includes first and second lead frames separated from each other, a chip mounting recess formed on one upper surface region of the first lead frame by reducing a thickness of the one upper surface region below other upper surface regions of the first lead frame, an LED chip mounted on a bottom surface of the chip mounting recess and connected with the second lead frame via a bonding wire, and a transparent encapsulation material protecting the LED chip while supporting the first and second lead frames.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 25, 2014
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Eun Jung Seo
  • Patent number: 8653540
    Abstract: An optoelectronic semiconductor body includes a semiconductor layer sequence which has an active layer suitable for generating electromagnetic radiation, and a first and a second electrical connecting layer. The semiconductor body is provided for emitting electromagnetic radiation from a front side. The first and the second electrical connecting layer are arranged at a rear side opposite the front side and are electrically insulated from one another by means of a separating layer. The first electrical connecting layer, the second electrical connecting layer and the separating layer laterally overlap and a partial region of the second electrical connecting layer extends from the rear side through a breakthrough in the active layer in the direction of the front side. Furthermore, a method for producing such an optoelectronic semiconductor body is specified.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 18, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Engl, Patrick Rode, Lutz Hoeppel, Matthias Sabathil
  • Patent number: 8653541
    Abstract: A semiconductor device including a plurality of circuits that includes a transistor, where a semiconductor layer forming the transistor includes a first contact pad, a first part that is connected to the first contact pad and that extends in a direction intersecting a short direction of a pitch with which the circuits are arranged, a second part that extends from the first part in the short direction, and a second contact pad including the first part and the second part that are provided between the first contact pad and the second contact pad, where the second part overlaps an electrode layer across an insulating layer.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: February 18, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kouji Ikeda, Takanori Yamashita, Masami Iseki
  • Patent number: 8653545
    Abstract: A semiconductor light emitting device that includes a first conductive type semiconductor layer, a first electrode, a insulating layer, and an electrode layer. The first electrode has at least one branch on the first conductive type semiconductor layer. The insulating layer is disposed on the first electrode. The electrode layer is disposed on the insulating layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 18, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Woo Sik Lim, Sung Ho Choo
  • Patent number: 8648383
    Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, a first electrode disposed in an opening portion of the light emitting structure and contacted with a portion of the first conductive type semiconductor layer, an insulating layer covering the first electrode, a second electrode disposed on the insulating layer and connected to the second conductive type semiconductor layer, a first electrode layer under the second electrode.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Woo Sik Lim, Sung Ho Choo, Byeong Kyun Choi
  • Publication number: 20140034952
    Abstract: The present invention provides a manufacturing method for array substrate, including: forming a first conductive layer, a first isolator layer, a second conductive layer and a second isolator layer on a substrate from bottom up, the first conductive layer for forming electrically connected scan line and control terminal of switch transistor, performing dry etch on the second isolator layer to form via hole, and forming a third conductive layer on the second isolator layer for forming data line. The present invention also provides an arrays substrate and a liquid crystal display device. As such, the present invention can reduce the possibility of electrostatic explosion during array substrate manufacturing process and improve the yield rate of array substrate.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventor: Cheng-hung Chen
  • Patent number: 8643029
    Abstract: Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type semiconductor layer located on a portion of the N-type semiconductor layer. The plurality of light emitting cells are bonded to a submount substrate. Accordingly, heat generated from the light emitting cells can be easily dissipated, so that a thermal load on the light emitting device can be reduced. Meanwhile, since the plurality of light emitting cells are electrically connected using connection electrodes or electrode layers formed on the submount substrate, it is possible to provide light emitting cell arrays connected to each other in series.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: February 4, 2014
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Chung Hoon Lee, Lacroix Yves, Hyung Soo Yoon, Young Ju Lee
  • Patent number: 8642395
    Abstract: A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhe Li, Qingchun He, Guanhua Wang, Zhijie Wang, Nan Xu
  • Patent number: 8643048
    Abstract: Disclosed is a light emitting device. The light emitting device includes a light emitting structure comprising a first area comprising a first semiconductor layer doped with a first dopant, a second semiconductor layer doped with a second dopant and a first active layer, and a second area comprising a third semiconductor layer doped with the first dopant and comprising an exposed region, a fourth semiconductor layer arranged on the third semiconductor layer except for the exposed region and doped with the second dopant and a second active layer, and provided with first and second trenches formed from the fourth semiconductor layer to the first semiconductor layer and separated from each other, a first electrode comprising first and second electrode pad, a second electrode, and a third electrode arranged on the fourth semiconductor layer and comprising a third electrode pad, a fourth electrode pad and a fifth electrode pad.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 4, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sungmin Hwang
  • Patent number: 8643035
    Abstract: A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: February 4, 2014
    Assignee: LG Electronics Inc.
    Inventors: Jong Wook Kim, Hyun Kyong Cho, Gyu Chul Yi, Sung Jin An, Jin Kyoung Yoo, Young Joon Hong
  • Patent number: 8643054
    Abstract: A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and a second branch extending from the first branch; an electrical contact structure between the second branch and the semiconductor light-emitting stack and having a first width; and a current blocking structure located right beneath the electrical contact structure and having a second width larger than the first width.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 4, 2014
    Assignee: Epistar Corporation
    Inventors: Chien-Fu Huang, Min-Hsun Hsieh, Chih-Chiang Lu, Chia-Liang Hsu, Shih-I Chen
  • Patent number: 8642388
    Abstract: A method for manufacturing LEDs includes following steps: forming circuit structures on a substrate, each circuit structure having a first metal layer and a second metal layer formed on opposite surfaces of the substrate and a connecting section interconnecting the first and second metal layers; cutting through each circuit structure along a middle of the connecting section to form first and second electrical connecting portions insulated from each other via a gap therebetween; arranging LED chips on the substrate and electrically connecting the LED chips to the first and second electrical connecting portions; forming an encapsulation on the substrate to cover the LED chips; and cutting through the substrate and the encapsulation between the first and second electrical connecting portions of neighboring circuit structures to obtain the LEDs.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 4, 2014
    Assignee: Advanced Optoelectronics Technology, Inc.
    Inventor: Chao-Hsiung Chang
  • Patent number: 8637892
    Abstract: According to one embodiment, an LED package includes first and second lead frames, an LED chip and a resin body. The first and second lead frames are apart from each other. The LED chip is provided above the first and second lead frames, the LED chip includes a semiconductor layer which contains at least indium, gallium and aluminum, one terminal of the LED chip is connected to the first lead frame, and another terminal of the LED chip is connected to the second lead frame. The resin body covers the LED chip and an entire upper surface, a part of a lower surface, and parts of edge surfaces of each of the first and second lead frames, and the resin body exposes a rest of the lower surface and a rest of the edge surfaces. And, an appearance of the resin body is a part of an appearance of the LED package.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Egoshi, Hiroaki Oshio, Teruo Takeuchi, Kazuhiro Inoue, Iwao Matsumoto, Satoshi Shimizu
  • Patent number: 8637897
    Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
  • Patent number: 8633506
    Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: January 21, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Masahiko Kobayakawa, Kazuhiro Mireba, Shintaro Yasuda, Junichi Itai, Taisuke Okada
  • Patent number: 8624288
    Abstract: An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: January 7, 2014
    Assignees: LG Electronics, Inc., LG Innotek Co., Ltd.
    Inventors: Jun Ho Jang, Jae Wan Choi, Duk Kyu Bae, Hyun Kyong Cho, Jong Kook Park, Sun Jung Kim, Jeong Soo Lee
  • Publication number: 20130334561
    Abstract: A method for bonding an LED wafer, a method for manufacturing an LED chip, and a bonding structure are provided. The method for bonding an LED wafer includes the following steps. A first metal film is formed on an LED wafer. A second metal film is formed on a substrate. A bonding material layer whose melting point is lower than or equal to about 110° C. is formed on the surface of the first metal film. The LED wafer is placed on the substrate. The bonding material layer is heated at a pre-solid reaction temperature for a pre-solid time to perform a pre-solid reaction. The bonding material layer is heated at a diffusion reaction temperature for a diffusing time to perform a diffusion reaction, wherein the melting points of the first and the second inter-metallic layers after diffusion reaction are higher than about 110° C.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Hsiu-Jen LIN, Jian-Shian Lin, Shau-Yi Chen, Jen-Hui Tsai
  • Patent number: 8610144
    Abstract: A semiconductor light emitting device that includes a first conductive type semiconductor layer, a first electrode, a insulating layer, and an electrode layer. The first electrode has at least one branch on the first conductive type semiconductor layer. The insulating layer is disposed on the first electrode. The electrode layer is disposed on the insulating layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: December 17, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Woo Sik Lim, Sung Ho Choo
  • Patent number: 8610141
    Abstract: The invention includes one or more LED elements, a silicon substrate on which the LED elements are mounted via micro bumps and internally formed wiring is connected to the micro bumps, a heat insulation organic substrate which is stuck to the opposite side of the LED elements-mounting side of the silicon substrate and has through-holes in which the wiring goes through, a chip-mounting substrate which is stuck to the opposite side of the silicon substrate side of the heat insulation organic substrate and internally formed wiring is connected to wiring in the through-holes of the heat insulation organic substrate, and an LED control circuit chip which is connected to the wiring of the chip-mounting substrate via micro bumps, and mounted via the micro bumps on the opposite side of the heat insulation organic substrate side of the chip-mounting substrate.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: December 17, 2013
    Assignee: Liquid Design Systems, Inc.
    Inventors: Naoya Tohyama, Takuya Inoue, Kouichi Kumagai, Takaha Kunieda
  • Patent number: 8610237
    Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Naoki Sakura
  • Patent number: 8610140
    Abstract: Packages, systems, and devices for light emitting diodes (LEDs) and related methods are provided. The packages can include a lead frame with an electrically conductive chip carrier comprising an upper surface. An LED can be placed on the upper surface of the electrically conductive chip carrier. A casing can be disposed on the lead frame covering at least a portion of the lead frame. A reflector cavity can be in the casing surrounding the LED. The reflector cavity can have angled side wall portions and angled end wall portions with an angle at which the side wall portions are angled that is different from an angle at which the end wall portions are angled.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 17, 2013
    Assignee: Cree, Inc.
    Inventors: Sung Chul Joo, Christopher P. Hussell
  • Patent number: 8610166
    Abstract: According to one embodiment, a light emitting device includes a first lead, a light emitting element, a second lead and a molded body. The light emitting element is fixed on the first lead. The second lead is provided away from the first lead and electrically connected to the light emitting element via a metal wire. The, molded body made of a sealing resin covers the light emitting element, end portions of the first lead and the second lead, the light emitting element being fixed on the end portion of the first read, and the metal wire being bonded on the end portion of the second lead. The first groove is provided between first and second portions in a front surface of the second lead, the first portion being in contact with an outer edge of the molded body and the metal wire being bonded on the second portion.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Takeshita, Yuichi Ikedo, Tetsuya Muranaka
  • Publication number: 20130320386
    Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Martin F. Schubert, Ming Zhang, Lifang Xu
  • Patent number: 8598617
    Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: December 3, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chih-Kuang Yu, Chyi Shyuan Chern, Hsing-Kuo Hsia, Hung-Yi Kuo
  • Patent number: 8598619
    Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
  • Patent number: 8598606
    Abstract: A mounting substrate for a semiconductor light emitting device includes a solid metal block having first and second opposing metal faces. The first metal face includes an insulating layer and a conductive layer on the insulating layer. The conductive layer is patterned to provide first and second conductive traces that connect to a semiconductor light emitting device. The second metal face may include heat sink fins therein. A flexible film including an optical element, such as a lens, also may be provided, overlying the semiconductor light emitting device.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: December 3, 2013
    Assignee: Cree, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 8592962
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 26, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Patent number: 8592857
    Abstract: An exemplary encapsulation structure for encapsulating an LED chip includes a first encapsulation, a second encapsulation and a transparent resin layer with phosphorous compounds doped therein. The first encapsulation defines a receiving room for receiving the LED chip therein. The second encapsulation defines a receiving space for receiving the first encapsulation therein. The second encapsulation is separated from the first encapsulation to define a clearance between the first encapsulation and the second encapsulation. The transparent resin layer is filled in the clearance. The transparent resin layer has a uniform thickness.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 26, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Shiun-Wei Chan, Chih-Hsun Ke
  • Patent number: 8586422
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 19, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R Camacho, Henry D Bathan, Lionel Chien Hui Tay, Amel Senosa Trasporto
  • Patent number: 8587014
    Abstract: The present invention provides a LED packaging structure, and more particularly to an innovative one designed with blind hole welding device. It at least comprises: a packaging body, which is provided with a wiring substrate; metal layers are separately arranged at both sides for coating the wiring substrate; the metal layers are divided into three portions, i.e. metal layer 1, 2, 3, according to the electrical connection point; a plurality of blind holes arranged at bottom of the wiring substrate, and then connected with metal layer 3; a single or a plurality of LED chips arranged onto the wiring substrate; a colloid coated on the LED chip; the packaging body is welded directly onto the substrate for electrical connection, so that LED chip is highlighted. The blind hole is arranged to facilitate the welding, helping to improve the electrical connection and welding performance.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: November 19, 2013
    Assignee: Kingbright Electronic Co., Ltd.
    Inventor: Wen-Joe Song
  • Patent number: 8587013
    Abstract: A semiconductor package structure includes an insulating substrate, a patterned conductive layer, a light emitting diode (LED) chip and a conductive connection part. The insulating substrate has an upper surface divided into an element configuration region and an element bonding region. The patterned conductive layer includes plural circuits located in the element configuration region and at least one bonding pad located in the element bonding region. The LED chip is flip chip bonded on the patterned conductive layer and electrically connected to the circuits. The conductive connection part has a first end point electrically connected to the bonding pad and a second end point electrically connected to an external circuit. The bonding pad and a corner of the LED chip are disposed correspondingly. A horizontal distance between an apex of the corner and the first end point of the conductive connection part is greater than or equal to 30 micrometers.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Genesis Photonics Inc.
    Inventors: Po-Jen Su, Chih-Ling Wu, Yi-Ru Huang, Yi-Ju Shih
  • Publication number: 20130299858
    Abstract: A light emitting device includes an active layer configured to provide light emission due to carrier recombination therein, a surface on the active layer, and an electrically conductive contact structure on the surface. The contact structure includes at least one plated contact layer. The contact structure may include a sublayer that conforms to the surface roughness of the underlying surface, and the plated contact layer may be substantially free of the surface roughness of the underlying surface. The surface of the plated contact layer may be substantially planar and/or otherwise configured to reflect the light emission from the active layer. Related fabrication methods are also discussed.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Inventors: Pritish Kar, David Beardsley Slater, JR., Matthew Donofrio, Brad Williams
  • Patent number: 8581291
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani
  • Patent number: 8581279
    Abstract: In a luminescence diode chip having a radiation exit area (1) and a contact structure (2, 3, 4) which is arranged on the radiation exit area (1) and comprises a bonding pad (4) and a plurality of contact webs (2, 3) which are provided for current expansion and are electrically conductively connected to the bonding pad (4), the bonding pad (4) is arranged in an edge region of the radiation exit area (1). The luminescence diode chip has reduced absorption of the emitted radiation (23) in the contact structure (2, 3, 4).
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: November 12, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Johannes Baur, Volker Härle, Berthold Hahn, Andreas Weimar, Raimund Oberschmid, Ewald Karl Michael Guenther, Franz Eberhard, Markus Richter, Jörg Strauss