Field-effect Device (e.g., Tft, Fet) (epo) Patents (Class 257/E51.005)
  • Patent number: 7489072
    Abstract: An organic electroluminescence display device and a method for fabricating the same is described. The organic electroluminescence display device comprises pixels defined by a gate line and a data line perpendicular to the gate line, a switching device and a driving device formed in the unit pixel, a first power line, a transparent electrode layer and a conductive electrode layer for supplying a driving signal to the driving device, a storage electrode overlapped with the first power line such that an insulating layer is interposed therebetween, and an organic electroluminescence layer.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: February 10, 2009
    Assignee: LG. Display Co., Ltd.
    Inventors: Joon-Young Yang, Jung-Il Lee
  • Publication number: 20090026443
    Abstract: A durable organic thin-film transistor and a method of manufacture thereof, the organic thin-film transistor having: a source electrode and a drain electrode arranged mutually separated; an organic semiconductor layer interposed between the source electrode and the drain electrode; and a gate electrode arranged to face said organic semiconductor layer which is between said source electrode and said drain electrode, with a gate insulating film being provided between said gate electrode and said organic semiconductor layer, wherein the gate insulating film includes an organic compound and particles of an inorganic compound dispersed in the organic compound, and a flattened film is provided between the source electrode and the drain electrode, or the gate electrode and the gate insulating film.
    Type: Application
    Filed: March 13, 2006
    Publication date: January 29, 2009
    Applicant: PIONEER CORPORATION
    Inventor: Satoru Ohta
  • Publication number: 20090020750
    Abstract: Apparatus including a support body; an organic semiconductor composition body on the support body, —and a first body including a hydrogenated vinylaromatic-diene block copolymer on the organic semiconductor composition body. Apparatus including a support body, —a first body including a hydrogenated vinylaromatic-diene block copolymer on the support body; and an organic semiconductor composition body on the first body. Techniques for making an apparatus.
    Type: Application
    Filed: September 28, 2006
    Publication date: January 22, 2009
    Applicant: BASF SE
    Inventors: Florian Doetz, Ingolf Hennig
  • Patent number: 7470951
    Abstract: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region (63) defined in said fin and in said horizontal region.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: December 30, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Jerry G. Fossum
  • Publication number: 20080300501
    Abstract: A gas analyser (12) comprises a transistor (1) that has a cavity (7) between its gate (2) and its organic semiconductor (6) based conducting channel. In operation a component from a gas sample introduced into the cavity (7) may absorb onto an exposed absorption sensitive surface portion of the organic semiconductor (6). A detector (13) detects a change in the threshold voltage of the transistor caused by the component absorbing on the exposed surface portion. In response to detecting this change, the detector generates a measurement signal indicative of a concentration of the component in the sample.
    Type: Application
    Filed: July 6, 2006
    Publication date: December 4, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Nicolaas Petrus Willard, Sepas Setayesh, Dagobert Michel De Leeuw
  • Publication number: 20080290339
    Abstract: The present invention is directed to manufacturing an organic transistor with an organic semiconductor film formed by a coating method, without involving a process of forming a rib for forming the organic semiconductor film. To be more specific, the organic transistor of the present invention includes: (1) a source electrode part and a drain electrode part which are formed on a substrate; (2) rib selectively formed on part of the source electrode part and the drain electrode part; (3) an organic semiconductor film placed in the region defined by the ribs and connecting the source electrode part and the drain electrode part; and (4) a gate electrode formed on the organic semiconductor film through a gate insulating film. The organic transistor of the present invention is characterized in that there is a gap between the rib formed on the source electrode part and the rib formed on the drain electrode part.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shuhei NAKATANI, Sadayoshi HOTTA, Hidehiro YOSHIDA
  • Publication number: 20080283825
    Abstract: A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode and a second dielectric region located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode.
    Type: Application
    Filed: April 5, 2005
    Publication date: November 20, 2008
    Inventors: Lay-Lay Chua, Peter Kian-Hoon Ho, Richard Henry Friend
  • Patent number: 7453087
    Abstract: A thin-film transistor including a channel layer being formed of an oxide semiconductor transparent to visible light and having a refractive index of nx, a gate-insulating layer disposed on one face of the channel layer, and a transparent layer disposed on the other face of the channel layer and having a refractive index of nt, where there is a relationship of nx>nt. A thin-film transistor including a substrate having a refractive index of no, a transparent layer disposed on the substrate and having a refractive index of nt, and a channel layer disposed on the transparent layer and having a refractive index of nx, where there is a relationship of nx>nt>no.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: November 18, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuya Iwasaki
  • Publication number: 20080265244
    Abstract: A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer.
    Type: Application
    Filed: December 2, 2005
    Publication date: October 30, 2008
    Inventors: Henning Sirringhaus, Seamus Burns
  • Patent number: 7432525
    Abstract: A transistor includes a first electrode, a second electrode, an organic layer provided between the first and second electrodes, and a third electrode for use to apply an electric field to the organic layer. The organic layer includes a polymer inclusion complex.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: October 7, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanobu Mizusaki, Motohiro Yamahara
  • Publication number: 20080237581
    Abstract: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a phase-separated dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the semiconductor layer.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Applicant: XEROX CORPORATION
    Inventors: Yiliang Wu, Hadi K. Mahabadi, Beng S. Ong, Paul F. Smith
  • Publication number: 20080230769
    Abstract: Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate, each of the first electrode and the second electrode comprising two electrode pads separated from each other and a heating element that connect the two electrode pads; a catalyst metal layer formed on the heating element of the first electrode; and a carbon nanotube connected to the second electrode by horizontally growing from the catalyst metal layer; wherein the heating elements are separated from the substrate by etching the substrate under the heating elements of the first and the second electrodes.
    Type: Application
    Filed: September 6, 2007
    Publication date: September 25, 2008
    Inventors: Jun-hee Choi, Andrei Zoulkarneev
  • Patent number: 7422933
    Abstract: A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma is decreased by forming an element having an LDD structure according to a manufacturing method of a semiconductor device using a hard mask. Covering the substrate by an electrically conductive film allover, the density of electric charge accumulated in a gate electrode in the plasma process such as anisotropic etching can be reduced, and the degradation due, to plasma process can be reduced.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: September 9, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Isikawa
  • Publication number: 20080197343
    Abstract: An electronic device, in particular an RFID transponder, comprises at least one logic gate, in which the logic gate is formed from a plurality of layers, which are applied on a common substrate, which layers comprise at least two electrode layers and at least one of the layers, in particular an organic layer, forms a semiconductor layer which is applied as a liquid, and an insulator layer and wherein the logic gate comprises at least two differently constructed field effect transistors. The field effect transistors are formed from a plurality of functional layers applied to a carrier substrate by printing or blade coating.
    Type: Application
    Filed: December 6, 2005
    Publication date: August 21, 2008
    Inventors: Robert Blache, Walter Fix, Jurgen Ficker
  • Publication number: 20080164464
    Abstract: The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the aforementioned functions, where wireless communication is not blocked by the internal structure. The semiconductor device of the invention has an organic memory provided with a memory cell array including a plurality of memory cells, a control circuit for controlling the organic memory, and a wire for connecting an antenna. Each of the plurality of memory cells has a transistor and a memory element. The memory element has a structure where an organic compound layer is provided between a first conductive layer and a second conductive layer. The second conductive layer is formed in a linear shape.
    Type: Application
    Filed: November 21, 2005
    Publication date: July 10, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kiyoshi Kato
  • Patent number: 7394097
    Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: July 1, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Kobayashi, Nobuhiro Nakamura, Ken Nakashima, Yuichi Masutani
  • Publication number: 20080145966
    Abstract: A method for fabricating organic thin-film transistors is disclosed. The method includes the steps of: providing a mold and a flexible substrate, wherein the mold comprises microstructures for defining source/drain electrode patterns on the substrate and at least an opening for feeding a solution material; forming an adhesive layer on the flexible substrate such that the mold is attached to the flexible substrate via the adhesive layer; feeding a solution material for forming source/drain electrodes via the opening of the mold and curing the solution material so as to form source/drain electrodes; removing the mold and forming a semiconductor layer on the source/drain electrodes; forming an insulator layer on the semiconductor layer and on the source/drain electrodes; forming a gate electrode on the insulator layer; and forming a protective layer for covering the organic thin-film transistor. The channel length of the thin film transistor is determined by the resolution of the microstructures of the mold.
    Type: Application
    Filed: October 24, 2007
    Publication date: June 19, 2008
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Min-Hua Yang, Meng-Che Chuang, Wei-Hsiang Lin, Yu-Hsuan Chen, Chun-Hao Hsu, Wen-Hsin Hsiao, Chih-Kung Lee, Wen-Jong Wu
  • Publication number: 20080135836
    Abstract: Semiconducting device and method of manufacturing a semiconducting device in which organic thin film transistors (TFTs) and other components are fabricated on a substrate (206), using a hybrid technology of lithographic and printing steps. A lithographically defined resist pattern (211, 311) provides barriers and cavities which serve to guide subsequently printed materials. Different components of the integrated circuitry form separate islands on the substrate (206). The risk of adjacent films cracking and peeling from stress is reduced. The flexibility of the device is increased.
    Type: Application
    Filed: November 4, 2005
    Publication date: June 12, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Gerwin H. Gelinck, Paulus C. Duineveld
  • Publication number: 20080128688
    Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed.
    Type: Application
    Filed: January 18, 2008
    Publication date: June 5, 2008
    Applicant: NANOSYS, INC.
    Inventors: Yaoling Pan, Francisco Leon, David P. Stumbo
  • Patent number: 7381990
    Abstract: A thin film transistor with multiple gates is fabricated using a super grain silicon (SGS) crystallization process. The thin film transistor a semiconductor layer formed in a zigzag shape on an insulating substrate, and a gate electrode intersecting with the semiconductor layer. The semiconductor layer has a high-angle grain boundary in a portion of the semiconductor layer that does not cross the gate electrode.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: June 3, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Woo-Young So
  • Publication number: 20080121876
    Abstract: A high electron mobility transistor is disclosed which has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer. A source, drain, and gate overlie the electron supply layer. Also formed on the electron supply layer is a surface-stabilizing organic semiconductor overlay which is of p conductivity type in contrast to the n type of the electron supply layer.
    Type: Application
    Filed: December 20, 2007
    Publication date: May 29, 2008
    Applicant: Sanken Electric Co., Ltd.
    Inventors: Koji Otsuka, Osamu Machida, Hitoshi Murofushi
  • Publication number: 20080121870
    Abstract: Briefly described, embodiments of this disclosure include transition-metal charge-transport materials, methods of forming transition-metal charge-transport materials, and methods of using the transition-metal charge-transport materials.
    Type: Application
    Filed: June 14, 2005
    Publication date: May 29, 2008
    Inventors: Marder Seth, Jian-Yang Cho, Bernard Kippelen, Benoit Domercq, Steve Barlow
  • Patent number: 7378303
    Abstract: A method for fabricating a thin film transistor is provided. A conductive layer is formed on a substrate. A patterned mask is formed on the conductive layer to cover a predetermined thin film transistor (TFT) area, and at least one portion of the conductive layer exposed by the patterned mask are removed. A laser is applied to form a laser hole in the patterned mask to expose a portion of the conductive layer and the laser hole substantially corresponds to a channel region of the predetermined TFT area. The exposed conductive layer is etched to form source and drain electrodes on opposite sides of the channel region.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 27, 2008
    Assignee: AU Optronics Corp.
    Inventors: Chih-Hung Shih, Ta-Wen Liao, Han-Tu Lin, Feng-Yuan Gan
  • Publication number: 20080111131
    Abstract: An organic thin film transistor (OTFT) includes an organic semiconductor layer on a substrate, source/drain electrodes spaced apart from each other on the substrate, a mixed layer between the source/drain electrodes and the organic semiconductor layer, the mixed layer including an organic material and a metal oxide or metal salt, and a gate electrode.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 15, 2008
    Inventor: Nam-Choul Yang
  • Publication number: 20080111128
    Abstract: Disclosed is a composition, an organic insulating film including the same, an organic thin film transistor including the organic insulating film, an electronic device including the organic thin film transistor and methods of fabricating the same. In the composition, an organic polymer material having a carboxyl group and an organic silane material having an electron-donating group are included to thus realize a structure which may further stabilize an unreacted crosslinking material. Thereby, a hysteresis phenomenon may be decreased and transparency may be increased, thus making it possible to assure stability upon exposure to air. Accordingly, the lifetime of the organic thin film transistor may be lengthened.
    Type: Application
    Filed: June 4, 2007
    Publication date: May 15, 2008
    Inventors: Jung Seok Hahn, Eun Kyung Lee, Sang Yoon Lee, Eun Jeong Jeong, Joo Young Kim
  • Publication number: 20080105868
    Abstract: The present invention provides an organic semiconductor device, which can be produced uniformly on a large substrate, having a high mobility and capable of greatly modulating the drain current by varying the voltage applied to a gate electrode. The present invention provides an organic semiconductor device having at least a substrate, an organic semiconductor, a gate insulating film and conductors, and having electrodes for applying bias, wherein a polymer layer, which is different from the gate insulating film, is provided in contact with the organic semiconductor, and the polymer layer is formed of a copolymer of methyl methacrylate and divinylbenzene, or the like; a process for producing the organic semiconductor device; and an organic semiconductor apparatus using the organic semiconductor device.
    Type: Application
    Filed: December 26, 2007
    Publication date: May 8, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Akira Unno, Naotake Sato, Hajime Miyazaki, Noriyuki Doi
  • Publication number: 20080087888
    Abstract: A method for easily forming a region with conductivity and high wettability without a step for removing a photocatalytic reaction layer, which is formed over a conductive layer, is proposed. The photocatalytic reaction layer is formed over a photocatalytic conductive layer, and the photocatalytic conductive layer is irradiated with ultraviolet light to form a region with conductivity and higher wettability than the photocatalytic reaction layer on a surface of the photocatalytic conductive layer which is irradiated with ultraviolet light. Note that for the photocatalytic conductive layer, a layer having a photocatalytic property of which resistivity is lower than or equal to 1×10?2 ? cm can be used.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 17, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masafumi Morisue
  • Publication number: 20080090325
    Abstract: A method for producing an organic field-effect transistor, comprising the steps of: a) providing a substrate comprising a gate structure, a source electrode and a drain electrode located on the substrate, and b) applying an n-type organic semiconducting compound to the area of the substrate where the gate structure, the source electrode and the drain electrode are located, wherein the n-type organic semiconducting compound is selected from the group consisting of compounds of the formula I wherein R1, R2, R3 and R4 are independently hydrogen, chlorine or bromine, with the proviso that at least one of these radicals is not hydrogen, Y1 is O or NRa, wherein Ra is hydrogen or an organyl residue, Y2 is O or NRb, wherein Rb is hydrogen or an organyl residue, Z1, Z2, Z3 and Z4 are O, where, in the case that Y1 is NRa, one of the residues Z1 and Z2 may be a NRc group, where Ra and Rc together are a bridging group having 2 to 5 atoms between the terminal bonds, where, in the case that Y2 is NRb, one of th
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Applicants: BASF Aktiengesellschaft, Stanford University
    Inventors: Martin KOENEMANN, Peter Erk, Zhenan Bao, Mang Mang Ling
  • Patent number: 7352004
    Abstract: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Hun Lee, Yang-Ho Bae, Beom-Seok Cho, Chang-Oh Jeong
  • Patent number: 7351606
    Abstract: An improved method of forming a semiconducting polymer layer protected by an insulating polymer layer is described. In the method, a material for forming a semiconducting polymer and an insulating polymer are dissolved in a solvent. The blended solution is deposited on a substrate where the semiconducting polymer and insulating polymer segregate. Upon evaporation of the solvent, the semiconducting material forms the active region of a TFT and the insulating polymer minimizes the exposure of the semiconducting polymer to air.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: April 1, 2008
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Ana C. Arias
  • Publication number: 20080073648
    Abstract: A thin film transistor array panel includes a gate electrode formed on a substrate, a gate insulator covering the gate electrode, a source electrode including a first transparent material and disposed on the gate insulator, a drain electrode including a second transparent material and disposed on the gate insulator, and an organic semiconductor formed on the source and drain electrodes, and the gate insulator therebetween. The source electrode includes a first boundary opposing a second boundary of the drain electrode relative to the gate electrode, and the opposing boundaries overlap boundaries of the gate electrode with an alignment margin in the range of about ?1 to +5 microns.
    Type: Application
    Filed: September 21, 2007
    Publication date: March 27, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Young CHOI, Bo-Sung KIM
  • Patent number: 7348655
    Abstract: An organic electro luminescence device is provided. A thin film transistor (TFT) is formed within a sub-pixel region defined by a gate line and a data line on a substrate. A passivation layer and a first electrode are sequentially formed on the substrate where the TFT is formed. A contact hole is formed at a predetermined portion of the passivation layer and the first electrode so as to expose a drain electrode of the TFT. An electrode separator and a buffer layer are misaligned with the gate line by a predetermined position, such that an emission region corresponding to the sub-pixel and a region including the contact hole of the TFT are separated. An organic electro luminescent layer is formed within a region defined by the buffer region. A second electrode is formed on the organic electrode luminescent layer and is connected to the drain electrode of the TFT through the contact hole.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: March 25, 2008
    Assignee: LG. Philips LCD. Co., Ltd
    Inventors: Sung Joon Bae, Jae Yoon Lee
  • Patent number: 7348593
    Abstract: An organic thin film transistor (OTFT) having an adhesive layer and a method of fabricating the same. The OTFT includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode and on remaining exposed portions of the substrate, an adhesive layer formed on the gate insulating layer, source/drain electrodes formed on the adhesive layer, and a semiconductor layer formed on the source/drain electrodes and on the adhesive layer. The gate insulating layer and the semiconductor layer are organic, the adhesive layer providing adhesion between the source/drain electrodes and the gate insulating film while preventing gate leakage current while also improving contact resistance.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: March 25, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Bon Koo, Min-Chul Suh
  • Publication number: 20080054257
    Abstract: A thin-film transistor and fabrication method thereof are provided. A controlled micro-line is formed by inkjet printing in combination with the coffee ring effect. At least two organic thin-film transistors are formed on two ring ridges of the coffee rings. For example, N-type and P-type soluble semiconductor materials may be formed on two adjacent ring ridges to form a complementary metal-oxide semiconductor (CMOS) device. Thus, the invention can simplify the process for fabricating thin-film transistors and increase their applications.
    Type: Application
    Filed: July 19, 2007
    Publication date: March 6, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsuan-Ming Tsai, Yuh-Zheng Lee, Chao-Kai Cheng, Jhih-Ping Lu, Kuo-Tong Lin
  • Patent number: 7335917
    Abstract: Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer and diffusing the crystallization inducing metal layer. The thin film transistor may include a crystallization inducing metal layer formed on an insulating substrate, a buffer layer formed on the crystallization inducing metal layer, and an active layer formed on the buffer layer and including source/drain regions, and including polycrystalline silicon crystallized by the MIC process.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: February 26, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Bon Koo, Sang-Gul Lee
  • Publication number: 20080035918
    Abstract: An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode layer is screen printed on the semiconductor layer, and a passivation layer is coated on the electrode layer. The organic thin-film transistor manufactured by the method of the invention has a substrate, a gate layer formed on the substrate, an insulator layer formed on the substrate, a semiconductor layer formed on the insulator layer, a strip for defining a channel length formed on the semiconductor layer, an electrode layer screen-printed on the semiconductor layer, and a passivation layer coated on the electrode layer. Thereby, an organic thin-film transistor with a top-contact/bottom-gate structure is obtained.
    Type: Application
    Filed: July 27, 2007
    Publication date: February 14, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Liang-Ying Huang, Jia-Chong Ho, Cheng-Chung Lee, Tarng-Shiang Hu, Wen-Kuei Huang, Wei-Ling Lin, Cheng-Chung Hsieh
  • Publication number: 20080035919
    Abstract: Disclosed is a thin film transistor array panel including a substrate, a data line formed on the substrate, a gate line that intersects the data line and includes a gate electrode, a source electrode connected to the data line, and a drain electrode facing the source electrode. An organic semiconductor contacts the source electrode and the drain electrode via an insulating layer having an opening that defines the location of the organic semiconductor. The insulating layer includes an acrylic photosensitive resin having a fluorine-containing compound. A method of manufacturing the above-described thin film transistor array panel is disclosed.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Inventors: Jung-Han Shin, Keun-Kyu Song, Tae-Young Choi, Young-Min Kim, Joon-Hak Oh, Seung-Hwan Cho
  • Patent number: 7326956
    Abstract: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide 3,4,9,10-perylene-based compound having, attached to each of the imide nitrogen atoms a carbocyclic or heterocyclic aromatic ring system substituted with one or more fluorine-containing groups. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating ac thin film transistor device, preferably by sublimation or solution-phase deposition onto a substrate, wherein the substrate temperature is no more than 100° C.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: February 5, 2008
    Assignee: Eastman Kodak Company
    Inventors: Deepak Shukla, Diane C. Freeman, Shelby F. Nelson
  • Patent number: 7312110
    Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: December 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-Ho Kwak, Sung-Jin Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Hoon Lim, Jong-Hyuk Kim, Myang-Sik Han, Byung-Jun Hwang
  • Patent number: 7300830
    Abstract: A method of fabricating a liquid crystal display panel includes forming a first conductive layer on a substrate and patterning the first conductive layer using a first resist pattern printed on the first conductive layer to form a gate pattern. A semiconductor layer and a second conductive layer are stacked on a gate insulating film formed on the gate pattern. A second resist pattern having a stepped part printed on the second conductive layer forms a source/drain pattern of a transistor. A third resist pattern printed on a passivation film formed on the substrate patterns the film. A third conductive layer is formed on the patterned film and the third resist pattern and the third resist pattern is stripped to form a transparent electrode pattern including a pixel electrode connected to the drain electrode of the transistor.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 27, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Soon Sung Yoo, Seung Hee Nam
  • Patent number: 7288818
    Abstract: Provided are an organic thin film transistor, a flat panel display device and methods of manufacturing these. The organic thin film transistor includes: source and drain electrodes and an organic semiconductor layer formed on a surface of a substrate; a gate electrode insulated from the source and drain electrodes and the organic semiconductor layer; wherein a thickness of at least a portion of the gate insulator above both the source and drain electrodes is larger than a thickness of at least a portion of the gate insulator above the channel region of the organic semiconductor layer.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: October 30, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Hun-Jung Lee, Jae-Bon Koo
  • Patent number: 7286195
    Abstract: An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: October 23, 2007
    Assignee: AU Optronics Corp.
    Inventor: Kun-Hong Chen
  • Patent number: 7285459
    Abstract: A flat panel display device having a high capacitance and a high aperture ratio. A thin film transistor and a capacitor are formed on an insulating substrate. The thin film transistor includes a semiconductor layer, a gate electrode and source and drain electrodes. The capacitor has first and second capacitor electrodes and a dielectric layer. An insulating layer is formed over the transistor to insulate the gate electrode from the source and drain electrodes, and a portion of the insulating layer is formed as the dielectric layer between the first and second capacitor electrodes. A non-planar shape of the first capacitor electrode and a conforming shape of the dielectric layer and a second capacitor electrode increase a capacitance of the capacitor. The portion of the insulating layer serving as the capacitor dielectric is formed to be thinner than the portion of the insulating layer formed over the gate electrode.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: October 23, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Seong-Moh Seo, Jae-Bon Koo
  • Publication number: 20070241325
    Abstract: A Schottky gate field effect transistor with high speed and simple structure is provided. The Schottky gate field effect transistor includes: a source, a channel and a drain formed by one organic conductive material, in which the source, channel and drain are formed in a continuous structure within an organic conductor; a gate electrode functioning as a metal gate on one surface of the organic conductor; a Schottky barrier formed by contact between the gate electrode and the organic conductor, in which the region overlapping with the Schottky contact is the channel region.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 18, 2007
    Applicant: Yamanashi University
    Inventor: Hidenori Okuzaki
  • Patent number: 7282767
    Abstract: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: October 16, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Gianluca Boselli, John E. Kunz, Jr.
  • Patent number: 7279702
    Abstract: The electronic device of the invention comprises one or more active elements, each comprising a first and a second electrode and an active layer of organic material separating the first and second electrodes. Examples of active elements are thin-film transistors and light-emitting diodes. The active layer comprises a polymeric material having conjugated units A and non-conjugated intermediate units B, which intermediate units B separate the conjugated units A from each other, such that no conjugation extends from a first conjugated unit A1 to a second conjugated unit A2. The polymeric material may be a polymer network, an alternating copolymer or a polymer in which the conjugated units are present in side chains. The polymer can be prepared from monomers having a B1-A1-B2 structure, wherein at least one of B1 and B2 comprises a reactive group enabling polymerization.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: October 9, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Bart-Hendrik Huisman, Dagobert Michel De Leeuw, Johan Lub
  • Patent number: 7268366
    Abstract: A method of fabricating an X-ray detecting device that is capable of preventing breakage of a transparent electrode. In the method, patterning of first and second insulating films occurs at different etching rates, with an etching ratio of the second insulating material to the first insulating material being greater than 1. Accordingly, undercut of the first and second insulating materials can be prevented. This stabilizes the step coverage of a subsequently formed transparent electrode.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: September 11, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Kyo Ho Moon
  • Patent number: 7265009
    Abstract: A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the at least two overlying semiconductor structures without applying a chucking bias Voltage to hold the semiconductor substrate.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: September 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yao-Hsiang Chen
  • Patent number: 7253086
    Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Lindsey Hall
  • Patent number: 7253439
    Abstract: The invention relates to a substrate for a display, a method of manufacturing the same, and a display having the same and provides a substrate for a display which can be manufactured through simple steps with high reliability, a method of manufacturing the same, and a display having the same. The substrate is configured to have a gate bus line, an OC layer formed on the gate bus line, a pixel electrode formed on the OC layer at each pixel region, and a gate terminal for electrically connecting an external circuit and the gate bus line.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: August 7, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsunori Misaki, Shiro Hirota