Field-effect Device (e.g., Tft, Fet) (epo) Patents (Class 257/E51.005)
  • Publication number: 20070178617
    Abstract: A pixel structure of a thin film transistor liquid crystal display employs a design of three metal layers and includes an organic insulating layer between a data signal line and a common electrode for reducing a parasitic capacitance, while a passivation layer included between the common electrode and a pixel electrode acts as a storage capacitor required for the pixels, so as to achieve a high aperture ratio, and the common electrode can act as a shielding bar for enhancing the display contrast.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 2, 2007
    Inventors: Che-Fu Tsai, Yi-Lin Chou, Wen-Chun Wang
  • Patent number: 7250316
    Abstract: A method for fabricating a device is disclosed. The method includes providing a substrate; forming a thin film on the substrate; forming a photoresistable layer on the thin film; irradiating light onto the photoresistable layer through a photo mask having a transmissive region, a semi-transmissive region, a diffractive region and an interceptive region, and developing the photoresistable layer to form a photoresist pattern having at least three different thicknesses. With the above-described process, a liquid crystal display device (LCD), for example, can be manufactured using three photo masks.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: July 31, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Jae-Moon Soh
  • Patent number: 7250629
    Abstract: A semiconductor device having two thin film transistors where cross-talk is minimized and a flat panel display device having the same.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: July 31, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Bon Koo, Min-Chul Suh
  • Patent number: 7238554
    Abstract: A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: July 3, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Paul J. Schuele, Apostolos T. Voutsas
  • Publication number: 20070145354
    Abstract: A novel barrier layer which protects electronic devices from adverse environmental effects such as exposure to light, especially white light, is described. The barrier layer comprises a copolymer having an acrylate unit and an acrylate unit with a pendant dye group. Also disclosed are processes for producing such electronic devices.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Mihaela Birau, Yiliang Wu, Beng Ong
  • Patent number: 7235434
    Abstract: A thin film transistor with multiple gates using an MILC process which is capable of materializing multiple gates without increasing dimensions and a method thereof. The thin film transistor has a semiconductor layer which is formed on a insulating substrate in a zigzag shape; and a gate electrode which is equipped with one or more slots intersecting with the semiconductor layer, the semiconductor layer includes two or more body parts intersecting with the gate electrode; and one or more connection parts connecting each neighboring body part, wherein a part overlapping the semiconductor layer in the gate electrode acts as a multiple gate, and MILC surfaces are formed at a part which does not intersect with the gate electrode in the semiconductor layer.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: June 26, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Woo-Young So
  • Patent number: 7229847
    Abstract: The present invention provides a process for forming electrical contacts to a molecular layer in a nanoscale device, the nanoscale device, and a method of manufacturing an integrated circuit comprise such devices. The process includes coating a surface of a stamp with a metal layer and forming an attached layer of anchored molecules by coupling first ends of the anchored molecules to a conductive or semiconductive substrate. The process also includes placing the metal layer in contact with the attached layer of anchored molecules such that the metal layer chemically bonds to free ends of the anchored molecules. The resulting devices produced have superior reliability as compared to conventional prepared devices.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: June 12, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Julia Wan-Ping Hsu, Yueh-Lin Loo, John A. Rogers
  • Patent number: 7229868
    Abstract: The invention relates to an organic field-effect transistor, to a method for structuring an OFET and to an integrated circuit with improved structuring of the functional polymer layers. The improved structuring is obtained by introducing, using a doctor blade, the functional polymer in the mold layer in which recesses are initially produced by imprinting.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: June 12, 2007
    Assignee: PolyIC GmbH & Co. KG
    Inventors: Adolf Bernds, Wolfgang Clemens, Peter Haring, Heinrich Kurz, Borislav Vratzov
  • Patent number: 7226818
    Abstract: The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have been fractionated so as to be concentrated in semiconducting CNTs. Additionally, the relatively low-temperature solution-based processing achievable with the methods of the present invention permit the use of plastics in the fabricated devices.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: June 5, 2007
    Assignee: General Electric Company
    Inventors: Patrick Roland Lucien Malenfant, Ji-Ung Lee, Yun Li, Walter Vladimir Cicha
  • Patent number: 7221039
    Abstract: A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of a silicon rich silicon oxide material formed over the thin film transistor device. The passivation layer formed of the silicon rich silicon oxide material provides the thin film transistor device with enhanced performance.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: May 22, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Ming Huang, Cheng-Fu Hsu
  • Publication number: 20070090352
    Abstract: A thin film transistor includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer that is insulated from the gate electrode and is electrically connected to the source and drain electrodes; an insulating layer that insulates the gate electrode from the source and drain electrodes or the organic semiconductor layer; and an ohmic contact layer that is interposed between the source/drain electrodes and the organic semiconductor and contains a compound having a hole transporting unit. By providing the ohmic contact layer, the ohmic contact between source/drain electrodes and the organic semiconductor layer can be effectively achieved and the adhesive force between the source/drain electrodes and the organic semiconductor layer is increased. In addition, a flat panel display having improved reliability can be obtained using the thin film transistor.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 26, 2007
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Taek Ahn, Min-Chul Suh, Jin-Seong Park, Seok-Jong Lee, Jung-Han Shin
  • Publication number: 20070085078
    Abstract: An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into the organic semiconductor layer. Deterioration of the organic semiconductor layer is started by breaking the protection film and using a specified means, thus starting operation of the lifetime period. The property deterioration material layer contains a material for deteriorating the property of the organic semiconductor and deterioration of the organic semiconductor layer is started, for example, by diffusing the material into the organic semiconductor layer.
    Type: Application
    Filed: December 15, 2006
    Publication date: April 19, 2007
    Inventors: Kazuo Kuroda, Shuuichi Yanagisawa
  • Patent number: 7202500
    Abstract: A thin film transistor array substrate includes a gate pattern on a substrate. The gate pattern includes a gate electrode, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line. A source/drain pattern includes a source electrode and a drain electrode, a data line connected to the source electrode, and a lower data pad electrode connected to the data line. A semiconductor pattern is formed beneath the source/drain pattern. A transparent electrode pattern includes a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode. The thin film array substrate further includes a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: April 10, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Soon Sung Yoo, Heung Lyul Cho
  • Patent number: 7198977
    Abstract: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide 3,4,9,10-perylene-based compound having, attached to each of the imide nitrogen atoms a substituted or unsubsitituted phenylalkyl group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation or solution-phase deposition onto a substrate, wherein the substrate temperature is no more than 100° C.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 3, 2007
    Assignee: Eastman Kodak Company
    Inventors: Deepak Shukla, Diane C. Freeman, Shelby F. Nelson
  • Patent number: 7195960
    Abstract: A thin film transistor has a structure capable of decreasing deterioration in Vgs-Ids characteristics. The thin film transistor has a source region composed of an N-type impurity-diffused region, a drain region, and a gate electrode, and a channel region formed directly below the gate electrode. To the source region and the drain region are connected a source electrode and a drain electrode, respectively, through a plurality of contact holes. In the channel region are formed a plurality of P-type impurity-diffused regions at constant intervals.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: March 27, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Inoue
  • Patent number: 7193238
    Abstract: An image display device which includes a display pixel block and circuit blocks peripheral thereto. Each block has a circuit made of high-performance thin film transistors. The display pixel block and the peripheral circuit blocks including the four corners of the display device are formed on an image display device substrate of circuit-built-in type thin film transistors having a small circuit occupation surface area. A circuit including thin film transistors of a polycrystalline silicon film anisotropically crystal-grown and having crystal grains aligned in its longitudinal direction with a current direction is provided in the whole or partial surface of the display pixel block and circuit blocks. The longitudinal direction is aligned with a horizontal or vertical direction within the block, and blocks aligned in the horizontal and vertical directions can be arranged as mixed when viewed from an identical straight line.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: March 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takeo Shiba, Mutsuko Hatano, Shinya Yamaguchi, Seong-kee Park
  • Patent number: 7189603
    Abstract: A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is fomed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold voltage for p-channel TFT. A second gate electrode layer is formed and patterned to form second gate electrodes. By using the first gate electrode layer as a mask, boron ions are implanted at a high concentration to form source/drain regions of the p-channel TFT. By using the second gate electrodes as a mask, the first gate electrode layer is etched to form gate electrodes. Phosphorous ions are implanted at a low concentration to form LDD regions. By using a fourth mask, P ions are implanted at a high concentration to form source/drain regions of n-channel TFTs.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: March 13, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Patent number: 7189995
    Abstract: The present invention relates to a thin film transistor for easily displaying gradation of an organic electroluminescence display device and a fabrication method of the thin film transistor, and an organic electroluminescence display device using the thin film transistor. The present invention provides an organic electroluminescence display device comprising a thin film transistor; a protection film and an organic light-emitting device electrically connected to the thin film transistor, wherein an S-factor of the thin film transistor is 0.35 V/dec or more.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: March 13, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Bon Koo, Sang-Il Park
  • Patent number: 7180093
    Abstract: The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 20, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno, Masakazu Murakami, Toshiji Hamatani, Hideaki Kuwabara, Shunpei Yamazaki
  • Publication number: 20070034860
    Abstract: A field effect organic transistor includes a source electrode, a drain electrode, a gate electrode, a gate insulating layer and an organic semiconductive layer; in the field effect organic transistor, the organic semiconductive layer includes a first organic semiconductive layer forming a channel region and a second organic semiconductive layer arranged to abut the first organic semiconductive layer; the charge mobility (?1) in the first organic semiconductive layer is 10?3 cm2/Vs or more; the charge mobility (?2) in the second organic semiconductive layer is 10?4 cm2/Vs or less; and the ratio (?1/?2) between the two organic semiconductive layers is 10 or more.
    Type: Application
    Filed: July 2, 2004
    Publication date: February 15, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Shinichi Nakamura
  • Publication number: 20070034861
    Abstract: A field effect type organic transistor is provided which comprises a source electrode, a drain electrode, and a gate electrode, a gate insulating layer, and an organic semiconductor layer, wherein the gate insulating layer contains an optical anisotropic material having an anisotropic structure formed by light irradiation, and the organic semiconductor layer is in contact with the anisotropic structure.
    Type: Application
    Filed: September 16, 2004
    Publication date: February 15, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Shinichi Nakamura
  • Patent number: 7176535
    Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: February 13, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Gee-Sung Chae
  • Patent number: 7170093
    Abstract: A dielectric material prepared from a siloxy/metal oxide hybrid composition, and electronic devices such as thin film transistors comprising such dielectric material are provided herein. The siloxy/metal oxide hybrid composition comprises a siloxy component such as, for example, a siloxane or silsesquioxane. The siloxy/metal oxide hybrid composition is useful for the preparation of dielectric layers for thin film transistors using solution deposition techniques.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: January 30, 2007
    Assignee: Xerox Corporation
    Inventors: Yiliang Wu, Beng S. Ong, Ping Liu
  • Publication number: 20070012914
    Abstract: There is provided a field effect transistor having an organic semiconductor layer, including: an organic semiconductor layer containing at least porphyrin; and a layer composed of at least a polysiloxane compound, the layer being laminated on the organic semiconductor layer so as to be in intimate contact with the organic semiconductor layer. As a result, there can be provided a field effect transistor which enables an organic semiconductor layer having high crystallinity and high orientation to be formed and which exhibits a high mobility.
    Type: Application
    Filed: March 9, 2005
    Publication date: January 18, 2007
    Applicant: Canon Kabushiki Kaisha
    Inventors: Daisuke Miura, Tomonari Nakayama, Toshinobu Ohnishi, Makoto Kubota, Akane Masumoto, Hidetoshi Tsuzuki, Makiko Miyachi
  • Patent number: 7160754
    Abstract: The present invention provides an organic field-effect transistor (OFET) and a method of fabricating the OFET. The OFET, configured to function as a p-type semiconductor, includes a substrate having a top surface and a semiconductor layer located over the top surface. The semiconductor layer comprises organic semiconductor molecules. Each of the organic semiconductor molecules includes a core having conjugated pi bonds, a fluorinated alkyl group, and an alkyl spacer group having a chain of two or more carbon atoms. One end of the chain is bonded to the fluorinated alkyl group and another end of the chain is bonded to the core. Substituents coupled to the carbon atoms have an electronegativity of less than about 4.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 9, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Zhenan Bao, Evert-Jan Borkent
  • Publication number: 20060284253
    Abstract: An organic thin film transistor (OTFT) includes a substrate, a gate electrode formed on the transparent substrate, a gate insulation film formed on the gate electrode, a source electrode and a drain electrode formed spaced apart from each other on the gate insulation film, a device insulation film formed over the gate, source, and drain electrodes, and an organic semiconductor film formed on the device insulation film.
    Type: Application
    Filed: December 29, 2005
    Publication date: December 21, 2006
    Inventors: Chang Han, Hee Pang
  • Patent number: 7144752
    Abstract: A method of manufacturing an organic electroluminescent display device, an organic electroluminescent display device, and a display device equipped with an organic electroluminescent display device are provided that enable a microlens to be formed without affecting an organic luminescent layer during the manufacturing process and to easily manufacture an organic electroluminescent display device with increased light output efficiency. According to the method, a lens pattern corresponding to a microlens that refracts the light from an organic luminescent layer is formed by performing photolithography treatment on a first transparent resin film formed on a substrate, and the microlens is formed by performing reflow treatment on the lens pattern.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: December 5, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Shinichi Yotsuya
  • Patent number: 7141839
    Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: November 28, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Danielle A. Thomas, Bruno J. Debeurre, Peter J. Thoma
  • Patent number: 7138652
    Abstract: Improved electroluminescent and photonic devices with integrated logic and control circuits are disclosed. Low mobility, contact barrier, space charge limitation and carrier balancing are provided solutions that increase efficiency, reliability and longevity of the devices. Device power loss and power requirements are reduced. True-ohmic contact materials allow a gate-controlled, light emitting organic triode MESFET configuration that eliminates commonly used ITO thereby increasing luminous output, and providing ease of address and control by integrally fabricated complementary MESFET address and control circuitry. The devices can be fabricated by printing or by weaving appropriate materials, and can be configured as color displays.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 21, 2006
    Assignee: Salonga Access LLC
    Inventor: Alton O. Christensen
  • Patent number: 7132322
    Abstract: Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: November 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brian Joseph Greene, Kern Rim, Clement Wann
  • Patent number: 7122830
    Abstract: The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: October 17, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Ishikawa, Yasumori Fukushima
  • Publication number: 20060220009
    Abstract: A thin film transistor composed of: (a) a semiconductor layer including a thiophene compound, wherein the thiophene compound comprises one or more substituted thiophene units, one or more unsubstituted thiophene units, and optionally one or more divalent linkages; (b) a gate dielectric; and (c) a layer contacting the gate dielectric disposed between the semiconductor layer and the gate dielectric, wherein the layer comprises a substance comprising a fluorocarbon structure.
    Type: Application
    Filed: March 10, 2006
    Publication date: October 5, 2006
    Applicant: XEROX CORPORATION
    Inventors: Yiliang Wu, Ping Liu, Beng Ong
  • Patent number: 7115448
    Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 3, 2006
    Assignee: AU Optronics Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 7105118
    Abstract: Nanostructures and methods of making nanostructures having self-assembled nanodot arrays wherein nanodots are self-assembled in a matrix material due to the free energies of the nanodot material and/or differences in the Gibb's free energy of the nanodot materials and matrix materials.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 12, 2006
    Assignee: North Carolina State University
    Inventors: Jagdish Narayan, Ashutosh Tiwari
  • Publication number: 20060151781
    Abstract: An organic thin film transistor including a fluorine-based polymer thin film and method of fabricating the same. The organic thin film transistor may include a gate electrode, a gate insulating layer, an organic semiconductor layer, source electrode, and a drain electrode formed on a substrate wherein a fluorine-based polymer thin film may be formed (or deposited) at the interface between the gate insulating layer and the organic semiconductor layer. The organic thin film transistor may have higher charge carrier mobility and/or higher on/off current ratio (Ion/Ioff). In addition, a polymer organic semiconductor may be used to form the insulating layer and the organic semiconductor layer by wet processes, so the organic thin film transistor may be fabricated by simplified procedure(s) at reduced costs.
    Type: Application
    Filed: December 8, 2005
    Publication date: July 13, 2006
    Inventors: Joo Kim, Eun Lee, Bang Lee, Bon Koo, Hyun Park, Sang Lee
  • Publication number: 20060124930
    Abstract: A thin film transistor is characterized by having an island-in structure having a semiconductor layer with a channel region, a bottom heavily-doped semiconductor layer, and a top heavily-doped semiconductor layer. The bottom heavily-doped semiconductor layer is positioned on two opposite sides of the surface of the semiconductor layer beyond the channel region. The top heavily-doped semiconductor layer, positioned on the bottom heavily-doped semiconductor layer, covers two opposite side walls of the bottom heavily-doped semiconductor layer and the semiconductor layer so that current leakage from the drain electrode to the source electrode is prevented.
    Type: Application
    Filed: April 27, 2005
    Publication date: June 15, 2006
    Inventors: Chi-Wen Chen, Ting-Chang Chang, Po-Tsun Liu, Feng-Yuan Gan
  • Publication number: 20060113526
    Abstract: A manufacturing method of an organic semiconductor device wherein an organic semiconductor layer being, a structural component of an organic semiconductor device is formed continuously with uniform performance over a sufficiently large area.
    Type: Application
    Filed: March 29, 2005
    Publication date: June 1, 2006
    Inventors: Junichi Hanna, Hiroaki Iino, Hiroki Maeda
  • Patent number: 7019328
    Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: March 28, 2006
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Michael L. Chabinyc, Ana C. Arias
  • Publication number: 20060038179
    Abstract: A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device.
    Type: Application
    Filed: February 11, 2005
    Publication date: February 23, 2006
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Jia Chen, Christian Klinke, Paul Solomon
  • Patent number: 6995432
    Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: February 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Publication number: 20050184407
    Abstract: A TFT circuit includes a source terminal, a drain terminal, and first and second transistors having source-drain paths that are connected in series between the source terminal and the drain terminal, and mutually independent gate electrodes. The TFT circuit further includes upper and lower shaping circuits that, at least, turn off all of the first and second transistors by differentiating gate potentials such that a voltage between the source terminal and the drain terminal may substantially equally be distributed to the first and second transistors.
    Type: Application
    Filed: February 17, 2005
    Publication date: August 25, 2005
    Inventor: Takahiro Korenari
  • Patent number: 6913944
    Abstract: An organic thin-film transistor manufacturing method and an organic thin-film transistor manufactured by the method are disclosed, the method comprising the steps of a) forming a gate electrode on a substrate, b) forming a gate insulating layer on the substrate, c) forming an organic semiconductor layer on the substrate, d) forming an organic semiconductor layer protective layer on the organic semiconductor layer, e) removing a part of the organic semiconductor layer protective layer, and f) forming a source electrode and a drain electrode at portions where the organic semiconductor layer protective layer has been removed, so that the source electrode and drain electrode contacts the organic semiconductor layer.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: July 5, 2005
    Assignee: Konica Minolta Holdings, Inc.
    Inventor: Katsura Hirai