Solid Dielectric Type Patents (Class 29/25.42)
  • Patent number: 8621730
    Abstract: In a capacitor producing method, a bottom electrode, a thin-film dielectric, and a top electrode are deposited on a substrate so as to form a capacitor, wherein defects including particles and electrical short-circuits between the bottom electrode and the top electrode are detected before the capacitor is divided into capacitor cells. Next, defects such as particles and electrical short-circuits between the bottom electrode and the top electrode are removed before the capacitor is divided into capacitor cells.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 7, 2014
    Assignee: NEC Corporation
    Inventors: Akinobu Shibuya, Koichi Takemura, Takashi Manako
  • Publication number: 20140002955
    Abstract: A dielectric ceramic composition is represented by BaTiO3+aRe2O3+bMnO+cV2O5+dMoO3+eCuO+fB2O3+gLi2O+xSrO+yCaO (wherein Re represents one or more elements selected from among Eu, Gd, Dy, Ho, Er, Yb, and Y; and a-h each represents the mole number of each component with respect to 100 mol of the main component that is composed of BaTiO3). When the molar ratio of (Ba+Sr+Ca)/Ti contained in the dielectric ceramic composition is represented by m, the 0.10?a?0.50, 0.20?b?0.80, 0?c?0.12, 0?d?0.07, 0.04?c+d?0.12, 0?e?1.00, 0.50?f?2.00, 0.6?(100(m?1)+2g)/2f?1.3, and 0.5?100(m?1)/2g?5.1 are satisfied.
    Type: Application
    Filed: September 26, 2011
    Publication date: January 2, 2014
    Applicant: TAIYO YUDEN CO., LTD.
    Inventor: Shinsuke Takeoka
  • Publication number: 20140002952
    Abstract: A stacked MLCC capacitor is provided wherein the capacitor stack comprises multilayered ceramic capacitors wherein each multilayered ceramic capacitor comprises first electrodes and second electrodes in an alternating stack with a dielectric between each first electrode and each adjacent second electrode. The first electrodes terminate at a first side and the second electrodes second side. A first transient liquid phase sintering conductive layer is the first side and in electrical contact with each first electrode; and a second transient liquid phase sintering conductive layer is on the second side and in electrical contact with each second electrode.
    Type: Application
    Filed: August 6, 2013
    Publication date: January 2, 2014
    Applicant: Kemet Electrinics Corporation
    Inventors: John E. McConnell, Garry L. Renner, John Bultitude, Allen Hill
  • Publication number: 20140002950
    Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer; a plurality of internal electrodes disposed to face each other within the ceramic body, having the dielectric layer interposed therebetween; and external electrodes electrically connected to the internal electrodes, wherein the ceramic body includes an active layer corresponding to a capacitance forming part and a cover layer formed on at least one of an upper surface and a lower surface of the active layer and corresponding to a non-capacitance forming part, an average thickness of the cover layer is 15 ?m or less, the external electrodes include a conductive metal and a glass, and when an area of the external electrodes occupied by the glass is A and an area thereof occupied by the conductive metal is B, 0.05?A/B?0.6 is satisfied.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 2, 2014
    Inventors: Hyun Hee GU, Myung Jun Park, Kyu Ha Lee, Da Young Choi, Jae Young Park, Sang Hoon Kwon, Byung Jun Jeon
  • Publication number: 20140002954
    Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: ZOLL MEDICAL CORPORATION
    Inventor: Allan Scott Baucom
  • Publication number: 20130335882
    Abstract: The invention is directed to a process for making a dielectric ceramic film capacitor and the ceramic dielectric laminated capacitor formed therefrom, the dielectric ceramic film capacitors having increased dielectric breakdown strength. The invention increases breakdown strength by embedding a conductive oxide layer between electrode layers within the dielectric layer of the capacitors. The conductive oxide layer redistributes and dissipates charge, thus mitigating charge concentration and micro fractures formed within the dielectric by electric fields.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: UCHICAGO ARGONNE, LLC.
    Inventors: Beihai Ma, Uthamalingam Balachandran, Shanshan Liu
  • Patent number: 8607424
    Abstract: A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Cypress Semiconductor Corp.
    Inventors: Vladimir Korobov, Oliver Pohland
  • Patent number: 8607445
    Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 17, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin
  • Patent number: 8601658
    Abstract: The embodiments disclosed herein are directed to fabrication methods useful for creating MEMS via microcontact printing by using small organic molecule release layers. The disclose method enables transfer of a continuous metal film onto a discontinuous platform to form a variable capacitor array. The variable capacitor array can produce mechanical motion under the application of a voltage. The methods disclosed herein eliminate masking and other traditional MEMS fabrication methodology. The methods disclosed herein can be used to form a substantially transparent MEMS having a PDMS layer interposed between an electrode and a graphene diaphragm.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: December 10, 2013
    Assignee: Massauchusetts Institute of Technology
    Inventors: Vladimir Bulovic, Corinne Evelyn Packard, Jennifer Jong-Hua Yu, Apoorva Murarka, LeeAnn Kim
  • Publication number: 20130321980
    Abstract: A multilayer ceramic capacitor includes a multilayer body including a plurality of laminated dielectric layers and a plurality of internal electrodes arranged along interfaces between the dielectric layers, and a plurality of external electrodes located on an outer surface of the multilayer body and electrically connected to the internal electrodes. A main component of the internal electrodes is Ni, and the internal electrodes also contain Sn.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 5, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shoichiro SUZUKI, Shinichi YAMAGUCHI
  • Publication number: 20130314838
    Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 28, 2013
    Inventors: Jong Taek HWANG, Han Choon Lee, Oh Jin Jung, Jin Youn Cho
  • Patent number: 8590123
    Abstract: The disclosure provides a method for producing an electronic component in which the oxidation of Cu constituting an internal conductor part of the component is inhibited or prevented in a firing step, and even when a magnetic body part containing NiO, ZnO, Fe2O3, etc. is reduced in the firing step, the magnetic body part is subsequently oxidized to ensure the original characteristics. In producing the electronic component, an unfired laminated body including parts to serve as the magnetic body part and the internal conductor part after firing is subjected to firing in an atmosphere with an oxygen concentration equal to or lower than the equilibrium oxygen partial pressure of Cu—Cu2O, and the fired laminated body is then subjected to an oxygenic-atmosphere heat treatment in an atmosphere with an oxygen concentration of 0.01% or more in a step of decreasing the temperature.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: November 26, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Yamamoto, Akihiro Nakamura
  • Patent number: 8584332
    Abstract: In a manufacturing method for a monolithic ceramic electronic component, a ceramic paste is applied by using an application plate to a side surface of each of a plurality of green chips arrayed in row and column directions which are obtained after cutting a mother block. In the applying step, the ceramic paste is transferred to the side surface by moving the green chips and the application plate relative to each other in the direction in which the side surface extends while separating the green chips from the application plate, in a state where the ceramic paste is connected to both the green chips and the application plate.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 19, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Togo Matsui, Minoru Dooka, Hiroyoshi Takashima, Kenichi Okajima
  • Publication number: 20130301188
    Abstract: A method for manufacturing a capacitive storage element having a layer system on one side of a porous substrate, which is designed as a conductive substrate or has a conductive surface layer at least on the one side, the layer system having a layer sequence of a dielectric titanate layer and an electrically conductive layer. It is provided that to form a closed titanate layer having an adjustable minimum layer thickness, an external electrical field is applied in the direction of the layer sequence, and when the field is applied, a fluid containing titanate particles is applied to the substrate. A corresponding capacitive storage element and the use of a capacitive storage element as a storage element of an electrical energy storage unit for supplying energy to an electric drive or hybrid drive of a motor vehicle are also described.
    Type: Application
    Filed: September 21, 2011
    Publication date: November 14, 2013
    Inventor: Bert Walch
  • Publication number: 20130298364
    Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.
    Type: Application
    Filed: December 11, 2012
    Publication date: November 14, 2013
    Applicant: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Publication number: 20130294010
    Abstract: There is provided a multilayer ceramic electronic component. The multilayer ceramic electronic component includes: a ceramic body including a dielectric layer; first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween in the ceramic body; external electrodes formed on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes; and grooves formed in at least one of top and bottom surface of the ceramic body on which the external electrodes are formed.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 7, 2013
    Inventors: Kyoung No Lee, Eun Me Park, Byung Gyun Kim, Chul Soon Ahn, Hye Young Choi, Young Sook Lee
  • Publication number: 20130279074
    Abstract: There is provided a multilayer ceramic electronic component. The multilayer ceramic electronic component includes a ceramic main body including a dielectric layer, and first and second internal electrodes disposed to face each other within the ceramic main body and having the dielectric layer interposed therebetween. When an average roughness of center lines of the first and second internal electrodes is Ra, a maximum distance from a virtual line corresponding to Ra to a bottom of a pit (d) formed below the virtual line is 0.1 ?m to 13 ?m. The surface roughness of the internal electrode printed surface is improved to decrease the occurrence of electrical shorts.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 24, 2013
    Inventors: Jin Woo LEE, Tae Hyeong KIM, Eung Soo KIM, Chi Hyoun RO, Hang Kyu CHO
  • Patent number: 8561271
    Abstract: A method for making a capacitor having improved capacitance efficiency which results from increasing the effective area of an electrode surface is disclosed. Specifically, an improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode-dielectric-electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 22, 2013
    Inventors: Liang Chai, Alan Rae, James M Wison
  • Patent number: 8555474
    Abstract: A method of manufacturing a capacitor includes: anodizing a metal substrate in two stages by applying two different voltage so as to make first and second holes having different pitches, distributed randomly in an oxide substance; filling the first and second holes with an electrode material, respectively, to form first and second electrodes; connecting the first electrodes to a conductive layer formed on one surface of the oxide substance; and connecting the second electrodes to another conductive layer formed on another surface of the oxide substance.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 15, 2013
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Hidetoshi Masuda, Taisei Irieda, Masaru Kurosawa, Kotaro Mizuno
  • Publication number: 20130266826
    Abstract: This disclosure provides systems, methods and apparatus for a combined battery/capacitor energy storage device. The energy storage device includes an energy storage device housing, with a battery housing portion, a capacitor housing portion, and a housing lid. The energy storage device includes a battery disposed within the battery housing portion. The battery includes a first battery terminal extending through a battery lid enclosing the battery housing portion. The energy storage device includes a capacitor disposed within the capacitor housing portion and connected in parallel with the battery. The capacitor includes a first capacitor terminal. The energy storage device includes a first bus bar electrically connecting the first battery terminal and the first capacitor terminal. The energy storage device includes a first external device terminal extending through the energy storage device housing and configured to electrically connect to the first battery terminal and the bus bar.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 10, 2013
    Inventors: Jeremy Cowperthwaite, Takao Shimbori, Mikael Setterberg, Priya Bendale, Thomas J. Dougherty
  • Publication number: 20130266824
    Abstract: This disclosure provides systems, methods and apparatus for a combined battery/capacitor energy storage device. In one aspect, the device includes a housing with an integrated battery housing portion, a capacitor housing portion, and a housing lid. A plurality of battery electrodes and electrolyte are contained directly within the integrated battery housing portion and are configured to form an integrated battery within the integrated battery housing portion. The capacitor is connected in parallel with the battery and contained within the capacitor housing portion. A first device terminal and a second device terminal extending through the housing.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 10, 2013
    Inventors: Jeremy Cowperthwaite, Takeo Shimbori, Mikael Setterberg, Priya Bendale, Thomas J. Dougherty
  • Publication number: 20130265121
    Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 10, 2013
    Applicant: MediaTek Inc.
    Inventors: Ming-Tzong YANG, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang
  • Patent number: 8547683
    Abstract: In a method for manufacturing a laminated ceramic electronic component, after a plating layer for an external terminal electrode is formed by applying copper plating to an end surface of a component main body at which respective ends of a plurality of internal electrodes primarily including nickel are exposed, when a heat treatment at a temperature of about 800° C. or more is applied in order to improve adhesion strength and resistance to moisture of the external terminal electrode, voids may occur in the plating layer. The step of applying a heat treatment at a temperature of about 800° C. or more to a component main body with plating layers formed thereon includes not only a step of maintaining a top temperature of about 1000° C. or more but also a step of maintaining a temperature of about 600° C. to 900° C. at least once before the step of maintaining the top temperature.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 1, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahito Saruban, Makoto Ogawa, Toshiyuki Iwanaga, Seiichi Matsumoto, Akihiro Motoki, Shunsuke Takeuchi, Seiichi Nishihara, Kenichi Kawasaki
  • Publication number: 20130250473
    Abstract: An improved multi-layered ceramic capacitor, and method of making the multi-layered ceramic capacitor, is described. The capacitor has an active area comprising first layers and second layers in alternating parallel arrangement with dielectric there between. The first layer comprises a first active electrode and a first floating electrode in a common plane and the second layer comprises a second active electrode and a second floating electrode in a second common plane. At least one shield layer is adjacent to an outermost first layer of the first layers wherein the shield layer has a first projection and the first layers have a second projection wherein the first projection and the second projection are different.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 26, 2013
    Inventors: John Bultitude, Lonnie G. Jones, James R. Magee, Kitae Park
  • Publication number: 20130250475
    Abstract: A capacitor includes a capacitor element that is a wound element or an element other than the wound element, and that includes electrode bodies each of which is in an anode side and a cathode side, and separators that intervenes between the electrode bodies; a sealing member that seals an opening of a case member accommodating the capacitor element; at least one electrode protrusion that protrudes from one of the electrode bodies on an element end-face of the capacitor element, at least one of current collector plate that is connected to the electric protrusion; and at least one terminal member that is disposed in the sealing member, and is superposed on the current collector plate, a side face part of the terminal member being welded to a side face part of the current collector plate.
    Type: Application
    Filed: May 9, 2013
    Publication date: September 26, 2013
    Applicant: NIPPON CHEMI-CON CORPORATION
    Inventors: Masayuki Mori, Tatsuo Kubouchi, Akihiro Furusawa
  • Publication number: 20130250477
    Abstract: A method of forming a capacitor structure includes forming a mold layer on a substrate, in which the substrate includes a plurality of plugs therein, partially removing the mold layer to form a plurality of openings, in which the plugs are exposed by the openings, forming a plurality of lower electrodes filling the openings, in which the lower electrodes have a pillar shape, removing an upper portion of the mold layer to expose upper portions of the lower electrodes, forming a supporting pattern on exposed upper sidewalls of the lower electrodes and on the mold layer, removing the mold layer, and sequentially forming a dielectric layer and an upper electrode on the lower electrodes and the supporting pattern.
    Type: Application
    Filed: February 7, 2013
    Publication date: September 26, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jun-Hee LIM
  • Publication number: 20130242460
    Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same, the multilayer ceramic electronic including: a ceramic body; and a plurality of internal electrodes laminated within the ceramic body, wherein, when T1 is the greatest distance between an upper outermost internal electrode and a lower outermost internal electrode among the plurality of internal electrodes and T2 is the distance between the highest point and the lowest point in each of the upper outermost internal electrode and the lower outermost internal electrode in a thickness direction of the ceramic body, T2/T1<0.05 is satisfied, and thus, defects in alignment of internal electrodes of the multilayer ceramic electronic component may be suppressed.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 19, 2013
    Inventors: Jong Ho LEE, Sung Chul Bae, Jae Yeol Choi, Sung Woo Kim, Yu Na Kim
  • Patent number: 8528175
    Abstract: Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second component relative to a first component. The continuous concentration gradient may correspond to a decreasing concentration of the second component as a distance from the first capacitor electrode increases. The first component may be selected from the group consisting of zirconium oxide, hafnium oxide and mixtures thereof; and the second component may be selected from the group consisting of niobium oxide, titanium oxide, strontium oxide and mixtures thereof. A second capacitor electrode may be formed over the first capacitor electrode. Some embodiments include capacitors that contain at least one metal oxide mixture having a continuous concentration gradient of the above-described second component relative to the above-described first component.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vassil Antonov, Vishwanath Bhat, Chris M. Carlson
  • Publication number: 20130215554
    Abstract: An electric double layer capacitor and a method for manufacturing the same, in which one or more projections are formed on an inner bottom surface of a lower case, which is a concave container made of ceramic, in a the process of sequentially stacking a lower electrode, a separator, and an upper electrode in the lower case and covering the lower case with a sealing plate. It is possible to eliminate the process of injecting a bonding liquid and strongly connect the lower electrode and the upper electrode to the lower case and the sealing plate, respectively, by means of the projections, thus preventing the occurrence of a short circuit and reducing the equivalent series resistance.
    Type: Application
    Filed: August 30, 2012
    Publication date: August 22, 2013
    Applicant: ROSWIN, INC.
    Inventors: Ho Won SON, Jung Won LEE, Ki Yeon LEE
  • Publication number: 20130201602
    Abstract: A laminated ceramic capacitor includes multiple dielectric layers, internal electrodes having Cu as the primary component and embedded between the dielectric layers, and external electrodes. The dielectric layers contain a primary component comprised of a CaZrO3 compound and auxiliary components that include Mn, B, Si, and Li wherein a primary phase comprised of the primary component, segregation phases containing Ca and at least one of the auxiliary components, and secondary phases containing at last Ca and Zr are formed. The ratio of Ca to Zr in the secondary phases is smaller than the ratio of Ca to Zr in the primary phase, and the number of secondary phases with a diameter of 100 nm or greater in a cross section of the dielectric layers averages 30 or less per 10 square ?m.
    Type: Application
    Filed: September 26, 2011
    Publication date: August 8, 2013
    Applicant: TAIYO YUDEN CO., LTD.
    Inventor: Shinsuke Takeoka
  • Patent number: 8499426
    Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventor: Cengiz A. Palanduz
  • Patent number: 8503160
    Abstract: In a laminate type ceramic electronic component, when an external electrode is formed directly by plating onto a surface of a component main body, the plating film that is to serve as the external electrode may have a low fixing strength with respect to the component main body. In order to prevent this problem, an external electrode includes a first plating layer composed of a Ni—B plating film and is first formed such that a plating deposition deposited with the exposed ends of respective internal electrodes as starting points is grown on at least an end surface of a component main body. Then, a second plating layer composed of a Ni plating film containing substantially no B is formed on the first plating layer. Preferably, the B content of the Ni—B plating film constituting the first plating layer is about 0.1 wt % to about 6 wt %.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: August 6, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahito Saruban, Makoto Ogawa, Akihiro Motoki, Takehisa Sasabayashi, Takayuki Kayatani
  • Publication number: 20130193215
    Abstract: A permanently deactivatable security tag and method to create a permanently deactivatable security tag to eliminate tag pollution caused by reactivated tags reentering a store premises and setting off false alarms. The security tag includes a frangible conductive portion that fractures due to stress applied on the frangible conductive portion from a hardened substrate located on the tag. The hardened substrate induces stress to the frangible conductive portion located adjacent to the edge of the hardened substrate as the tag is flexed and bent. The fracture of the frangible conductive portion of the tag results in a shifting and/or disabling of the predetermined frequency of the security tag.
    Type: Application
    Filed: January 10, 2013
    Publication date: August 1, 2013
    Applicant: Checkpoint Systems, Inc.
    Inventor: Checkpoint Systems, Inc.
  • Publication number: 20130180344
    Abstract: The present invention relates to a transducer and a method for manufacturing same, and more particularly, to a transducer and to a method for manufacturing same, in which a first liquid and a second liquid are supplied such that, at the boundary therebetween, a deformation-generating part, including a perforated structure having one or more holes therein, is formed, and the effect of external pressure is negated by the action between the liquids.
    Type: Application
    Filed: September 20, 2010
    Publication date: July 18, 2013
    Applicant: SEOUL NATIONAL UNIVERSITY R&D FOUNDATION
    Inventors: Jung Hoon Lee, Jae Ha Shin, Jun Kyu Choi
  • Publication number: 20130182371
    Abstract: Provided are a capacitor and a method of manufacturing the same. A first capacitor unit and a second capacitor unit are alternately stacked to three layers or more to form a stacked body, collector lead parts of the first capacitor units are connected to contact each other, collector lead parts of the second capacitor units are connected to contact each other, and the collector lead parts of the stacked body are stacked such that side surfaces thereof form a stepped shape.
    Type: Application
    Filed: December 21, 2012
    Publication date: July 18, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Samsung Electro-Mechanics Co., Ltd.
  • Patent number: 8484815
    Abstract: A method for manufacturing a laminated electronic component including an electronic component main body including laminated functional layers, internal conductors which are disposed inside the electronic component main body and a portion of which are exposed portions exposed at outer surfaces of the electronic component main body, and external terminal electrodes disposed on the outer surfaces of the electronic component main body so as to connect to the internal conductors and cover the exposed portions of the internal conductors includes the step of forming a substrate plating film having an average particle diameter of metal particles of at least about 1.0 ?m on the outer surface of the electronic component main body through direct plating so as to cover the exposed portions of the internal conductors in the formation of the external terminal electrodes on the electronic component main body.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 16, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shunsuke Takeuchi, Kenichi Kawasaki, Akihiro Motoki, Makoto Ogawa, Toshiyuki Iwanaga
  • Patent number: 8475866
    Abstract: A method for manufacturing a ceramic electronic component capable of preventing degradation of the self alignment property and product characteristics due to absorption of flux into pores of a ceramic element assembly during soldering in mounting and a ceramic electronic component. In the method, a ceramic element assembly is subjected to an oil-repellent treatment by using an oil-repellent agent containing a polyfluoropolyether compound as a primary component and hydrofluoroether as a solvent, so as to avoid absorption of the flux by the ceramic element assembly.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 2, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuya Mizuno, Masaharu Konoue, Hiroki Hashimoto, Mitsuru Ueda
  • Patent number: 8474126
    Abstract: A manufacturing method of a semiconductor device include forming a capacitor by forming an oxide film on a surface of a valve metal based on anodic oxidization and by forming a conductive part made of a conductive material on the oxide film; adhering the capacitor on a semiconductor element mounted on a supporting substrate; and coupling the capacitor to the supporting substrate via an outside connection terminal.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: July 2, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 8468664
    Abstract: An EMI filtered terminal assembly including at least one conductive terminal pin, a feedthrough capacitor, and a counter-bore associated with a passageway through the capacitor is described. Preferably, the feedthrough capacitor having counter-drilled or counter-bored holes on its top side is first bonded to a hermetic insulator. The counter-drilled or counter-bore holes in the capacitor provide greater volume for the electro-mechanical attachment between the capacitor and the terminal pin or lead wire, permitting robotic dispensing of, for example, thermal-setting conductive adhesive.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: June 25, 2013
    Assignee: Greatbatch Ltd.
    Inventors: Richard L. Brendel, Jason Woods, Jose Luis Lorente-Adame, Robert A. Stevenson, John Roberts, Buehl E. Truex
  • Patent number: 8468665
    Abstract: A method of manufacturing a capacitive microphone comprises providing a substrate having at least one cavity. The method further comprises forming a backplate on the substrate, wherein the backplate has a plurality of holes, and forming a diaphragm on the backplate, wherein there are a first distance and a second distance between the diaphragm and the backplate. The method still further comprises forming an air gap between the backplate and the diaphragm through the first distance, and fastening the diaphragm to the backplate through the second distance.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: June 25, 2013
    Assignee: Industrial Technology Research Institute
    Inventor: Jen-Yi Chen
  • Patent number: 8465555
    Abstract: The present subject matter includes a method of producing an apparatus for use in a patient, the method including etching an anode foil, anodizing the anode foil, assembling the anode foil, at least one cathode foil and one or more separators into a capacitor stack adapted to deliver from about 5.3 joules per cubic centimeter of capacitor stack volume to about 6.3 joules per cubic centimeter of capacitor stack volume at a voltage of between about 465 volts to about 620 volts, inserting the stack into a capacitor case, inserting the capacitor case into a device housing adapted for implant in a patient, connecting the capacitor to a component and sealing the device housing.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: June 18, 2013
    Assignee: Cardiac Pacemakers, Inc.
    Inventor: Gregory J. Sherwood
  • Publication number: 20130141838
    Abstract: Provided is a laminated ceramic capacitor which produces excellent lifetime characteristics in a high-temperature loading test even when dielectric layers are reduced in thickness. The dielectric ceramic contains, as its main constituent, a compound represented by the general formula (Ba1-x-yCaxRey)(Ti1-zMz)O3 (where Re is at least one or more elements selected from among La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y, and M is at least one or more elements selected from among Mg, Mn, Al, Cr, and Zn), 0?x?0.2, 0.002?y?0.1, and 0.001?z?0.05. This dielectric ceramic has crystal grains of 20 nm or more and 150 nm or less in average grain size.
    Type: Application
    Filed: January 30, 2013
    Publication date: June 6, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Murata Manufacturing Co., Ltd.
  • Publication number: 20130135787
    Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body including dielectric layers; and first and second inner electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic body, the first and second inner electrodes being alternately laminated with a difference in printing widths therebetween, wherein a difference ratio between the printing widths of the first and second inner electrodes is 20 to 80%. According to embodiments of the present invention, a multilayer ceramic electronic component having excellent reliability and withstand voltage characteristics may be realized, by reducing the occurrence of cracking through a reduction in the influence of step height while securing high capacitance.
    Type: Application
    Filed: August 2, 2012
    Publication date: May 30, 2013
    Inventors: Jin Hyung LIM, Seok Kyoon Woo, Chung Eun Lee, Doo Young Kim
  • Publication number: 20130135789
    Abstract: There is provided a multilayer ceramic electronic part, including: a ceramic body including dielectric layers each having an average thickness of 0.6 ?m or less; and first and second internal electrodes disposed to face each other within the ceramic body with the dielectric layer interposed therebetween, wherein the ceramic body includes a capacitance forming part and non-capacitance forming parts, and when the capacitance forming part is divided into 2n+1 (n is 1 or more) regions in a thickness direction of the ceramic body, the dielectric layers of the capacitance forming part get thinner in directions from a central region toward upper and lower regions, whereby continuity of the internal electrode may be improved and a high-capacity multilayer ceramic electronic part may be realized.
    Type: Application
    Filed: February 24, 2012
    Publication date: May 30, 2013
    Inventors: Wi Heon KIM, Doo Young Kim, Jin Man Jung
  • Patent number: 8448313
    Abstract: Provided is a method for producing a ceramic body, which is capable of preventing the ingress of moisture into a void between a conductor and the ceramic body more effectively in the ceramic body including the conductor therein. Ingress of a supercritical fluid containing an oxide sol precursor is achieved into a void between an internal electrode layer and a ceramic laminate. After that, the oxide sol is turned into a gel, and subjected to a heat treatment, thereby filling the void between the internal electrode layer and the ceramic laminate with an oxide.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: May 28, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuo Kunishi, Junichi Saito, Yoshinori Ueda, Akihiro Motoki
  • Patent number: 8443498
    Abstract: The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: May 21, 2013
    Assignee: Sehyang Industrial Co., Ltd.
    Inventor: Jae-Ho Ha
  • Publication number: 20130120902
    Abstract: A substrate-incorporated capacitor includes a first electrode extending in a predetermined direction, a dielectric layer arranged on the first electrode, a second electrode arranged on the dielectric layer and facing the first electrode through the dielectric layer, wherein the second electrode includes an end projecting from the dielectric layer in the predetermined direction, and an electrode layer spaced apart from the first electrode in the predetermined direction. The end of the second electrode is connected to the electrode layer in the predetermined direction. The electrode layer includes a surface that is flush with a surface of the first electrode.
    Type: Application
    Filed: July 7, 2011
    Publication date: May 16, 2013
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hitoshi Noguchi, Kenichi Ezaki
  • Publication number: 20130120416
    Abstract: This disclosure provides systems, methods and apparatus for storage capacitors. In one aspect, an electromechanical systems (EMS) device includes a substrate, an optical stack disposed over the substrate, a mechanical layer positioned over the optical stack, and a storage capacitor. The optical stack includes a stationary electrode and at least one dielectric layer disposed over the stationary electrode, and the storage capacitor includes a first plate, a second plate and a dielectric structure disposed between the first and second plates. The first plate includes a portion of the mechanical layer positioned over an optically non-active region of the device, and the dielectric structure of the storage capacitor includes a portion of the at least one dielectric layer of the optical stack.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 16, 2013
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventors: Jae Hyeong Seo, Ming-Hau Tung, Marc M. Mignard
  • Publication number: 20130120904
    Abstract: A substrate-incorporated capacitor includes a first electrode extending in a predetermined direction, a dielectric layer arranged on part of the first electrode, a second electrode arranged on the dielectric layer and facing the first electrode through the dielectric layer, and an electrode layer arranged on the first electrode surrounding the dielectric layer and connected to the first electrode. Part of the electrode layer is arranged on an end of the dielectric layer and is spaced apart from the second electrode in the predetermined direction, and the part of the electrode layer faces the first electrode through the dielectric layer.
    Type: Application
    Filed: July 7, 2011
    Publication date: May 16, 2013
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hitoshi Noguchi, Kenichi Ezaki
  • Patent number: 8438710
    Abstract: A structure with an integrated circuit (IC) and a silicon condenser microphone mounted thereon includes a substrate having a first area and a second area. The IC is fabricated on the first area in order to form a conducting layer and an insulation layer. Both the conducting layer and the insulation layer further extend to the second area. The insulation layer is removed under low temperature in order to expose the conducting layer on which the silicon condenser microphone is fabricated. The silicon condenser microphone includes a first film layer, a connecting layer and a second film layer under a condition that the connecting layer connects the first and the second film layers. The first film layer and the second film layer act as two electrodes of a variable capacitance.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: May 14, 2013
    Inventor: Gang Li