Solid Dielectric Type Patents (Class 29/25.42)
  • Patent number: 8434211
    Abstract: A method for manufacturing a measuring apparatus for capacitive determining and/or monitoring of at least the fill level of a medium. The measuring apparatus has a probe unit and an electronics unit. During a measurement, the electronics unit supplies the probe unit with an exciter signal and receives from the probe unit a received signal, from which the electronics unit ascertains a capacitance value. The probe unit is coated with an insulation layer, the coated probe unit is connected with the electronics unit and inserted into a container containing a calibration medium, the coated probe unit is covered completely by the calibration medium and an associated received signal is gained, and, with the associated received signal, at least one adjustable component of the electronics unit is set.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 7, 2013
    Assignee: Endress + Hauser GmbH + Co. KG
    Inventors: Volker Dreyer, Armin Wernet
  • Publication number: 20130107417
    Abstract: There is provided a multi-layered ceramic electronic component. The multi-layered ceramic electronic component according to embodiments of the present invention includes: a ceramic element in which a plurality of dielectric layers are stacked; and a plurality of first and second internal electrodes formed on at least one surface of the dielectric layer and alternately disposed in a width direction, wherein, when a distance from one side of the ceramic element to a leading edge of the first internal electrode in a width direction is set to be B, and a distance from one side of the ceramic element to a leading edge in a width direction of the second internal electrode thereof is set to be A, a difference between A and B is 10 to 14% of a width of the first internal electrode or the second internal electrode.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 2, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Su Cho, Hyun Woo Kim, Jae Yeol Choi, Doo Young Kim, Sang Hoon Kwon, Seon Cheol Park
  • Publication number: 20130100586
    Abstract: In a solid electrolytic capacitor, resistance welding is carried out to bond a valve metal substrate and a spacer together while controlling a welding current so that only a bonding material provided in spacers and having a relatively low melting point is melted. At least a portion of the bonding material provided in the spacer penetrates an etching part of the valve metal substrate, and thickness Ta of a core part located at a positive electrode part in the valve metal substrate and thickness Tc of the core part located at a negative electrode part satisfy the requirement of |Tc?Ta|/TcĂ—100?10 [%].
    Type: Application
    Filed: August 29, 2012
    Publication date: April 25, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiroki Kitayama, Akio Katsube
  • Patent number: 8424176
    Abstract: The present invention relates to methods of making and using tunable capacitors and devices. Using the methods described, one or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Patrick Smith, Zhigang Wang
  • Patent number: 8424177
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Publication number: 20130081240
    Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
    Type: Application
    Filed: November 27, 2012
    Publication date: April 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORP
  • Patent number: 8407871
    Abstract: A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer on a substrate; depositing a thin, ceramic dielectric layer over the metal layer; depositing a second thin metal layer over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor from the substrate. The method may also include bending the resulting capacitor into a serpentine arrangement with gaps between the layers that allow venting of evaporated electrode material in the event of a benign failure.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: April 2, 2013
    Assignee: Delphi Technologies, Inc.
    Inventors: Ralph S. Taylor, John D. Myers, William J. Baney
  • Patent number: 8397360
    Abstract: A method of adjustment on manufacturing of a monolithic oscillator including circuit elements and a BAW resonator, this method including the steps of: a) forming the circuit elements and the resonator and electrically connecting them; b) covering the resonator with a frequency adjustment layer; c) measuring the output frequency of the oscillator; d) modifying the thickness of the frequency adjustment layer to modify the output frequency of the oscillator.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: March 19, 2013
    Assignee: STMicroelectronics SA
    Inventors: Pierre Bar, Sylvain Joblot, Jean-Francois Carpentier
  • Publication number: 20130058007
    Abstract: A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 7, 2013
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Patent number: 8383195
    Abstract: In a production method for a laminated electronic component, a ceramic base body is formed by stacking a plurality of ceramic layers, and internal electrodes are formed in the ceramic base body. Lead-out portions of the internal electrodes are exposed from side surfaces of the ceramic base body. Belt-shaped external terminal electrodes are formed on the side surfaces by plating so as to be electrically connected to the exposed portions of the internal electrodes. The distance from an end surface to an external terminal electrode closest to the end surface in the ceramic base body is measured. When the measured distance does not correspond to a predetermined reference value, the ceramic base body is removed as being defective.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: February 26, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Atsushi Sakanaka
  • Patent number: 8375539
    Abstract: A method of manufacturing a low capacitance density, high voltage MIM capacitor and the high density MIM capacitor. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: James Stuart Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8375560
    Abstract: A method for manufacturing a condenser microphone includes forming a diaphragm module using microelectromechanical system (MEMS) techniques. The diaphragm module includes a diaphragm that is deformable by energy of sound waves, and a diaphragm spacer that extends from one side of the diaphragm and controls a tension of the diaphragm. The method further includes providing a backplate with vent holes, aligning the vent holes of the backplate with a central region of the diaphragm, and connecting the backplate to the diaphragm spacer to construct a transducer unit. The diaphragm spacer, the diaphragm and the backplate cooperate to form an air chamber in fluid communication with an environment external to the condenser microphone. The backplate and the diaphragm cooperate to form a condenser. The method further includes enclosing the transducer unit in a housing that includes a shell and a circuit board to form the condenser microphone.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: February 19, 2013
    Assignee: Taiwan Carol Electronics Co., Ltd.
    Inventors: Jean-Yih Tsai, Chung-Ching Lai, Chao-Chih Chang
  • Patent number: 8378221
    Abstract: The underlying purpose of the invention is to manufacture electrical leadthroughs, which are improved with regard to the temperature resistance thereof. Proposed for this purpose is a method for manufacturing an electrical leadthrough, for which at least one metal tube is fused in a glass insulator, whereby a metal rod is mounted in the metal tube by means of soldering-in, prior to or during the sealing of the tube in the glass insulator.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: February 19, 2013
    Assignee: Schott AG
    Inventor: Johann Bernauer
  • Publication number: 20130038981
    Abstract: A method of manufacturing a capacitor includes forming, above a first metal foil, a first dielectric film of a ceramic material containing barium oxide by blowing dry ceramic particles to the first metal foil from a nozzle, forming, in the first dielectric film, a first via conductor connected to the first metal foil and a second via conductor connected to the first metal foil, forming, above the first dielectric film, a first electrode pattern connected to the first via conductor, and patterning the first metal foil to form a second electrode pattern connected to the second via conductor.
    Type: Application
    Filed: October 16, 2012
    Publication date: February 14, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Patent number: 8358494
    Abstract: A laminated ceramic capacitor is provided which is excellent in reliability even when its dielectric ceramic layers thinned. For a dielectric ceramic in a laminated ceramic capacitor, a ceramic is used which includes a main component containing a barium titanate based composite oxide represented by the general formula: (Ba1-h-m-xCahSrmRex)k(Ti1-n-yZrnMy)O3, where Re is La or the like, M is Mg or the like, and the respective relationships of 0.05?x?0.50, 0.02?y?0.3, 0.85?k?1.05, 0?h?0.25, 0?m?0.50, and 0?n?0.40 are satisfied; and an accessory component as a sintering aid, wherein the average grain diameter of crystal grains in a sintered body is 0.6 ?m or less.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: January 22, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hitoshi Nishimura, Noriyuki Inoue, Takafumi Okamoto
  • Patent number: 8347482
    Abstract: A method for manufacturing a ferrite magnet device including a ferrite body and first and second center electrodes arranged so as to intersect and be electrically insulated from each other and a permanent magnet arranged to apply a direct current magnetic field to the ferrite body and a method for manufacturing an isolator or a composite electronic component, which include the ferrite magnet device. A magnetic force of the permanent magnet is adjusted using a measurement jig and a magnetic force adjusting apparatus while the permanent magnet is fixed to a principal surface of the ferrite body.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: January 8, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Hasegawa
  • Publication number: 20130003253
    Abstract: A varactor includes a first PTC region, which comprises a ceramic material with a positive temperature coefficient with respect to the resistance. The varactor also includes a capacitor region that includes a first electrode, a second electrode, and a first dielectric layer arranged between the first electrode and the second electrode. The first PTC region and the capacitor region are connected thermally conductively to one another. The capacitance of the capacitor region can be changed by applying a bias to the first PTC region, the capacitor region or to the first PTC region and the capacitor region.
    Type: Application
    Filed: December 21, 2010
    Publication date: January 3, 2013
    Applicant: EPCOS AG
    Inventor: Andrea Testino
  • Patent number: 8341815
    Abstract: A laminate is prepared in which adjacent internal electrodes are electrically insulated from each other at an end surface at which the internal electrodes are exposed, a space between the adjacent internal electrodes, which is measured in the thickness direction of insulating layers, is about 10 ?m or less when a withdrawn distance of the adjacent internal electrodes from the end surface is about 1 ?m or less, and is about 20 ?m or less when a protruding length of the adjacent internal electrodes from the end surface is at least about 0.1 ?m. In an electroplating step, electroplating deposits deposited on the ends of the adjacent internal electrodes are grown so as to be connected to each other.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: January 1, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuo Kunishi, Yoshihiko Takano, Shigeyuki Kuroda, Akihiro Motoki, Hideyuki Kashio, Takashi Noji
  • Publication number: 20120327553
    Abstract: A high capacitance single layer ceramic capacitor structure having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and bottom surfaces and a metallization pad electrically isolated from the metallization side and bottom surfaces positioned on a top surface of the ceramic body.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 27, 2012
    Inventors: Ali Moalemi, Euan Patrick Armstrong
  • Patent number: 8332996
    Abstract: Provided are a conductive paste composition for inner electrodes and a method of manufacturing a multilayer ceramic capacitor using the same. The conductive paste composition for inner electrodes includes a metal powder having an average particle size ranging from 50 nm to 300 nm, and 4 to 10 parts by weight of a binder resin. The binder resin contains at least one resin selected from the group consisting of a high-molecular-weight polyvinylbutyral resin having a weight-average molecular weight of 250 thousand to 400 thousand, a low-molecular-weight polyvinylbutyral resin having a weight-average molecular weight of 50 thousand to 150 thousand, and a rosin ester.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Han Kim, Hyun Chul Jung, Jwa Jin Yoon, Jae Joon Lee
  • Publication number: 20120297596
    Abstract: In a method of manufacturing a multilayer ceramic component, a ceramic capacitor body is formed from electrode layers and dielectric layers. First and second external terminals are attached on opposite ends of the ceramic capacitor body. The ceramic capacitor body is coated to assist in increasing breakdown voltage. The electrode layers include active electrode layers configured in an alternating manner such that a first end of the active electrodes extends from one end of the ceramic capacitor body inwardly and a next internal active electrode extends from an opposite end of the ceramic capacitor body inwardly. The active electrode layer includes side shields to provide additional shielding.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Applicant: VISHAY SPRAGUE, INC.
    Inventors: JOHN BULTITUDE, JOHN JIANG, JOHN ROGERS
  • Publication number: 20120300369
    Abstract: A solid capacitor having an embedded electrode includes a substrate unit, a first conductive unit, a second conductive unit, a first insulative unit, a third conductive unit, a second insulative unit, and an end electrode unit. The substrate unit includes a substrate body and a conductive body embedded into the substrate body. The substrate body has a lateral opening and a plurality of top openings, and the conductive body has a lateral conductive area exposed from the lateral opening and a plurality of top conductive areas respectively exposed from the top openings. The first conductive unit includes a plurality of first conductive layers respectively covering the top conductive areas. The second conductive unit includes a second conductive layer covering the first conductive layers. The porosity rate of the second conductive layer is larger than that of each first conductive layer.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicants: APAQ TECHNOLOGY CO., LTD., INPAQ TECHNOLOGY CO., LTD.
    Inventors: WEI-CHIH LEE, Ming-Tsung Chen
  • Patent number: 8320102
    Abstract: The present invention relates to a small, low-height capacitor device in which deterioration of characteristics such as leakage current is reduced. The capacitor device includes a supporting substrate 1; at least one capacitor element 21 disposed on the supporting substrate 1, including a dielectric layer 4 and a pair of electrodes 2 and 5 sandwiching the dielectric layer 4; and a sealant that seals the capacitor element 21 through a space 22. The dielectric layer 4 has an exposed part 23 exposed in the space 22. According to this structure, deterioration of the dielectric layer can be prevented, and a capacitor device exhibiting a good leakage current characteristic is obtained.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: November 27, 2012
    Assignee: KYOCERA Corporation
    Inventors: Hideharu Kurioka, Hiroshi Katta, Yoshihiro Okubo
  • Patent number: 8320101
    Abstract: In a method for manufacturing a multilayer electronic component, after a plating layer for forming an external electrode is formed on an end surface of a laminate, conditions for heat-treating the laminate are set such that interdiffusion layers have ends which face internal electrodes and which are spaced from the end surface of the laminate at a distance of about 0.5 ?m to about 1.9 ?m.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: November 27, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shunsuke Takeuchi, Kenichi Kawasaki, Akihiro Motoki, Makoto Ogawa
  • Publication number: 20120293917
    Abstract: A method for forming a hermetically sealed capacitor including: forming an anode; forming a dielectric on the anode; forming a conductive layer on the dielectric thereby forming a capacitive element; inserting the capacitive element into a casing; electrically connecting the anode to an exterior anode connection; electrically connecting the cathode to an exterior cathode connection; filling the casing with an atmosphere comprising a composition, based on 1 kg of atmosphere, of at least 175 g to no more than 245 g of oxygen, at least 7 g to no more than 11 g of water, at least 734 grams to no more than 818 grams of nitrogen and no more than 10 grams of a minor component; and hermetically sealing the casing with the atmosphere with the capacitive element contained in the casing.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Applicant: Kemet Electronics Corporation
    Inventors: Qingping Chen, Yurl Freeman, Steven C. Hussey
  • Publication number: 20120287553
    Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 15, 2012
    Applicant: INTERMOLECULAR, INC.
    Inventors: Karthik Ramani, Wim Deweerd, Hiroyuki Ode
  • Publication number: 20120281336
    Abstract: A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable MOS capacitor structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the equivalent capacitor area of the MOS structure by increasing or decreasing its DC voltage with respect to another terminal of the device, in order to change the capacitance over a wide ranges of values. Furthermore, the present invention decouples the AC signal and the DC control voltage avoiding distortion and increasing the performance of the device, such as its control characteristic. The present invention is simple and only slightly dependent on the variations due to the fabrication process. It exhibits a high value of capacitance density and, if opportunely implemented, shows a linear dependence of the capacitance value with respect to the voltage of its control terminal.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Inventors: Fabio Alessio Marino, Paolo Menegoli
  • Patent number: 8302270
    Abstract: A method of manufacturing a capacitor-embedded printed circuit board that includes fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: November 6, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woon-Chun Kim, Sung Yi, Hwa-Sun Park, Hong-Won Kim, Dae-Jun Kim, Jin-Seon Park
  • Publication number: 20120275081
    Abstract: A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.
    Type: Application
    Filed: April 16, 2012
    Publication date: November 1, 2012
    Inventors: Young Ghyu AHN, Byoung Hwa Lee, Min Cheol Park, Sang Soo Park, Dong Seok Park
  • Publication number: 20120268862
    Abstract: A high-frequency and low-dielectric-constant ceramic dielectric material matched with nicket internal electrode and a method for producing capacitor using same. The ceramic dielectric material consists of main crystalline phase, modifying additive and sintering flux. The main crystalline phase is MgZrxSi(1?x)O3, wherein 0.05?x?0.15. The modifying additive is one or more of MnO2, Al2O3, CaO, Bi2O3 and TiO2, and the sintering flux is one or more of B2O3, SiO2, ZnO, Li2O, K2O and BaO. The ceramic dielectric material has good uniformity, and excellent dielectric properties, meets the requirements of COG characteristics in EIA standard, and meets the environmental requirements. The ceramic dielectric material can be sintered under the reducing atmosphere and can be matched with nickel electrodes. The chip multilayer ceramic capacitor made of the ceramic dielectric material and nickel internal electrodes has stable performance.
    Type: Application
    Filed: December 20, 2010
    Publication date: October 25, 2012
    Inventors: Beibei Song, Yongsheng Song, Fangce Mo, Juan Li, Xiaoguo Wang, Jinghua Guo
  • Publication number: 20120250219
    Abstract: A multilayer ceramic capacitor component includes a ceramic capacitor body having opposite ends and comprised of a plurality of electrode layers and dielectric layers, first and second external terminals attached to the ceramic capacitor body. The plurality of electrode layers include a plurality of alternating layers of active electrodes extending inwardly from alternating ends of the ceramic capacitor body. The capacitor may include a plurality of side shields disposed within the plurality of alternating layers of active electrodes to provide shielding with the alternating layers of active electrodes having a pattern to increase overlap area to provide higher capacitance without decreasing separation between the alternative layers of active electrodes. The capacitor may have a voltage breakdown of 3500 volts DC or more in air. The capacitor may have a coating. The capacitor provides improved resistance to arc-over, high voltage breakdown in air, and allows for small case size.
    Type: Application
    Filed: February 27, 2012
    Publication date: October 4, 2012
    Applicant: Vishay Sprague, Inc.
    Inventors: John Bultitude, John Jiang, John Rogers
  • Publication number: 20120233828
    Abstract: In a manufacturing method for a monolithic ceramic electronic component, a ceramic paste is applied by using an application plate to a side surface of each of a plurality of green chips arrayed in row and column directions which are obtained after cutting a mother block. In the applying step, the ceramic paste is transferred to the side surface by moving the green chips and the application plate relative to each other in the direction in which the side surface extends while separating the green chips from the application plate, in a state where the ceramic paste is connected to both the green chips and the application plate.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 20, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Togo MATSUI, Minoru DOOKA, Hiroyoshi TAKASHIMA, Kenichi OKAJIMA
  • Publication number: 20120236467
    Abstract: In one aspect of the present invention, an ultracapacitor has a first plate, a second plate and a separator sandwiched between the first plate and the second plate. Each of the first plate and the second plate includes a substrate, first nanostructures formed on the substrate, and second nanostructures, being different from the first nanostructures, attached to the first nanostructures. The first nanostructures include carbon nanotubes (CNTs) or carbon fibers/nanofibers (CFs). The second nanostructures include nano-particles of an active material including MnO2.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 20, 2012
    Applicant: Vanderbilt University, Center for Technology Transfer and Commercialization
    Inventors: Weng Poo Kang, Supil Raina, SiYu Wei, Shao-Hua Hsu
  • Patent number: 8268019
    Abstract: A powder compaction press having opposed rib and channel punches which are interleaved and a production method are used to produce capacitor elements having a uniform compaction density and which are free of surface imperfections.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: September 18, 2012
    Assignee: Kemet Electronics Corporation
    Inventor: Jeffrey P. Poltorak
  • Publication number: 20120229951
    Abstract: The present invention relates to a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a ceramic body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side; a plurality of inner electrodes formed within the ceramic body and having respective one ends exposed to the third side and the fourth side; and outer electrodes formed on the third side and the fourth side and electrically connected to the inner electrodes. A shortest distance from distal edges of an outermost inner electrode among the plurality of inner electrodes to the first side or the second side is smaller than a shortest distance from distal edges of a central inner electrode to the first side or the second side.
    Type: Application
    Filed: October 28, 2011
    Publication date: September 13, 2012
    Inventor: Hyung Joon KIM
  • Publication number: 20120229950
    Abstract: There are disclosed a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes: a ceramic body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side, a plurality of inner electrodes formed within the ceramic body, and outer electrodes formed on the third side and the fourth side and electrically connected to the inner electrodes. A distance from distal edges of the inner electrodes to the first side or the second side of the ceramic body is 30 ?m or less.
    Type: Application
    Filed: October 25, 2011
    Publication date: September 13, 2012
    Inventors: Hyung Joon Kim, Dae Bok Oh
  • Publication number: 20120229955
    Abstract: A solid electrolytic capacitor that includes an anode body, a dielectric overlying the anode body, a solid electrolyte overlying the dielectric, and a colloidal particle coating that overlies the solid electrolyte. The coating is formed from a colloidal particle dispersion. The particles of the dispersion contain at least two different polymer components—i.e., a conductive polymer and a latex polymer. One benefit of such a coating is that the presence of the latex polymer can help mechanically stabilize the capacitor during encapsulation due to its relatively soft nature. This helps limit delamination of the solid electrolyte and any other damage that may otherwise occur during formation of the capacitor. Furthermore, the latex polymer can also enhance the ability of the particles to be dispersed in an aqueous medium, which is desirable in various applications.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: AVX CORPORATION
    Inventor: Martin Biler
  • Publication number: 20120229952
    Abstract: There are provide a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a multilayer body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side, inner electrodes formed in the multilayer body and formed to be spaced apart from the third side or the fourth side by a predetermined distance, groove portions formed on at least one of top and bottom surfaces of the multilayer body and formed parallel to the third or fourth side by a predetermined distance from the third side or the fourth side, and outer electrodes extended from the third side and the fourth side to the top surface or the bottom surface of the multilayer body to cover the groove portions.
    Type: Application
    Filed: October 31, 2011
    Publication date: September 13, 2012
    Inventor: Hyung Joon KIM
  • Patent number: 8256077
    Abstract: A method for forming a capacitor dielectric includes depositing a tantalum oxide layer over a substrate, performing a post-treatment on the tantalum oxide layer to provide the tantalum oxide layer with a tetragonal phase, and depositing a zirconium oxide layer over the tantalum oxide layer such that the zirconium oxide layer has a tetragonal phase.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Patent number: 8256078
    Abstract: A method for forming a plurality of strips to be used for formulating high-breakdown strength and high-temperature capacitors is disclosed. The method includes forming a metalized substrate having a particular pattern, masking a portion of the metalized substrate, coating the metalized substrate with a dielectric material and removing the masking material and thus the dielectric layer from a portion of the metalized layer to form a contact surface. In lieu of placing a masking material on the metalized substrate, the exposed contact area can be formed by shielding a portion of the metalized substrate while depositing the dielectric layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: September 4, 2012
    Assignee: Faradox Energy Storage, Inc.
    Inventors: William M. Balliette, Keith D. Jamison
  • Patent number: 8250747
    Abstract: A method is provided to mount a capacitor array onto a circuit board formed with first leads for connecting power lines to each other and a second lead for grounding. The method uses one of a first connection method of connecting such that first and second capacitor sections are parallel to each other, third capacitor section is in series with the parallel first and second capacitor sections; a second connection method of connecting such that the first to third capacitor sections are in series in sequence; and a third connection method of connecting such that the first and second capacitor sections are in series with each other without using the third capacitor section.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 28, 2012
    Assignee: TDK Corporation
    Inventor: Masaaki Togashi
  • Patent number: 8248754
    Abstract: A dielectric ceramic contains a barium titanate and Li. In the dielectric ceramic, the following inequalities are satisfied: 0.5?e?6.0, 0.06<Rg<0.17, and ?g<0.075, where e is the content, in molar parts, of Li with respect to 100 molar parts of the titanate; Rg is the average size, in ?m, of grains in the dielectric ceramic; and ?g is the standard deviation, in ?m, of the size of the grains.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: August 21, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tomonori Muraki, Tomoyuki Nakamura, Makoto Matsuda, Hironori Suzuki, Takehisa Sasabayashi, Masayuki Ishihara, Akihiro Shiota
  • Publication number: 20120204389
    Abstract: A method of manufacturing a solid electrolytic capacitor includes steps (a) to (e). The steps (a) and (b) provide anode and cathode terminals to an insulating base respectively. The step (c) mounts a capacitor element on the insulating base. The step (d) coats the capacitor element with enclosure resin. The step (e) separates a first region of the insulating base to which the anode and cathode terminals are provided and on which the capacitor element is mounted from a second region of the insulating base which is different from the first region. The step (a) includes a step (a1) forming a first through hole in the insulating base, and a step (a2) plating an inner surface of the first through hole. The step (b) includes a step (b1) forming a second through hole in the insulating base, and a step (b2) plating an inner surface of the second through hole.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yasuko Ibata, Hiroya Nishimoto, Takeshi Takamatsu
  • Patent number: 8240016
    Abstract: A method for manufacturing a multilayer electronic component includes a step of preparing a laminate which includes a plurality of stacked insulator layers and a plurality of internal electrodes extending along the interfaces between the insulator layers, and in which an end of each of the plurality of internal electrodes is exposed at a predetermined surface corresponding to one of the first and second end surfaces; a step of forming external electrodes on the predetermined surfaces; and a step of forming thick-film edge electrodes at edge portions. The step of forming external electrodes includes a step of attaching a plurality of conductive particles having a particle size of about 1 ?m or more to the predetermined surfaces of the laminate, and a step of performing plating directly on the predetermined surfaces to which the conductive particles are attached.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: August 14, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akihiro Motoki, Makoto Ogawa, Kenichi Kawasaki, Shunsuke Takeuchi
  • Publication number: 20120198673
    Abstract: [Problem to be Solved] To provide a helical capacitor for controlling a high-frequency power which flows in power lines, and a manufacturing method of the helical capacitor. [Solution] A helical capacitor is constituted by helically spiraling a belt shape capacitor line 1001 which includes an internal metal body to be a helically spiraled belt-shape internal electrical conductor, a dielectric film covering the internal electrical conductor, and an electrically conductive layer covering the dielectric film. The capacitor line of belt shape 1001 can be wrapped around the internal support body 1200. Internal metal body lead terminals 1311, 1321 are respectively formed at both ends of the internal metal body, and electrically conductive layer lead terminals 1312, 1322 can be respectively formed at both ends of the electrically conductive layer.
    Type: Application
    Filed: April 13, 2012
    Publication date: August 9, 2012
    Applicant: NEC CORPORATION
    Inventor: Koichiro MASUDA
  • Patent number: 8230576
    Abstract: Provided is a method of manufacturing a capacitive electromechanical transducer, including: forming a lower electrode layer on a substrate; forming a sacrificial layer on the lower electrode layer; forming by application a resist layer on the sacrificial layer to form a cavity pattern; forming an insulating layer above regions including a region that contains the resist layer used to form the cavity pattern, and then removing a part of the insulating layer that is formed above the resist layer along with the resist layer, thereby leaving the insulating layer in the other regions than the region where the cavity pattern has been formed; forming a vibrating film above the region where the cavity pattern has been formed and the regions where the insulating layer remains; and removing the sacrificial layer to form a cavity.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Masaki
  • Patent number: 8230564
    Abstract: A millimeter wave transmission line filter having a plurality of filter pole determining coupled cavities fabricated with a multiple lithographic layer micromachining process. The filter cavities are oriented perpendicular to an underlying substrate element in order to achieve micromachining, fabrication and accuracy advantages. Multiple filters can be used in a frequency multiplex arrangement as in a duplexer. Radio frequencies in the 15 to 300 gigahertz range are contemplated.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 31, 2012
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: J. Robert Reid, Jr.
  • Publication number: 20120176226
    Abstract: A MOS RF surveillance and/or identification tag, and methods for its manufacture and use. The tag includes an interposer, an antenna/inductor, and integrated circuitry on the interposer. The integrated circuitry has a lowest layer in physical contact with the interposer. The method of manufacture includes forming a lowest layer of integrated circuitry on an interposer, forming successive layers of the integrated circuitry on the lowest layer of integrated circuitry, and attaching an electrically conductive functional layer to the interposer. Alternatively, an electrically conductive structure may be formed from a functional layer attached to the interposer. The method of use includes causing/inducing a current in the present tag sufficient for it to generate, reflect or modulate a detectable electromagnetic signal, detecting the signal, and optionally, processing information conveyed by the detectable electromagnetic signal.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Inventors: J. Devin MACKENZIE, Vikram Pavate
  • Patent number: 8214984
    Abstract: A method for producing a multilayer component is described. A stack of green foils, to which inner electrodes including palladium oxide are applied, is sintered. The sintered stack is provided with a silver paste on two or more sides for outer electrodes that are burned into the sintered stack in a further temperature step.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: July 10, 2012
    Assignee: EPCOS AG
    Inventors: Gerhard Bisplinghoff, Axel Pecina
  • Patent number: 8209829
    Abstract: A method of fabricating an electronic device includes selectively forming a glass layer on a ceramic substrate by printing, baking the glass layer, and forming a capacitor on the glass layer, the capacitor including metal electrodes and a dielectric layer interposed between the metal electrodes.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 3, 2012
    Assignees: Taiyo Yuden Co., Ltd., Fujitsu Limited
    Inventors: Takeo Takahashi, Xiaoyu Mi, Satoshi Ueda