Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Patent number: 5724726
    Abstract: A method of making a semiconductor device having a lead-on-chip structure includes bending a die pad extending from an outer frame outwardly from the outer frame. Thereafter, with the die pad in a convenient position, a semiconductor chip is die-bonded to the die pad. Thereafter, the die pad is bent back toward the outer frame so that it is generally parallel to but spaced from the outer frame with leads extending from the outer frame being generally parallel to the semiconductor chip. Electrodes of the semiconductor chip are connected by wire-bonding to the leads extending from the outer frame. After resin molding, the outer frame lying outside the resin package is severed and removed, completing the lead-on-chip semiconductor device.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: March 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Naoto Ueda, Yoshirou Nishinaka, Shunichi Abe, Hideyuki Ichiyama
  • Patent number: 5724717
    Abstract: A method for making an electrical article includes: providing a conductive lead frame having a first contact section (129) adapted to be electrically and mechanically secured to a discrete second conductive member (144) and a holding section proximate the first contact section (129) adapted to hold a portion of the discrete second conductive member (144); positioning a discrete second conductive member (144) on the holding section with a first connecting end (146) in engagement with the first contact section (129)of the lead frame; terminating the second member (144) to the contact section (129), the lead frame and the second conductive member (144) defining a subassembly; overmolding the subassembly with dielectric material at least over portions of the lead frame and the second conductive member; and removing at least the holding section from the overmolded subassembly thereby defining an electrical article.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: March 10, 1998
    Assignee: The Whitaker Corporation
    Inventors: Stephen Daniel Gherardini, Scott Keith Mickievicz, Richard Nicholas Whyne, John Anthony Woratyla
  • Patent number: 5715593
    Abstract: There is provided a plastic-packaged semiconductor integrated circuit including (a) an inner lead having a lead-on-chip (LOC) type structure,(b) a ball grid array (BGA) type terminals for electrically connecting the inner lead to an external circuit, and (c) an outer package made of thermosetting resin for shielding the inner lead therein.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: February 10, 1998
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 5706577
    Abstract: A no fixture method to cure die attach for bonding IC dies (16) to substrates in which a solvent is applied to top and bottom surfaces of a thermoplastic die attach film (14), prior to component placement of the die (16) on a lead frame die support pad or on a printed circuit board PCB (12). The die attach film (14) is bonded to the IC die (16) and the lead frame, or to the IC die (16) and the printed circuit board PCB (12) upon drying of the solvent.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 13, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Linden T. Halstead
  • Patent number: 5692296
    Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: December 2, 1997
    Assignee: LSI Logic Corporation
    Inventor: Patrick Variot
  • Patent number: 5685073
    Abstract: A printed circuit board modular assembly is disclosed. The disclosed invention comprises a first printed circuit board having an electronic terminal portion for providing electrical connection to the first printed circuit board; a second printed circuit board having an electrical terminal portion for providing electrical connection to the second printed circuit board; a spacing member disposed between the first and second printed circuit boards; and electrical signal transmission contacts situated on the spacing member for providing electrical connection between the first printed circuit board and the second printed circuit board.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: November 11, 1997
    Assignee: Compaq Computer Corporation
    Inventors: H. Scott Estes, James J. Ganthier
  • Patent number: 5685069
    Abstract: A method of making a device for establishing an electric contact with conductors of an electric apparatus includes the following steps: forming a one-piece leadframe from sheet metal; securing the leadframe pattern to an electrically insulating carrier; severing the conductor into individual conductor strips; mounting an electric and/or electronic component on the carrier; and electrically contacting the components with selected conductor strips.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: November 11, 1997
    Assignee: Robert Bosch GmbH
    Inventors: Cornelius Peter, Peter-Josef Bauer
  • Patent number: 5683943
    Abstract: A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the first and the second major surfaces of a blank. The first and the second major surfaces of the blank are etched through the first and the second resist pattern by a first etching process using a first etchant to form a first recess corresponding to the first opening and second recesses corresponding to the second recesses in the first and the second major surfaces, respectively. The first recess is filled up with an etch-resistant layer. The second major surface is etched through the second resist pattern by a second etching process using a second etchant so that portions of the blank corresponding to the second openings of the second resist pattern are etched through to form the tips of the inner leads.
    Type: Grant
    Filed: June 12, 1995
    Date of Patent: November 4, 1997
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Junichi Yamada
  • Patent number: 5682673
    Abstract: A mold is provided for use in encapsulating integrated circuit (IC) dies attached to die attach pads of lead frames, wherein the mold has one or more support elements in cavities of the mold for supporting the die attach pad portions of the lead frame while the mold is closed on the lead frame and encapsulation material is injected to encapsulate the IC dies and die attach pads. The support elements are, in a preferred embodiment, pins extending from the surfaces of the cavities in the mold, and the pins keep the die attach pads from moving into contact with surfaces of the cavities, so die attach pads or dies are not exposed in finished packages. In a preferred embodiment the pins each are tapered in the extended portion, so the amount of exposure of the die attach pad is absolutely minimized. In another embodiment, the support elements are retractable.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: November 4, 1997
    Assignee: IPAC, Inc.
    Inventor: Gerald K. Fehr
  • Patent number: 5678301
    Abstract: A method for forming an interconnect for establishing electrical communication with a semiconductor die is provided. The method includes: providing a microbump tape and then mounting the tape to a substrate with a compliant layer therebetween. The microbump tape includes an insulating film having a pattern of microbump contact members corresponding to a pattern of bond pads on the die. The compliant layer can be formed of a curable adhesive such as a silicone elastomer. A coupon containing a plurality of microbump tapes can be mounted to a substrate wafer which can then be singulated to form a plurality of interconnects. The interconnects can be used with a testing apparatus for testing unpackaged semiconductor dice.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: October 21, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Derek Gochnour, Warren M. Farnworth
  • Patent number: 5679194
    Abstract: A substantially continuous layer of a first metal such as copper is provided with strips of a second metal such as gold by selective electroplating of the second metal. A dielectric support layer is provided in contact with the first metal layer, and the first metal layer is etched to leave strips of the first metal contiguous with the strips of the second metal, thereby providing composite leads with the first and second metal strips connected in series. The process provides simple end economical methods of making microelectronic connection components with leads having a flexible, fatigue resistant lead potion formed from a precious metal.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: October 21, 1997
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John W. Smith
  • Patent number: 5671531
    Abstract: A method for manufacturing an apparatus includes the steps of forming a plurality of circuit regions on a single master print circuit board, soldering one or more interconnection leads upon corresponding pad electrodes of the foregoing circuit regions, in a state that the plurality of circuit regions are connected with each other mechanically to form the master print circuit board, and dividing the master print circuit board into individual printed circuit boards each corresponding to one of the circuit regions on the master print circuit board.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: September 30, 1997
    Assignee: Fujitsu, Ltd.
    Inventor: Hiroshi Mugiya
  • Patent number: 5671525
    Abstract: A method of manufacturing a hybrid chip card comprises the steps of providing a card body; forming a cavity in the card body; mounting the electronic module in the cavity of the card body; and connecting an antenna to the electronic module. The cavity opens out on a face of the card body and is adapted for receiving an electronic module. The electronic module includes an integrated circuit chip. The mounting step further includes the step of exposing a plurality of contact pads of the electronic module on the outer surface of the card. The plurality of contact pads permit contact communication between the electronic module and the chip card reader, and the antenna permits contact-free communication between the electronic module and the chip card reader. The hybrid chip card thus manufactured is capable of both contact and contact-free communication with a chip card reader.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: September 30, 1997
    Assignee: Gemplus Card International
    Inventor: Jean-Christophe Fidalgo
  • Patent number: 5665651
    Abstract: Outer leads are buried in a package. At least the contact portions of the outer leads which are connected to a circuit board are exposed from the package and the exposed portions make the same flat surfaces as the package surface. When forming the package, the outer leads are used as the side wall of a mold forming mold, and therefore, they are formed thicker than inner leads inside the package. Thus, the package thickness can be made equal to the thickness of the outer leads.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: September 9, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Asada, Masahiko Hori, Shinji Takei
  • Patent number: 5661900
    Abstract: A method of fabricating a semiconductor device comprising the steps of providing an encapsulated semiconductor device bonded to a lead frame, providing a support ring formed of a material which softens when subjected to one of ultrasonic energy or formed of a material which softens when subjected to heat insufficient to cause sufficient expansion of said lead frame relative to said support ring to cause buckling of the leads of said lead frame, preferably thermoplastic and preferably polyphenylene sulfide, disposing leads of said lead frame over said support ring and causing said leads to embed in said support ring by applying ultrasonic energy to said support ring or by applying heat to said support ring insufficient to cause sufficient expansion of said lead frame relative to said support ring to cause buckling of the leads of said lead frame. The lead frame is preferably formed of gold plated copper, solder plate or tin plate.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: September 2, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Robert N. McLellan, Anthony M. Chiu, Paul J. Hundt, William K. Dennis
  • Patent number: 5663104
    Abstract: A method of manufacturing a semiconductor device for power supply use. A void is formed on a mating face of a pair of metallic molds. Moreover, an island of a lead frame is arranged in the void under the condition that the island is spaced from a surface of the void. A thermosetting resin is injected into the void so that the island and a semiconductor element assembled onto one face of the island are sealed by resin. At this time, a clearance between the other face of the island and one face of the metallic mold opposed to the other face of the island is set to be 2.0 to 0.3 mm and is smaller than a clearance between one face of the island and the other face of the metallic mold opposed to one face of the island. One face of the metallic mold is subjected to satin finish on which the maximum surface roughness H.sub.max is in a range from 3 to 10 .mu.m.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: September 2, 1997
    Assignee: Rohm Co., Ltd.
    Inventor: Jun Fukuyama
  • Patent number: 5660461
    Abstract: A low cost LED array is formed from a plurality of modular units that are snapped together. Each modular unit consists of one or more U-shaped lead frame substrates which are overmolded with a thermoplastic insulator material. The lead frame substrates act as heat dissipators. The LEDs are then bonded onto the upper surfaces of the lead frame substrates. A reflector unit is separately molded and has one cone-shaped reflector for each light emitting diode. The reflector unit is aligned and affixed to the top of the lead frame unit such that the LED is disposed in the center of each cone. Each of the reflector units has several dovetail-shaped connectors which enable the completed module to be connected to adjacent modules to form the array. The modules are then electrically connected together in series or in parallel according to the particular application. The arrays may be used for plant growth or in photodynamic therapy.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: August 26, 1997
    Assignee: Quantum Devices, Inc.
    Inventors: Ronald W. Ignatius, Todd S. Martin
  • Patent number: 5661086
    Abstract: Method for producing semiconductor devices comprises a first step in which a plurality of metal substrates each of which is provided with a die mounting region at a central portion thereof are connected in series to produce a train of connected metal substrates by means of first connecting tabs and a pair of first side rails each of which is provided with first positioning pilot apertures are connected to the train by means of second connecting tabs to produce a metal substrate frame, a second step in which a plurality of circuit substrates each of which is provided with a lead pattern around an opening formed at the central portion thereof are connected in series by means of third connecting tabs to produce a train of connected circuit substrates and a pair of second side rails each of which is provided with second positioning pilot apertures are connected by fourth connecting tabs to produce a circuit substrate frame, a third step in which both frames are alinged with each other making use of the first and
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: August 26, 1997
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Takashi Nakashima, Keiji Takai, Kouji Tateishi
  • Patent number: 5659950
    Abstract: A method of forming a package assembly (10) including a package (12) that encapsulates an electronic die. A leadframe (30) has edge rails (32), and the die is disposed on the leadframe. The package is formed around the die to encapsulate it, and the leadframe is trimmed to provide a plurality of leads (14) protruding from a first side of the package. This trimming also provides a support (16) connected to a second side of the package. The support is bent to be substantially orthogonal to the common plane containing the leads. A mounting tip (26) on the support is thus disposed outside of the common plane. This support improves the rigidity and natural bending frequency of the package assembly.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: August 26, 1997
    Assignee: Motorola, Inc.
    Inventors: Victor J. Adams, David J. Dougherty
  • Patent number: 5656550
    Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: August 12, 1997
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Masaki Waki
  • Patent number: 5653020
    Abstract: The invention relates to a method for forming a plastic package for an integrated electronic semiconductor device to be encapsulated within a plastic body, being of the type which comprises the step of molding said plastic body so as to fully enclose a semiconductor element, on which an integrated electronic circuit has been formed and which is placed onto a metal leadframe connected electrically to said integrated electronic circuit and carrying a plurality of terminal leads for external electric connection. To compensate the outward bends uncontrollably undergone by the plastic body due to thermal stresses during the molding step, a mold is used which has a cavity delimited by perimeter walls which define a concave-shaped volume. Preferably, at least one of the large walls, a bottom wall and a top wall, has a curvature inwardly of said mold cavity. The curvature values are predetermined to compensate any outward curvature undergone by corresponding surfaces of said plastic body during the molding step.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: August 5, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Luigi Romano', Fulvio Tondelli
  • Patent number: 5647121
    Abstract: A socket system that comprises a printed circuit board; an electrical module; and a socket having a hollow core. The socket holds the electrical module and is capable of electrically coupling the electrical module to the printed circuit board. The electrical module has at least one electrical lead. The socket has at least one electrical lead capable of electrically coupling with the electrical lead(s) of the electrical module. The electrical module comprises a second printed circuit board having a first and second surface; a lithium battery positioned on the first surface of the second printed circuit board and electrically coupled with the second printed circuit board, a crystal positioned on the first surface of said second printed circuit board and electrically coupled with the second printed circuit board, and an integrated circuit positioned on the second surface of the second printed circuit board.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 15, 1997
    Assignee: Dallas Semiconductor Corporation
    Inventors: Neil McLellan, Mike Strittmatter, Joseph Patrick Hundt, Christopher M. Sells, Francis A. Scherpenberg
  • Patent number: 5640746
    Abstract: A method of hermetically encapsulating a crystal oscillator using a thermoplastic shell. A first step (102) includes molding a thermoplastic shell defining a cavity around a periphery of oscillator locations on a lead frame. A second step (104) includes attaching oscillator components including a piezoelectric element, capacitors and an integrated circuit to the lead frame. A third step (106) includes dispensing an encapsulant within the cavity defined by the thermoplastic shell to encapsulate the oscillator components. A fourth step (108) includes curing the encapsulant. A last step (110) includes excising the oscillator from the lead frame and the leads are formed for mounting.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: June 24, 1997
    Assignee: Motorola, Inc.
    Inventors: Thomas A. Knecht, Steven L. Wille
  • Patent number: 5638596
    Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 17, 1997
    Assignee: LSI Logic Corporation
    Inventor: John McCormick
  • Patent number: 5637858
    Abstract: A method for producing identity cards which uses card bodies with standardized outer dimensions and wherein carrier elements with different dimensions are incorporated in the card bodies, the carrier elements having at least one integrated circuit connected electroconductively with coupling elements used for communication of the integrated circuit with external devices, characterized in thatadapter elements formed with uniform outer dimensions are provided for receiving the different carrier elements,for receiving the adapter elements the card bodies are provided with recesses corresponding in shape and size substantially to the outer dimensions of the adapter elements, andthe carrier elements are connected with the card body via the adapter elements.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: June 10, 1997
    Assignee: Giesecke & Devrient GmbH
    Inventors: Joachim Hoppe, Arno Hohmann
  • Patent number: 5636430
    Abstract: An improved lead working machine has a mechanism portion that supplies a leadframe 100, a working and handling portion that performs the necessary working processes on the work as it is fed consecutively, and a receiving mechanism portion that receives the worked products. A plurality of dies 40 and 42 for performing working processes including resin removal, dam bar cutting and lead forming, etc. are provided in tandem in the working and handling portion such that the direction of the working line of the first die 40 aligns with that of the subsequent die 42. A rail mechanism for guiding the lateral edge portions of the leadframe to be transported from the first die 40 to the subsequent die 42, as well as a pickup mechanism, by which a piece part that has been obtained by separating the product portion of the leadframe 100 in the first die 40 is picked up and transported to the subsequent die 42, are provided in positions intermediate between the dies 40 and 42.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: June 10, 1997
    Assignee: Apic Yamada Corporation
    Inventors: Shigeyuki Uchiyama, Yoshinao Todoroki, Shin Ando, Minoru Harayama
  • Patent number: 5633205
    Abstract: A lead frame includes a plurality of inner leads, each of the inner leads having at least one surface defining a bonding area and two opposed side edges. The tip ends of the plurality of inner leads are connected by a connecting part so that the inner leads are arranged side by side with respect to each other. The connecting part is integrally and simultaneously formed with the inner leads by an etching process. Each of the inner leads has recesses on the two side edges at a position, between the bonding area and the connecting part, on a cutting line along which the plurality of inner leads are to be cut and separated into individual inner leads.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: May 27, 1997
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kenichiro Tsuchiya, Toshiaki Ishizaki, Masahiro Iwabuchi
  • Patent number: 5633206
    Abstract: A process for manufacturing a lead frame having a pad, inner leads, outer leads and dambars, the lead frame being coated with a film on the back surface of the pad, which includes the steps of preparing a lead frame having a pad, inner leads and outer leads; placing a polyamic acid film on the back surface of the pad without using adhesive; and thermally compressing the polyamic acid film by using a heat; generator, to form polyimide film and simultaneously adhere that to the polyimide film the back surface of the pad.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: May 27, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang H. Kim, Sung M. Sim, In P. Hong, Sang G. Lee
  • Patent number: 5632083
    Abstract: A lead frame fabricating method and a lead frame fabricating apparatus are provided which can easily fabricate lead frames of fine pattern at a high speed, can improve dimensional accuracy and quality of the lead frames after the fabrication, and can realize mass-production at a lower cost. To this end, when cutting a metal plate 1101 by irradiation of a laser beam, a laser beam 1011 emitted in the form of pulses and having a circular section is converted by a beam section transformer 1020 into a laser beam 1012 having an elongate elliptic section. The section of the laser beam 1012 is rotated on its optical axis by a beam rotating device 1030 so that the lengthwise direction of the section of the laser beam 1012 is coincident with the lengthwise direction of each of inner leads 1013. An optical axis of a laser beam 1015 is revolved along each of concentric paths 161 to 174 around the original optical axis given when the laser beam 1011 is emitted.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: May 27, 1997
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Nobuhiko Tada, Naoki Miyanagi, Yoshiaki Shimomura, Shigeyuki Sakurai, Yoshinari Nagano
  • Patent number: 5631193
    Abstract: The present invention provides a method and apparatus for fabricating thermally and electrically improved electronic integrated circuits by laminating one or more lead frames to a standard integrated circuit package such as, for example, a thin small outline package (TSOP). The lead frame laminated to the package enhances thermal conduction of heat from the integrated circuit package. A heat spreader may also be utilized to improve heat transfer and can be further used as a ground plane to improve signal quality by reducing electrical circuit noise. Achieving improved thermal transfer characteristics from an integrated circuit package results in better dissipation of heat from the integrated circuit package and results in more reliable operation thereby. Using standard commercially available integrated circuit packages such as TSOP allows economical and rapid fabrication of thermally and electrically superior electronic circuits for applications that demand high reliability and performance.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: May 20, 1997
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5629239
    Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads. The process avoids the need for especially fine etching to form notches in the lateral edges of the leads.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: May 13, 1997
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine Karavakis, Joseph Fjelstad
  • Patent number: 5623123
    Abstract: Semiconductor device package 53 having a lead frame with a mounting pad 31 smaller than the IC chip 10 mounted thereon, and a method of making a semiconductor device package based on wire bonding using a heater insert 38 with a mounting pad insertion concave part 51. Separation between the mounting pad and an encapsulating resin is eliminated, cracks are not created in the resin, or are considerably reduced, and warpage of the package can be prevented. Also, bonding of wires between leads and respective bonding pads 17 on the chip 10can be executed stably and efficiently.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: April 22, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Norito Umehara
  • Patent number: 5622731
    Abstract: A post mold curing apparatus for use in association with a molding line system for providing plastic encapsulated semiconductor chips mounted on leadframes is disclosed which includes a leadframe carrier having a rotary, substantially cylindrical shaped assembly for containing and moving a plurality of semiconductor chips and their associated leadframe strips into both an elevated temperature post mold curing region and into a lower temperature cool-down region. Each of the leadframe strips with their associated semiconductor chips are sequentially inserted into cavity regions located in the cylindrical assembly to assist in moving each of the plurality of leadframe strips through the elevated temperature post mold curing region, and subsequently, each of the leadframe strips with their associated semiconductor chips are removed from the cavity regions after passing through the lower temperature cool-down region.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: April 22, 1997
    Inventor: Richard H. J. Fierkens
  • Patent number: 5622896
    Abstract: A method of providing an ultra-thin (<1 nm) silicon-oxide layer on a substrate surface, for example, of a metal. A film of a solution of a polyorganosiloxane is applied to the substrate surface. After drying, the polyorganosiloxane is completely converted to said silicon-oxide layer by means of an UV-ozone treatment. Such an ultra-thin silicon-oxide layer sufficiently protects a metal surface against corrosion. In addition, the silicon-oxide layer can be silanized with the customary silane coupling agents to improve the bond with polymers. The method can very suitably be used, for example, to treat metal leadframes for ICs and to provide a bonding layer for indium tin oxide on polyacrylate for a passive plate of LC displays.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: April 22, 1997
    Assignee: U.S. Philips Corporation
    Inventors: Dirk M. Knotter, Jacob Wijdenes
  • Patent number: 5619794
    Abstract: A complex structure molding process for molding a complex structure including a plastic base and a plurality of terminal pins, comprising the steps of molding the plastic base to have the terminal pins partly embedded in the plastic base, storing a continuous metal material having a rim portion and a plurality of terminal pins perpendicularly extending from the rim portion, cutting the continuous metal material in a first direction parallel to the direction in which the terminal pins extend from the rim portion to form a segmented metal material, and setting the segmented metal material in the molding means in the state having the segmented metal material assume their predetermined attitudes. The continuous metal material is fed in a second direction perpendicular to the first direction to cut the continuous metal material and to set the segmented metal material for molding the plastic base to have the terminal pins partly embedded in the plastic base.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: April 15, 1997
    Assignee: Teijin Seiki Co., Ltd.
    Inventor: Keizo Hokazono
  • Patent number: 5615475
    Abstract: This invention is for an integrated circuit package which includes two integrated circuit die connected to a common substantially planar lead frame, wherein bond pads on each die face the common lead frame.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: April 1, 1997
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5615571
    Abstract: A device for cambering conductive fingers, including a cambering plate (14) having a mold (16) which corresponds to the camber to be produced, a device for positioning (8) the intermediate substrate relative to the cambering plate (14), a cambering tool (22) disposed opposite the mold (16) for acting on a conductive finger (4), and a control device (24, 7) for ensuring or controlling the relative displacement of the cambering plate and the cambering tool in a first direction perpendicular to the plane containing the conductive fingers (4) and in a second direction parallel to the longitudinal direction of the conductive fingers (4).
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: April 1, 1997
    Assignee: Bull, S.A.
    Inventor: Patrick Courant
  • Patent number: 5613295
    Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Nagano
  • Patent number: 5610436
    Abstract: A surface mount electronic device, attachable to a circuit board, comprises an insulating substrate having a top surface and a bottom surface; a plurality of metallized terminal pads on the bottom surface; and a plurality of leads, each attached to one of the terminal pads by a solder column. Each of the leads comprises a first substantially horizontal lead portion attached to one of the terminal pads by the solder column. A plurality of upturned prongs on the first substantially horizontal lead portion forms a pronged area configured to hold the solder column. A second substantially horizontal lead portion terminates in a free end for attachment to the circuit board. An upwardly curved intermediate lead portion connects the first and second substantially horizontal portions and underlies the bottom surface of the substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 11, 1997
    Assignee: Bourns, Inc.
    Inventors: Roger Sponaugle, Robert R. Rainey
  • Patent number: 5592734
    Abstract: A TAB carrier for film-mounted integrated circuits comprises a body member having a rectangular cavity for receiving a TAB segment of a flexible film strip and a retainer member shaped and sized to fit conformably within the cavity, each integrally molded of a resilient polymeric material. A fully automated TAB framer includes a pair of vertically-oriented pneumatic rams having vacuum operated pick up heads on the lower ends thereof. A cutting assembly cuts TAB segments from the film strip. The rams are laterally shiftable between two positions for picking up TAB segments, placing a segment in a carrier body, picking up a retainer member and inserting the retainer member into the carrier body thereby forming a framed TAB segment.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: January 14, 1997
    Assignee: Byers Industries, Inc.
    Inventors: Jon C. Houghton, Chester H. Petry, Jr.
  • Patent number: 5592730
    Abstract: A Z-axis backing layer for an acoustic transducer is provided, which comprises a matrix of electrical conductors disposed in parallel and potted within an electrically insulating acoustic backing material. The acoustic transducers are disposed on a first end of the backing layer, with each individual transducer element connecting electrically to a respective one of the conductors. At the other end of the backing layer, the conductors connect electrically to a corresponding circuit element. The backing layer is fabricated from a plurality of leadframes each having an outer frame member and a plurality of conductors extending in parallel across the leadframes terminating at the frame members at opposite ends thereof. The plurality of leadframes are stacked such that respective conductors of adjacent ones of the leadframes are disposed in parallel with a space provided between the respective conductors equivalent to a width of one of the leadframes.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: January 14, 1997
    Assignee: Hewlett-Packard Company
    Inventors: Michael Greenstein, Henry Yoshida
  • Patent number: 5586914
    Abstract: An electrical connector which provides compensation for crosstalk includes a number of conductors positioned at least partially within an internal cavity defined by a housing. The elongate conductors are generally substantially parallel and laterally spaced and include a resilient contact portion at a first end and an insulation displacement contact portion at a second end. The elongate conductors include a pair conductors, at least a portion of which are positioned in an overlapping, vertically spaced relationship. The portions of the pair of conductors which overlap are generally wider than the substantially parallel, laterally spaced portions of the conductors so as to thereby define respective compensating segments. The length of the compensating segments as well as the width of the portion of the compensating segments which overlap can be selected to establish capacitive coupling between the compensating segments so as to thereby compensate for crosstalk between the conductors.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: December 24, 1996
    Assignee: The Whitaker Corporation
    Inventors: George H. Foster, Jr., deceased, Donald L. Metzger
  • Patent number: 5586389
    Abstract: In order to provide an electronic device that has high package density and can facilitate electrical connection between a plurality of circuit boards therein, the electronic device comprises a frame having two mutually opposed openings through major planes, a plurality of circuit boards disposed in the frame parallel to the major plane, and mounted selected electronic circuits thereon respectively, and first and second closure lids for closing the openings in the major plane; the first closure lid contacting with the surface of at least one of the circuit boards, on which no electronic circuit is mounted. Also, on the inner wall of the frame; appropriate stepped portions are formed for supporting the closure lid member, the supporting plate, the circuit board and so forth, Furthermore, in the stepped portion, a portion to accommodate an excess amount of an adhesive is provided.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: December 24, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yasunobu Hirao, Makoto Koyama, Yuji Motoyama
  • Patent number: 5577319
    Abstract: A method of encapsulating a crystal oscillator (100). First, a dielectric material is assembled or connected to the bottom side of a lead frame (102). Second, oscillator components including a piezoelectric element, capacitors and an integrated circuit are attached on the lead frame (104). Third, an epoxy dam is dispensed around the periphery of the oscillator component locations (106). Fourth, a encapsulant is dispensed within the epoxy dam to encapsulate the oscillator components (108). Fifth, the epoxy dam and encapsulant are cured (110). Thereafter, the oscillator is singulated from the lead frame and the leads are formed for mounting (112).
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: November 26, 1996
    Assignee: Motorola, Inc.
    Inventor: Thomas A. Knecht
  • Patent number: 5557842
    Abstract: A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: September 24, 1996
    Assignee: Motorola, Inc.
    Inventor: Keith W. Bailey
  • Patent number: 5548890
    Abstract: In a method for forming a lead frame (1) from a metallic plate, a metallic plate (11) is first etched to form outer leads (4) and outer portions (3b) of inner leads of the lead frame (1). Inner portions (3a) of the inner leads (3) are then laser-cut under the condition that a joint portion (7) is left so as to interconnect the inner leads (3) at their distal ends. Mechanical surface treatment and chemical surface treatment are then carried out to remove dross (10), spatters (9) and oxide films deposited during the laser cutting. Inner areas of the inner leads (3) connected to respective terminals of a semiconductor chip are then plated with gold to form plated terminal portions (3A). Subsequently, the region of the lead frame other than the outer leads (4) is coated with a protective film for solder plating and the outer leads (4) are plated with solder.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: August 27, 1996
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Nobuhiko Tada, Naoki Miyanagi, Yoshiaki Shimomura, Shigeyuki Sakurai, Shinya Okumura, Yoshinari Nagano
  • Patent number: 5541447
    Abstract: A lead frame for use in producing of a semiconductor integrated circuit comprises a lead frame member, a plurality of leads, a tie bar, a plurality of auxiliary leads, a support-stay portion and a connecting portion. A semiconductor element such as an IC chip is mounted on a semiconductor-element-mounting portion of the lead frame member, while the leads are arranged along and extending from a side portion of the lead frame member. The tie bar is connected among the leads and auxiliary leads at their tip-edge portions. Herein, the auxiliary leads are electrically unconnected from the semiconductor element. Further, the support-stay portion is provided at a corner portion of the lead frame member. The connecting portion is provided between a base-edge portion of the support-stay portion and a base portion of the auxiliary lead. A location of the connecting portion is selected in such a manner than the connecting portion will be unaffected by bending of the leads.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: July 30, 1996
    Assignee: Yamaha Corporation
    Inventors: Yoshihisa Maejima, Seiya Nishimura, Masayoshi Takabayashi, Tokuyoshi Ohta
  • Patent number: 5537737
    Abstract: The optical module manufacturing apparatus according to the present invention includes a pallet 205 on which the optically operating members and the lead frame are set to be kept in a positional relationship; a wire connection means 202 and 213 for connecting the wires to the members, the frame and the electronic circuits on the frame as the members and the frame remain kept in the positional relationship; conveyors 207, 208 and 209 for conveying the members and the frame to dies 204 after the connection as the members and the frame remain kept in the relationship; and a die-setting means 203 for setting the members and the frame in the dies through the suction of the members and the frame away from the pallet onto the setting means after the conveyance as the members and the frame remain kept in the relationship.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: July 23, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsutoshi Kamakura, Akihiko Shioda, Yoshihide Enami, Hisao Go
  • Patent number: 5535509
    Abstract: A semiconductor device including a lead on chip structure employs two frames. One of the frames includes a die pad and an outer frame portion and the other frame includes a plurality of leads and an outer lead portion. After a semiconductor chip is die bonded to the die pad, the two frames are connected to each other with the leads extending across the semiconductor chip. Slits within the second frame provide access to parts of the outer frame of the first frame and the first frame is severed at those slits. The severed portions of the first frame are removed after which the leads of the second frame are connected by wire bonding to the semiconductor chip. Finally, the semiconductor chip, the remaining part of the first frame, and the second frame are encapsulated in a resin with leads extending from the resin. The remaining parts of the outer frame of the second frame are removed by cutting and the exposed leads outside the resin are formed into a desired shape.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: July 16, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Naoto Ueda, Yoshirou Nishinaka, Shunichi Abe, Hideyuki Ichiyama
  • Patent number: 5513792
    Abstract: An outer-lead bonding apparatus according to the present invention comprises:(1) a punching die to stamp out chips from a film carrier tape,(2) a mounter to mount TAB chips on a substrate,(3) a first cover to enclose the mounter,(4) a second cover to enclose the punching die,(5) a pressure regulator to supply higher air pressure than outer air into inside space of the first cover, and(6) a exhaust to exhaust air from inside space of the second covering means. The outer-lead bonding apparatus of this invention keeps the environment around the mounter clean with air supplied from a pressure regulator and also by exhausting the air polluted by the punching operation through the exhaust. Neither products nor outer environment is thus contaminated.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: May 7, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuto Onitsuka