Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Patent number: 6400569
    Abstract: A lead frame apparatus that includes: an arrangement for dissipating heat generated at the lead frame, wherein the heat dissipating arrangement is uninterruptedly connected to the lead frame. Also contemplated herein are a lead frame heat dissipating apparatus having at least one element for dissipating heat generated at a lead frame and having an arrangement for directly and uninterruptedly connecting with a lead frame, as well as lead frame apparatus comprising an arrangement for directly and uninterruptedly accommodating at least one external element for dissipating heat generated at the lead frame. A method of making a lead frame apparatus involves the provision of a lead frame, the provision of an arrangement for dissipating heat generated at the lead frame, and the uninterrupted connection of the heat dissipating arrangement to the lead frame.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: June 4, 2002
    Assignee: Composidie, Inc.
    Inventor: Carl Auer
  • Patent number: 6374486
    Abstract: A method for manufacturing a smart card in which a through-passage is produced in a central sheet. At least one face of the central sheet is provided with at least one metal coil having connection parts, and an electronic chip having electrical connection pads is inserted into the passage. At least some of the electrical connection pads of the chip are soldered to the connection parts of the coil, and the faces of the central sheet are provided with external covering sheets to form a stack of sheets. In a preferred method, the stack of sheets is hot pressed or laminated such that the material of the sheets is flowed and fills the space around the chip. A smart card is also provided. The smart card includes at least one metal coil having at least two connection parts, an electronic chip connected to the connection parts of the coil, a central sheet having a through-passage, and external covering sheets that grip the central sheet. The electronic chip is placed in the passage in the central sheet.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: April 23, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Rémi Brechignac
  • Patent number: 6370785
    Abstract: The present invention relates to a leadframe stip counting gauge and comprises a gauge member having an engagement portion adapted for association with a leadframe carrier having leadframes contained therein. The leadframe strip counting gauge further comprises leadframe count indicia associated with the gauge member, wherein the indicia are spatially distributed with respect to the gauge member and are adapted to provide a count representing a number of leadframes residing in the leadframe carrier. The present invention also relates to a method of counting leadframes residing in a leadframe carrier, and comprises positioning a leadframe counting member near a leadframe carrier containing leadframes therein. The method further comprises determining a number of leadframes in the leadframe carrier using leadframe count indicia associated with the leadframe counting member.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Adisorn Kanjanavikat
  • Patent number: 6370767
    Abstract: A method and apparatus for dissipating heat from an electrical component. The method includes providing a planar element including a first electrically and thermally conductive region and a second electrically and thermally conductive region, such that the first and second regions define a spacing therebetween, and wherein the planar element includes at least one mechanically stabilizing tie connected between the first and second regions across the spacing, directly connecting a first terminal of an electrical component to the first region, directly connecting a second terminal of the electrical component to the second regions, such that the electrical component bridges the spacing, and removing the at least one mechanically stabilizing tie from between the first and second regions.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: April 16, 2002
    Assignee: Artesyn Technologies, Inc.
    Inventors: Terry B. Solberg, Daryl E. Weispfennig, Michael K. Hennies
  • Publication number: 20020038714
    Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 4, 2002
    Inventor: Thomas P. Glenn
  • Patent number: 6357275
    Abstract: The present invention is directed toward an apparatus and method for providing mechanically pre-formed conductive leads. In one embodiment of the invention, an apparatus includes a forming chuck engageable with a first surface of a conductive sheet, and a receiving chuck engageable with a second surface of the conductive sheet opposite from the forming chuck. The forming chuck has a raised forming portion alignable with one or more lead members formed in the conductive sheet, and the receiving chuck has a receiving portion alignable with the forming portion and shaped to closely conform to at least part of the forming portion. The conductive sheet is compressed between the forming chuck and the receiving chuck to mechanically pre-form the one or more lead members into one or more pre-formed conductive leads. In one embodiment, the raised forming portion includes a ridge having a polygonal cross-sectional shape and the receiving portion comprises a channel.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: March 19, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Ronald W. Ellis, Tracy Reynolds, Michael Bettinger
  • Patent number: 6353998
    Abstract: A fixture for aligning the leads of SMT components with the corresponding pads of the printed circuit board, which is to receive such components, before soldering the leads to the pads. The fixture includes clamps for applying forces directly to the leads of the SMT components, alone or in conjunction with the clamping forces which are traditionally applied to the body of the component, the applied forces sufficient to seat the leads on the corresponding pads. In a preferred embodiment, the forces are applied by providing the fixture with a series of rocker-type clamps, each having an edge for engaging the several leads associated with a particular SMT component to be joined to the printed circuit board. The clamp is preferably constructed of a non-wettable material so that the edge of the clamp will not be wet by the molten solder during the soldering procedure, and the edge is preferably thin so that the clamping surface in contact with a particular lead is minimized.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: March 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Wilton L. Cox, Terry R. Richards, Robert W. Wagner
  • Patent number: 6341549
    Abstract: A trimming apparatus according to the present invention has a trim punch that provides a route for continuous air flow to prevent trimmed gate scraps from clogging the apparatus. The trim punch can have a groove or a through hole for providing the continuous air flow from outside into an outlet, through which trimmed gate scraps are discharged. This continuous air flow prevents the trimmed gate scraps from remaining inside the outlet and adhering to the trim punch. Therefore, clogging of the trimmed gate scraps in the apparatus is prevented.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: January 29, 2002
    Assignee: Samsung Electronic Co., Ltd.
    Inventor: Sang Ki Kim
  • Patent number: 6324756
    Abstract: A system and method for providing plastic ball grid array (“PBGA”) packages is disclosed. In one aspect, the method and system provide a plurality of PBGA packages. Each of the plurality of PBGA packages including a semiconductor die and a portion of a substrate. The semiconductor die is electrically coupled to the portion of the substrate. The portion of the substrate has an edge. In this aspect, the method and system include forming the plurality of PBGA packages on the substrate and separating the portion of the substrate for each of the plurality of PBGA packages. The portion of the substrate for one of the plurality of PBGA packages is separated from the portion of the substrate for another of the plurality of PBGA packages by a gap. In a preferred embodiment, the gap is created by punching the substrate. The method and system further include filling the gap with a moisture sealant and cutting the moisture sealant to separate the plurality of PBGA packages.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: December 4, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Xia Li, Ranji Gannamani
  • Patent number: 6314639
    Abstract: A dense semiconductor flip-chip device is provided with a heat sink/spreading/dissipating member which is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Dice are bonded to the paddles by e.g. conventional die attach methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: November 13, 2001
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6305074
    Abstract: The process for mounting an integrated circuit (11) on a support (10) comprising a structure (13) of conductors (14) comprises connecting the conductors to respective terminals (12) of the integrated circuit without interposing a part of the support for insulating the conductors of the integrated circuit as in the standard TAB technology. The connection can be made directly by thermocompression or ultrasound, or indirectly through ball bonds. It is only after the connection that the insulation between the conductors and the integrated circuit is applied. The insulating substrate of the TAB support (10) can be attached to the conductors outside the integrated circuit, before or after the connection of the conductors.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: October 23, 2001
    Assignee: Bull, S.A.
    Inventor: Patrick Courant
  • Patent number: 6307253
    Abstract: A lead frame (1) is provided which includes elongated side frames (2, 3) extending in parallel to each other, and section bars (4) connecting the side frames in a manner allowing the side frames to be shifted longitudinally. The side frame (2) is integrally formed with first lead terminals (6), whereas the side frame (3) is integrally formed with second lead terminals (7). Extremities of the first and the second lead terminals are overlapped after the side frames (2, 3) are shifted. At least either one of the first lead terminal (6) and the second lead terminal (7) is formed with a weaker portion having reduced bending strength. The extremities of the first and the second lead terminals is bonded to a semiconductor element (T) after the side frames (2, 3) are shifted. Thereafter, restoring force due to the spring-back action of the section bars (4) acts on the lead terminals (6, 7) and the semiconductor element (T). However, the restoring force is used to deform the weaker portion.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: October 23, 2001
    Assignee: Rohm Co., Ltd.
    Inventors: Masao Yamamoto, Hiroshi Imai
  • Patent number: 6295726
    Abstract: A method for manufacturing a SIL hybrid circuit is presented. A lead frame is provided which includes side bands and clip members between the side bands configured to connectively receive a hybrid circuit. The lead frame further includes foot members between the side bands configured to be surface-mounted to a base substrate. Each foot member has tabs at the ends thereof and support members extending straight from the tabs to connect the tabs to the side bands. Corresponding contact areas of the hybrid circuit are attached to the clip members. At least one foot member and associated support members are selected to remain in the lead frame to support the SIL hybrid circuit during positioning on the base substrate and surface mounting thereto. Excess parts are removed from the lead frame based on the selecting. As such, SIL hybrid circuits may be efficiently used to achieve high packaging densities.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: October 2, 2001
    Assignee: Nokia Networks Oy
    Inventor: Hannu M{umlaut over (aa)}ttä
  • Patent number: 6294411
    Abstract: A semiconductor component includes, before molding, a lead frame, a semiconductor chip mounted on the lead frame, and bonding wires for connecting pads of the semiconductor chip to inner leads. This component is inserted between a lower mold and an upper mold having a mold cavity moving unit, and these molds are clamped. Thereafter, an inner space formed by these clamped molds is filled with resin to form a package. Particularly, before resin filling, the mold cavity moving unit is moved downward and presses upper portions of the bonding wires to regulate the wire height. In this state, the inner space of these molds is filled with the resin. Before the filling resin is cured, the mold cavity moving unit is returned to the upper surface position of the package to form a nonfilling space in these molds. Thereafter, the nonfilling space is filled with the resin.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: September 25, 2001
    Assignee: Nippon Steel Semiconductor Corporation
    Inventor: Akihito Nishibayashi
  • Patent number: 6289580
    Abstract: The present invention relates to a method and apparatus for manufacturing a surface mount power supply device having effective thermal management. The surface mount power supply device comprises a printed circuit board mounted to a thermal plastic lead frame attach by means of vertically-extending aluminum pins embedded in the lead frame attach. A cylindrical member is centered within the lead frame attach by means of inwardly protruding arms transversely connected to the lead frame attach to allow for a pick-and-place operation.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: September 18, 2001
    Assignee: Lambda Electronics, Inc.
    Inventor: Peter T. Brune
  • Patent number: 6279226
    Abstract: A method and apparatus for stabilizing the form of a letter S of an inner lead after bonding in a method of manufacturing &mgr;BGAoIC in which a chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead is disclosed. The inner lead is bonded to the electrode pad when the chip is supplied in a fixed position for a bonding tool using a sprocket hole of the tape carrier. Next, the respective positions of the inner lead and the electrode pad are recognized using a feature lead and an electrode pad. Afterward, the center line of the inner lead is recognized, the inner lead is touched to the chip by the bonding tool and after the inner lead is pushed in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: August 28, 2001
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
  • Patent number: 6277225
    Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: August 21, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Timothy J. Allen, Jerry M. Brooks
  • Patent number: 6272734
    Abstract: The relay is formed from two half-shells which are formed by extrusion coating the functional elements with plastic. A first half-shell is formed by extrusion coating a coil with a U-shaped core, while a second half-shell is formed by extrusion coating a spring support and at least one fixed contact element. A contact spring having a flat armature is attached to the spring support. The relay is adjusted and at the same time sealed by the process of joining the two half-shells.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: August 14, 2001
    Assignee: Tyco Electronics Logistics AG
    Inventor: Josef Kern
  • Patent number: 6272744
    Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: August 14, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gary W. Grube, Igor Y. Khandros, Gaètan Mathiew
  • Patent number: 6263563
    Abstract: The invention relates to electronic technique, particularly to technology of fabricating and checking semiconductor integrated circuits and semiconductor structures. The method of manufacturing and checking electronic components consists in that a plurality of dice are disposed in a press-form, orienting to the dice bonding pads and base elements of the press-form, all non-protected surfaces of the dice except the bonding pads are insulated. Specificity of the method consists in that disposing in the press-form dice are fixed one to another forming a group carrier, providing a disposal of the dice facial (main) surfaces on common plane with one of the group carrier's surfaces, at that all the conductors, necessary for burn-in and checking, and also external connector are deposited on this plane simultaneously. Variants of the method consist in that a group metal frame is disposed simultaneously with the dice.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: July 24, 2001
    Assignee: R-Amtech International, Inc.
    Inventor: Yuriy Dmitrievich Sasov
  • Patent number: 6256873
    Abstract: Smart cards employing ITA-based circuits can be made by associating a splitter edge material with the ITA-based circuit in order to direct an incoming stream of thermosetting polymeric above and below the ITA-based circuit.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: July 10, 2001
    Assignee: CardXX, Inc.
    Inventor: Harry J. Tiffany, III
  • Publication number: 20010005042
    Abstract: The present invention provides a method and apparatus for fabricating densely stacked ball-grid-array packages into a three-dimensional multi-package array. Integrated circuit packages are stacked on one another to form a module. Lead carriers provide an external point of electrical connection to buried package leads. Lead carriers are formed with apertures that partially surround each lead and electrically and thermally couple conductive elements or traces in the lead carrier to each package lead. Optionally thin layers of thermally conductive adhesive located between the lead carrier and adjacent packages facilitates the transfer of heat between packages and to the lead carrier. Lead carriers may be formed of custom flexible circuits having multiple layers of conductive material separated by a substrate to provide accurate impedance control and providing high density signal trace routing and ball-grid array connection to a printed wiring board.
    Type: Application
    Filed: January 16, 2001
    Publication date: June 28, 2001
    Inventor: Carmen D. Burns
  • Patent number: 6240632
    Abstract: According a method of manufacturing a lead frame of the present invention, a plurality of leads each having an inner lead portion and an outer lead portion are formed on a metal base having on its surface a nickel layer by copper plating. An insulative holding film for holding each of the leads is formed. A projecting electrode is formed on the outer lead portion. Respective leads are separated by selectively removing the metal base by etching.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: June 5, 2001
    Assignee: Sony Corporation
    Inventors: Makoto Ito, Kenji Ohsawa
  • Patent number: 6239980
    Abstract: A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Submodule connection pads are provided on upper surfaces of the submodules. As a second hierarchial assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the submodule connection pads.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: May 29, 2001
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Wolfgang Daum, Ronald Frank Kolc, Donald William Kuk, Rob Ert John Wojnarowski
  • Patent number: 6233818
    Abstract: Process and device for the contacting of a wire conductor (113) in the course of the manufacture of a transponder unit arranged on a substrate (111) and comprising a wire coil (112) and a chip unit (115), wherein in a first phase the wire conductor (113) is guided away via the terminal area (118, 119) or a region accepting the terminal area and is fixed on the substrate (111) relative to the terminal area (118, 119) or the region assigned to the terminal area, and in a second phase the connection of the wire conductor (113) to the terminal area (118,119) is effected by means of a connecting instrument (125).
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: May 22, 2001
    Inventors: David Finn, Manfred Rietzler
  • Patent number: 6230399
    Abstract: A TAB device (10) is coupled to a circuit board (12). The TAB device (10) includes a semiconductor die (11) having leads (18) extending therefrom. A material layer (30), typically a polyimide layer, covers the inward portion of the leads (18) to maintain leading position during attachment of the TAB device (10) to the circuit board (12). Prior to attachment, a backside encapsulation region (40) is applied to the backside of the TAB device (10), sealing the backside of the leads (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (30), to prevent excessive warpage.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: May 15, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Abhay Maheshwari, Sunil Thomas
  • Patent number: 6221748
    Abstract: The present invention is directed toward an apparatus and method for providing mechanically pre-formed conductive leads. In one embodiment of the invention, an apparatus includes a forming chuck engageable with a first surface of a conductive sheet, and a receiving chuck engageable with a second surface of the conductive sheet opposite from the forming chuck. The forming chuck has a raised forming portion alignable with one or more lead members formed in the conductive sheet, and the receiving chuck has a receiving portion alignable with the forming portion and shaped to closely conform to at least part of the forming portion. The conductive sheet is compressed between the forming chuck and the receiving chuck to mechanically pre-form the one or more lead members into one or more pre-formed conductive leads. In one embodiment, the raised forming portion includes a ridge having a polygonal cross-sectional shape and the receiving portion comprises a channel.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: April 24, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Ronald W. Ellis, Tracy Reynolds, Michael Bettinger
  • Patent number: 6219627
    Abstract: A method of manufacturing integrated circuits uses an architecture having multiple processors and multiple memories, such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at least a first memory. The second group has at least a second processor and at least a second memory. Regardless of where the architecture is sliced, the integrated circuits have a majority of the same address and data pin-outs.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: April 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Walt C. Bonneau, Karl Guttag, Robert Gove
  • Patent number: 6218628
    Abstract: A method for the manufacture of printed circuit boards, foil circuit boards and semifinished products for printed and foil circuit boards formed from preliminary products with electrically conductive coatings (7, 8) structurable to conductor patterns and structurable substrates (4), for the formation of connectors (V), contours (K) and conductor patterns (L), the connectors (V), contours (K) and conductor patterns (L) being structured simultaneously or in the same method steps from the preliminary products, and the connectors (V) and contours (K) are part of the structured preliminary product substrate, the connectors (V) being brought for electrical or mechanical connection into a position in which they are connectable and the finished conductor patterns (L) can be separated at contours (K).
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: April 17, 2001
    Assignee: Dyconex Patente AG
    Inventors: Walter Schmidt, Marco Martinelli
  • Patent number: 6202299
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 6198044
    Abstract: A method of manufacturing a microcircuit board with a mechanical cut-out piece between the microcircuit and the board to limit stresses transmitted to the microcircuit. A blank of a network of conductors is created and the microcircuit is fixed in a container formed by shaping the blank, the microcircuit keeping the different parts of the network in position relative to each other and the module thus formed is installed in a cavity in the board by fixing the external connection areas onto the upper surface of the cavity.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: March 6, 2001
    Assignee: De la rue Cartes et Systemes
    Inventors: Jacques Venambre, Francois Bouchez
  • Patent number: 6196042
    Abstract: A tool having a coining projection is operative for forming a frangible portion in a lead of a microelectronic connection component by application of a compressive force. The coining projection is supported on a pedestal formed from a tool body. In an alternative embodiment, the pedestal is formed on a backing plate for use in circuits up construction. The pedestal is sized and shaped so as to be received within a gap formed in a support layer for the leads. By application of the compressive force, the coining projection will penetrate the lead within the region of the gap to form the frangible portion.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: March 6, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Joseph Fjelstad, Belgacem Haba
  • Patent number: 6183589
    Abstract: A method for manufacturing lead-on-chip (LOC) semiconductor packages includes steps of preparing a lead frame having inner leads and outer leads, and applying a liquid adhesive having a certain viscosity to the bottom surfaces of the inner leads. The method also includes positioning a semiconductor chip under the lead frame, to expose electrode pads through the space defined between opposing rows of inner leads. The inner leads are then attached to the active surface of the semiconductor chip by means of the liquid adhesive. The adhesive applying step may be carried out using a tool having discharge projections through which liquid adhesive is discharged from a reservoir. The liquid adhesive under the lead frame may be cured and then turned into a solid adhesive layer by thermocompression. The liquid adhesive is a thermosetting resin or a thermoplastic resin.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: February 6, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin Kim, Byung Man Kim, Il Heung Choi, Jeong Ho Bang
  • Patent number: 6170151
    Abstract: An assembly for processing a flexible tape comprises a carrier frame having a slot and a cut-out region contiguous with one end of the slot for selectively transferring the flexible tape from the top surface of the carrier frame to the bottom surface of the carrier frame. An apparatus for processing the flexible tape is also disclosed and includes the carrier frame, a base having an aperture and a platform sized to fit within the aperture of the base. The base is pivotable around one end of the platform.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: January 9, 2001
    Assignee: Tessera, Inc.
    Inventors: Joseph Link, Kurt Raab
  • Patent number: 6163956
    Abstract: A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member which is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Dice are bonded to the paddles by e.g. conventional die attach methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: December 26, 2000
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6148509
    Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 21, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Schoenfeld, Jerry M. Brooks
  • Patent number: 6149741
    Abstract: A method for forming supports for use in electronic components. A plate of copper-based alloy including from 0.1 to 1.0% by weight nickel, and from 0.005 to 0.1% by weight of phosphorus is melted and cast. The alloy includes fine precipitates of nickel phosphides throughout the copper matrix. The plate is subjected to a series of deformation operations including, rolling and intermediate annealing at a temperature in the range of 400.degree. to 600.degree. C., with the annealing temperature being maintained for two to four hours, thereby maximizing the production of fine precipitates of nickel phosphides within the alloy. After alloy formation, the plate is coated with a layer of nickel, cut into a desired shape, and secured to an electronic component.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: November 21, 2000
    Assignee: Establissements Griset
    Inventor: Gerard Durand-Texte
  • Patent number: 6141872
    Abstract: A method of producing products wherein semi-finished products are supported between a pair of elongate, parallel carriers. Each semi-finished product is shaped by pressing the product into a finished form. Also, each semi-finished product is connected to at least one of the carriers by a deformable element. Deformation of the deformable element allows the semi-finished product to approach or move away from that carrier. Thus, when the semi-finished product is shaped by pressing, deformation of the deformable element allows the semi-finished product to move relative to that carrier so that unwanted tensions are relieved. Accordingly, the semi-finished product does not twist undesirably.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: November 7, 2000
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Hitoshi Takanashi
  • Patent number: 6141599
    Abstract: A method for setting data for conveying a lead frame having a plurality of islands thereon to and from a bonding position of a bonding apparatus including feeding a lead frame so that the first island on the lead frame is positioned at the bonding position and the cross-hairs of a television monitor are aligned with an arbitrary position on the first island, storing the amount of feeding of the lead frame in a data memory, feeding the lead frame next so that the last island on the lead frame is positioned at the bonding position, aligning an arbitrary position on the last island which corresponds to the arbitrary position on the first island with the cross-hairs of the television camera and storing the amount of feeding of the lead frame in the data memory.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: October 31, 2000
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Toru Mochida, Yoshimitsu Terakado, Masayuki Seguro
  • Patent number: 6131278
    Abstract: A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: October 17, 2000
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. MacQuarrie, Wayne R. Storr, James W. Wilson
  • Patent number: 6122822
    Abstract: A method for forming a plastic package of an electronic device that is substantially without void formation is disclosed. In the method, a lead finger which is to be encapsulated in a plastic package is first deformed into various configurations such that the mold flow pattern can be modified accordingly. For instance, the tip portion of the lead finger can be formed into a U-shaped or a V-shaped bend, can be tilted to a 45.degree. slope or can be formed with U-shaped or V-shaped notch in the lead finger such that plastic flow velocity may be increased where the flow channel has been enlarged. Numerous embodiments of the present invention novel method are available for achieving similarly desirable results.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: September 26, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Kuang-Ho Liao
  • Patent number: 6094812
    Abstract: A method of manufacturing semiconductor circuits or electronic packages is provided. The step of splitting up wide metal areas into metal stripes is included into the physical design step of such devices. This method does not increase the data complexity significantly and guarantees correctness of the design. Furthermore, the method allows to solve the dishing problem that is inherent to copper wiring technologies.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: August 1, 2000
    Assignee: International Business Machines
    Inventors: George English, Joachim Keinert, Oliver Rettig
  • Patent number: 6095404
    Abstract: A method for soldering electronic components capable of withstanding high temperature applications. A solder having a composition in the range between 83 and 87% lead, between 8.5 and 11.5% antimony, and the balance of tin provides superior results. The solder uniquely provides a sufficiently low melting point to enable mass flow without destruction of plastic package parts, and a sufficiently high melting point to achieve 200 degrees C. operation. Good mechanical strength is achieved while providing sufficient creep to permit differential expansion between components and a printed wiring board. A heavy solder layer is coated on a printed wiring board and is oxidized to generate a thin solderable layer. Manufacture of the circuit board can be performed with conventional techniques such as wave soldering, hand soldering, solder printing, solder dispensing, and solder pre-forms.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: August 1, 2000
    Assignee: Innova Electronics, Inc.
    Inventor: Charlie McAndrew
  • Patent number: 6085412
    Abstract: A card type memory device comprises a semiconductor chip having a nonvolatile semiconductor memory formed with external connection terminals and a metal frame comprising bed sections and external terminal electrode sections with a step section formed between the bed section and the external terminal electrode section, the bed sections of the metal frame being electrically connected to the external terminal electrode sections of the semiconductor chip. At least one surface and outer peripheral surface of the semiconductor chip are resin sealed such that at least electrode surfaces of the external terminal electrode sections of the metal frame are exposed substantially flush with a resin-sealed body surface. By doing so, a semiconductor package is formed. The semiconductor package is buried in a recess in a card type base board such that the electrode surfaces of the external terminal electrode sections of the metal frame in the semiconductor package is buried substantially flush with an external surface.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: July 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 6081997
    Abstract: A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: July 4, 2000
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Maniam Alagaratnam
  • Patent number: 6061895
    Abstract: A method for manufacturing an inexpensive rotation sensor having excellent performance, high workability, and high reliability is provided. In the method, the rotation sensor is manufactured by providing an insert conductor having a predetermined shape and insert-molding the insert conductor in a resin base such that at least a connector terminal and an conversion device terminal of the insert conductor remains exposed from the resin base. Also, a resin connector part is molded after the resin base is molded such that the resin connector part encircles the connector terminal.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: May 16, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Izuru Shinjo, Noriaki Hayashi, Naoki Hiraoka, Wataru Fukui, Yutaka Ohashi
  • Patent number: 6058602
    Abstract: A method for manufacturing a plastic encapsulated integrated circuit (IC) package has steps for placing a diamond substrate in a lower cavity of an encapsulation mold such that the diamond substrate in the finished package underlies the die attach pad and a portion of the leads in close proximity to each. Pins are provided in lower cavities of molds to support and/or position diamond substrates to lie close to both die attach pads and leads to facilitate efficient heat transfer from an operating IC, through the die attach pad, into and through the diamond substrate, and finally to the leads leading from the encapsulated package. Apparatus is disclosed for positioning and supporting diamond substrates, and combination heat slugs for the purpose are disclosed, having diamond substrates bonded to metal slugs.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: May 9, 2000
    Assignee: Integrated Packaging Assembly Corporation
    Inventor: Gerald K. Fehr
  • Patent number: 6049971
    Abstract: A method for fabricating a lead frame that includes a platform attached thereto for mounting a chip. A base frame is provided for mounting chips of various sizes. The base frame includes connection leads extending toward a central portion, which is substantially of the size of the smallest chip to mount. Connection leads are cut-out about the central portion to form an opening corresponding to the size of the chip to be mounted. A platform is soldered to at least two support leads to form the lead frame.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: April 18, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Luc Petit
  • Patent number: 6049975
    Abstract: An improved multichip semiconductor module compatible with existing SIMM memory sockets comprising a molded module frame and a composite semiconductor substrate subassembly received in a cavity in said frame. The composite semiconductor substrate subassembly or subassembly(s) comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the subassembly(s) includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: April 18, 2000
    Inventor: James E. Clayton
  • Patent number: RE37413
    Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: October 16, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gi Bon Cha