Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Patent number: 5501003
    Abstract: The method is used to assemble an electronic package of the type having a plurality of external conductive output pads for subsequent surface mounting of the electronic package. The method includes forming a nonconductive frame within the opening of a conductive lead frame such that the nonconductive frame is attached to and encapsulates a portion of each of the leads of the conductive lead frame. An electronic package, which includes two printed circuit boards, having components and conductive output areas on respective sides thereof, is positioned within the non-conductive frame from opposite sides and the conductive output areas of the boards attached to respective parts of different ones of the leads of the conductive lead frame. The electronic package is then encapsulated, leaving an air gap between the boards which cushions and isolates the internal solder joints from subsequent stress by allowing the boards to flex. The leads of the conductive lead frame are then separated from the frame.
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: March 26, 1996
    Assignee: Bel Fuse Inc.
    Inventor: Elliot Bernstein
  • Patent number: 5501004
    Abstract: An outer lead bonding apparatus and method bonds an outer lead of a tape carrier package to an electrode formed on a display panel. During the observation stage when positional deviations between the outer lead and electrode are detected and corrected, a pressing member presses on the outer lead to remove any warp or bend in the outer lead. The electrode includes anisotropic conductive tape which is inherently adhesive. To prevent unwanted movement of the tape carrier package during the observation and positioning process by premature sticking of the outer lead to the tape on the electrode, the tape carrier package is sandwiched firmly in place.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: March 26, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuto Onitsuka
  • Patent number: 5496435
    Abstract: The invention is to an apparatus and method for applying a plastic material to a lead frame for stabilizing the leads and retaining them in a common plane.
    Type: Grant
    Filed: July 13, 1994
    Date of Patent: March 5, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 5484097
    Abstract: Two phase bridge rectifiers are fabricated starting with three lead flames and bonding a first pair of semiconductor chips on mounting pads of a first of the frames and a second pair of semiconductor chips on mounting pads of a second of the frames. The frames are then disposed one on top of the other with upper surfaces of the first pair of chips contacting under surfaces of the mounting pads of the second frame and with upper surfaces of the second pair of chips contacting under surfaces of a pair of mounting pads on the third frame. A mounting pad on the third (upper) frame includes an extension thereof extending downwardly and bonded to a terminal formed in the second (middle) frame, and a mounting pad on the first (lower) frame includes an extension thereof extending upwardly and bonded to another terminal of the second frame.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: January 16, 1996
    Assignee: General Instrument Corp.
    Inventor: William Heuvel
  • Patent number: 5483740
    Abstract: A homogeneous thermoplastic semi-conductor chip carrier cavity package (HC package) which utilizes the same thermoplastic for various integral attachments to the HC package, such as, a molded lid and a circuit substrate. A chemical bonding or fusing of the integral attachments to the HC package provides increased protection from having moisture enter into the cavity of the HC package. The HC package eliminates problems which are associated with having different coefficients of thermal expansion for the HC package and its various integral attachments.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: January 16, 1996
    Assignee: AK Technology, Inc.
    Inventor: William H. Maslakow
  • Patent number: 5481798
    Abstract: A lead frame capable of easily connecting an inner lead to an electrode of a semiconductor element by way of a bump of the inner lead, and a method of manufacturing the lead frame capable of significantly easily forming the bump. A bump forming metal layer is formed on a metal base sheet on an area where each inner lead is to be formed. The inner lead is formed on the bump forming metal layer, and the bump forming metal layer is etched using the inner lead as a mask, thus forming a bump. After that, each outer lead is formed by selective etching of the metal base sheet from the rear surface side.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: January 9, 1996
    Assignee: Sony Corporation
    Inventors: Kenji Ohsawa, Makoto Ito, Mutsumi Nagano
  • Patent number: 5481899
    Abstract: The edges of a semiconductor die are moved away from the lead frame leads attached to the die by using a pressure differential across the semiconductor die.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: January 9, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Guy Harris, Duane Callaway, Rajesh Shah
  • Patent number: 5475918
    Abstract: Based on the fact that those portions of a lead frame which are liable to undergo deformation are the to-be-nonplated portions, the to-be-nonplated portions defined around the to-be-plated portions are covered with an adhesive tape or a resin film before the lead frame is subjected to a plating treatment, whereby to prevent deformation of the lead frame from the stage preceding to the surface treating step.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: December 19, 1995
    Assignee: Electroplating Engineers of Japan Ltd.
    Inventors: Tsuneo Kubota, Kazuhiro Taniguchi
  • Patent number: 5455394
    Abstract: A polymer lead frame is made from a flexible substrate with flexible conductive traces. The generally square lead frame has diagonal cutouts partially extending from the corners towards the center, as well as a central hole that lies within a footprint of the die. The die is bonded directly to the lead frame, preferably with anisotropic, electrically conductive adhesive. The die is placed with the lead frame in a fixture. A holding force is applied to secure the die and, if necessary, a curing force is applied during a cure cycle. The fixture allows transport of the assembly to a curing oven and allows application of the curing force. The die has contact pads characterized by a non-planar, non-bump-like surface with concavities having depths of at least about one-seventh the diameter of conductive particles in the anisotropic conductive adhesive.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: October 3, 1995
    Assignee: Poly-Flex Circuits, Inc.
    Inventors: David Durand, Chon M. Wong, Roger A. Iannetta, Jr.
  • Patent number: 5454160
    Abstract: An apparatus and method for stacking integrated circuit devices which combine flip-chip technology and soldering methods with laminated stack frames to provide a vertical stack array with minimal parasitic inductance. Each laminated stack frame has a central cavity and includes a plurality of vias extending through them. The vias have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump. Each laminated stack frame also includes a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a flip-chip integrated circuit chip, and a plurality of traces coupling each solder bump pad to a via. The bottom surfaces of the vias of a bottom laminated stack frame couple to contacts on a printed circuit board.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: October 3, 1995
    Assignee: NCR Corporation
    Inventor: Donald F. Nickel
  • Patent number: 5452511
    Abstract: A method for constructing a composite lead frame (10) wherein a plurality of lead segments (14) are separately constructed and then attached to a frame member (12). A plurality of the frame members (12) may optionally be produced as a lead frame strip (16). Each of the frame members (12) has an opposed pair of side rails (18) and a pair of cross members (20) for enclosing a lead area (22) wherein the lead segments (14) are affixed to the side rails (18) and the cross members (20) by a plurality of assembly tabs (40).
    Type: Grant
    Filed: November 4, 1993
    Date of Patent: September 26, 1995
    Inventor: Alexander H. C. Chang
  • Patent number: 5453913
    Abstract: A TAB tape having multiple metallic conductors arranged on the surface of a base film with substantially square device holes is formed with designed areas of stress refief formed by one or more slits and/or arrays of holes which extend outward from the corners or sides of the device holes, such that dimensional stability in the base film is improved in a direction parallel to inner leads when thermo-compression bonding is performed to connect the inner leads with IC chips resulting in improved connection reliability for connection between inner leads and IC chips.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: September 26, 1995
    Assignee: Minnesota Mining and Manufacturing Company
    Inventor: Tatsunori Koyanagi
  • Patent number: 5448825
    Abstract: An encapsulated electrically and thermally enhanced integrated circuit is disclosed. An integrated-circuit die is attached to a thermally conductive, electrically-insulated substrate. A lead frame having inwardly-extending bonding fingers has the bottom sides thereof attached to the top of the substrate. A contiguous layer of insulating material is bonded to the top sides of the bonding fingers, such that the layer of insulating material peripherally surrounds the integrated-circuit die. A conductive layer of material is then bonded to the top of the insulating layer. A second layer of insulating material followed by a second conductive layer may be bonded on top of the first conductive layer. Electrical connections are made from the integrated-circuit die to the conductive layers surrounding the die. The device is then encapsulated in a plastic material.
    Type: Grant
    Filed: March 25, 1994
    Date of Patent: September 12, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Sang S. Lee, William M. Loh
  • Patent number: 5448824
    Abstract: A molding apparatus and a molding method are provided which enable leads which project from an electronic housing, such as a housing configured to receive an accelerometer, to be formed during the molding operation in which the housing is formed. As a result, the leads used in the molding operation can be in an as-stamped, unformed condition, so as to facilitate handling and loading of the leads into the molding apparatus. In addition, because forming occurs during the molding operation, subsequent secondary forming operations are not required to achieve the desired configuration for the leads.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: September 12, 1995
    Assignee: Delco Electronics Corporation
    Inventors: Lloyd A. Groves, Phil O. Whelchel
  • Patent number: 5448826
    Abstract: A ceramic microelectronic package suitable for high-frequency microelectronic devices includes a base which is at least partially conductive attached either by seal glass or by solder to a ceramic RF substrate with a cavity formed at its center and a pattern of conductive paths for providing interconnection from the inside to the outside of the package. The base may be metal or ceramic with a metal layer deposited thereon. A ceramic seal ring with a second cavity corresponding to that of the RF substrate, but slightly larger, is attached to the RF substrate by seal glass which is patterned to generally match the dimensions of the seal ring. A ceramic lid is attached to the top of the seal ring by a non-conductive adhesive, such as a polymer adhesive or low temperature seal glass, to seal the package once the microelectronic device has been mounted inside.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: September 12, 1995
    Assignee: Stratedge Corporation
    Inventors: Martin Goetz, Joseph Babiarz
  • Patent number: 5446959
    Abstract: A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic packa
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: September 5, 1995
    Assignee: Electronics and Telecommunication Research Institute
    Inventors: Dong-Goo Kim, Min-Kyu Song, Seong-Su Park, Seung-Goo Kang, Hyung-Jin Yoon, Hyung-Moo Park
  • Patent number: 5444909
    Abstract: A heat sink incorporated into an electronic package. The package contains an integrated circuit enclosed by a dielectric housing. Coupled to the circuit is a lead frame which has a plurality of leads that extend from the outer edges of the housing. The heat sink has a bottom surface pressed against the lead frame and an opposite top surface that is exposed to the ambient. The heat sink also has a pair of oblique steps which engage the housing and insure that the sink does not become detached from the package.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: August 29, 1995
    Assignee: Intel Corporation
    Inventor: Behrooz Mehr
  • Patent number: 5438750
    Abstract: A method of manufacturing a chip card comprising a card base in which a cover section is secured, which cover section comprises a circuit support and at least one microcircuit arranged on a lower surface of the circuit support, which lower surface faces the interior of a recess and is spaced from the inner surface of the bottom of the recess, in which method an encapsulant is applied to said inner surface.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: August 8, 1995
    Assignee: U.S. Philips Corporation
    Inventor: Jacques Venambre
  • Patent number: 5437096
    Abstract: A fabrication method and leadframe construction in which the leadframe is formed by selectively removing portions of a multilayer clad strip to expose a selected pattern of a conductive metal to conform to the desired application of the leadframe. The clad strip may be formed of a base layer of copper alloy, a conducting layer of aluminum or aluminum alloy, and an upper layer of copper or a copper alloy. A layer of tin or lead-tin alloy may be plated onto the upper layer.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: August 1, 1995
    Assignee: Technical Materials, Inc.
    Inventor: Joseph P. Mennucci
  • Patent number: 5437095
    Abstract: A method of making an integrated circuit package is disclosed herein along with the package itself, which package is encapsulated by plastic that is caused to flow in a given direction during the package's formation. The package itself includes an IC chip having an army of chip output/input terminals, and means for supporting the chip including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip. In addition, the overall package includes bonding wires connecting the chip output/input terminals with respective ones of the leads such that each bonding wire extends in a direction that defines an acute angle of less than 45 degrees with the given flow direction of the plastic material used to encapsulate the IC chip, support means and bonding wires. In a preferred embodiment, at least a portion and most preferably substantially all of the bonding wires are substantially parallel with the given flow direction of the plastic material.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: August 1, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hem P. Takiar
  • Patent number: 5432127
    Abstract: A method for electrically connecting a lead frame (10) to an integrated circuit (40). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on to provide noise shielding for the integrated circuit (40). In addition, a power bus (12) and (14) is provided having false leads (24) and (26) to maintain equal capacitance.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: July 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Michael A. Lamson, Katherine G. Heinen
  • Patent number: 5428889
    Abstract: An outer lead of a metal lead frame is connected to an inner lead of a flexible lead-patterned substrate via a Au--Sn alloy layer. The Au--Sn alloy layer contains Au of 10 to 40 weight %. An inner lead of a metal lead frame is connected to a patterned lead of a flexible lead-patterned substrate by a heating tool. The inner lead is coated on bottom and side surfaces of its tip portion. The bottom surface faces the patterned lead.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: July 4, 1995
    Assignee: Hitachi Cable, Ltd.
    Inventors: Mamoru Mita, Tomio Murakami, Shoji Takagi, Hiroki Tanaka, Kenji Yamaguchi
  • Patent number: 5420757
    Abstract: A method of forming an environmentally sealed transponder type circuit wherein the circuit components are mounted on a lead type substrate frame, the components are encapsulated in a plastic housing in a plastic molding process so that the housing is supported in the frame only by a plurality of the leads, and then severing the leads at the periphery of the housing to provide a leadless package. The frame may be formed of a conductive material, an insulating material or as a printed circuit board. A novel printed circuit type lead frame whereby a coil of the circuit may be mechanically attached and directly secured to the frame is additionally disclosed.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: May 30, 1995
    Assignee: Indala Corporation
    Inventors: Noel H. Eberhardt, Jean-Marc Delbecq
  • Patent number: 5410804
    Abstract: Encapsulated integrated circuits (chips) (2, 3, 4, 5, 6) are manufactured by separating the encapsulated integrated circuits arranged on a lead frame (1), subsequently cutting away the lead-connecting strips (7) of the individual products, then bending the leads and finally cutting them to length. By subjecting the products individually to the above stated method steps, products in a great variety of dimensions can be processed. The method and device according to the invention are particularly suitable for manufacturing pilot series on laboratory scale.
    Type: Grant
    Filed: September 14, 1993
    Date of Patent: May 2, 1995
    Assignee: ASM-Fico Tooling B.V.
    Inventor: Hendrikus T. Berendts
  • Patent number: 5408741
    Abstract: The exposed portions of the leads of a semiconductor chip package are first bent in a forming process so that the ends of the leads are in proper positions to be attached to and electrically connected to contacts on a printed circuit board. Intermediate portions of the leads between the distal ends and the package body for connection to the printed circuit board and the package body are enclosed and fixed in position by a carrier body to hold the leads in position and to reduce the effects of any bending in destroying the coplanarity of the distal lead ends of the package. The package with the carrier body may be mounted onto the printed circuit board without first removing the carrier body. After the distal ends of the leads have been soldered to the printed circuit board, the carrier body is then removed.
    Type: Grant
    Filed: October 29, 1992
    Date of Patent: April 25, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5406699
    Abstract: An electronics package is provided with a substrate on which a patterned circuit is printed, a plurality of conductive leads connected to the patterned circuit along the periphery of the substrate, a first mold body arranged along the periphery of the substrate to reinforce the connection of the conductive leads to the patterned circuit, a plurality of chips attached on the substrate, a plurality of bonding wires connecting an integral circuit formed in each of the chips to the patterned circuit, and a second mold body arranged over the chips and the substrate. The second mold body functions as an insulating protector to protect the chips from an external obstacle and corrosive gases. An electric signal applied to one of the conductive leads is transferred to one of the chips through the patterned circuit and one of the bonding wires. The electric signal is processed in the chip to produce an output signal.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: April 18, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenshu Oyama
  • Patent number: 5406700
    Abstract: Disclosed is an integrated circuit lead frame which comprises: a die-pad; die-pad suspension leads for supporting the die-pad; a number of inner leads provided around the die-pad so as to be separated from the die-pad at a predetermined distance, and connected through wires with electrodes of an integrated circuit fixed onto the die-pad; wherein a step portion having a sharp corner portion is provided in at least one portion of the lead frame. Further disclosed is a method of producing such an integrated circuit lead frame as mentioned above, wherein a portion between one of the die-pad suspension leads and one of the inner leads adjacent to the one die-pad suspension lead is stamped out through two or more .steps to thereby form a step portion having a sharp corner portion in a side portion of the one die-pad suspension lead or the one inner lead.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: April 18, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Yuji Ito
  • Patent number: 5408050
    Abstract: Disclosed is a flat cable having a plurality of parallel-arranged flexible conductor wires and two pieces of insulating tape applied to the opposite center areas of the parallel arrangement of conductor wires leaving their opposite ends exposed, thereby permitting the exposed ends to be used as terminal contacts, each of said conductor wires having an intermediate length of reduced width for increasing the flexibility of the conductor wire. An elongated strip of electrically conductive, flexible metal foil is unrolled and fed to be punched to provide at one time, conductor wires of the same number and parallel arrangement as a flat cable to be made; two pieces of adhesive, insulating tape are applied to the center areas of the parallel conductor wire arrangement; and finally the opposite perforation edges are cut and removed.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: April 18, 1995
    Assignees: Honda Tsushin Kogyo Co., Ltd., Tohoku Honda Denshi Co., Ltd.
    Inventors: Kinji Kashio, Hikaru Mitani
  • Patent number: 5396701
    Abstract: The present invention provides a modular electronic component (10) wherein a sequence of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: March 14, 1995
    Assignee: Texas Instruments Inc.
    Inventor: Ernest J. Russell
  • Patent number: 5394608
    Abstract: A fabricating method of a laminated semiconductor device wherein two or more semiconductor chips are stacked as tape carrier packages and the tape carrier packages are mounted on at least one side of the printed wiring board so that outer connection leads provided in the tape carrier packages are stacked to be connected to the terminal porions of the printed wiring package, which includes stacking two or more tape carrier packages and aligning the outer connection leads of the tape carrier packages in the stacked direction, temporarily bonding the stacked outer connection leads to one another to combine the stacked tape carrier packages into one block, and placing the block on the printed wiring board and passing the terminal portions formed on the printed wiring board and lowermost outer connection leads of the block through a heating furnace to thereby solder them.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: March 7, 1995
    Assignee: Hitachi Maxwell, Ltd.
    Inventors: Takeshi Tottori, Satoshi Yamagata, Kazunari Nakagawa, Toshiharu Ochiai
  • Patent number: 5394675
    Abstract: A TAB (tape automated bonding) tape is disclosed which includes one or more openings, each adapted to receive a semiconductor chip, and electrical leads extending into each such opening. Significantly, this TAB tape also includes means for preventing a semiconductor chip, positioned within a tape opening, from being lifted toward a bonding tool as a result of electrical leads adhering to the bonding tool, when the bonding tool is used to bond contact pads on the semiconductor chip to the leads extending into the opening.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: March 7, 1995
    Assignee: International Business Machines Corp.
    Inventor: Katsuyuki Yonehara
  • Patent number: 5394607
    Abstract: The invention disclosed herein is a device and method in which a heat sink (22) is attached to support leads (18) of a leadframe (10) via a welding or mechanical joining technique. The method is performed prior to semiconductor device packaging and is usually performed after the leadframe is etched or stamped, and before it is cut into strips.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: March 7, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Tony Chiu, Robert Alvarez
  • Patent number: 5380952
    Abstract: A stabilizer bar made of non-conductive material (such as a poly enid plastic) is secured to the top side of extended leads on each side of a flat high density integrated circuit package. The bar is located intermediate the length of the leads, and is used as a lead form during a subsequent forming operation. The leads are formed around the stabilizer bar, which remains in place throughout the forming operation and during subsequent mounting of the integrated circuit package.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: January 10, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Paul S. Levy
  • Patent number: 5377403
    Abstract: A carrier frame has cells with inwardly extending thin flexible tabs. Pressure sensor housings are molded into the frame cells such that only the tips of the tabs penetrate the housing wall and after processing the housings are readily pushed out of the frame. A lead frame is insert molded at the same time. During molding the cells of the frame are open ended and after molding a reinforcing tie bar is attached across the open side of the frame to close the cells. A flange is bent up on the opposite side to lend rigidity to the frame. Preformed code flags are provided in the frame and selectively bent out for coding.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: January 3, 1995
    Assignee: Delco Electronics Corp.
    Inventors: John M. Hart, Jr., John M. Matly
  • Patent number: 5377077
    Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A plurality of level-one integrated circuit packages may be aligned and securely bound in a stacked configuration by use of a flexible high temperature material, such as silicon adhesive tape or a conformal coating, to form a thin and durable horizontal level-two package, or stack. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: December 27, 1994
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5375320
    Abstract: A method for forming a small outline "J" lead for a semiconductor device having a main body and a lead comprises three bend steps. The lead comprises a surface attached to the body, a distal end away from the body, and a proximal area interposed between the attached surface and the distal end. The method consists of the lead bend steps of rounding the distal end of the lead in a single bend step to form an are in the distal end having a radius of between 0.030" and 0.040", the arc terminating toward the proximal area of the leads in a substantially straight lead portion. Next, the proximal area of the lead is bent close to the attached surface such that the proximal area of the lead forms an angle of between about 60.degree. and 90.degree. with the attached surface of the lead. Finally, the arc in the distal end is increased to a radius of between about 0.035" and 0.045".
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: December 27, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Michael P. Grant, Gregory M. Chapman
  • Patent number: 5371943
    Abstract: A hole is formed in a metal plate, and after a concave portion is formed by pressurizing a predetermined area on the metal plate including the hole to cause plastic deformation, an island of a lead frame is formed in the concave portion. By forming the concave portion, the island and the inner lead are thinner than the outer lead, and the hole which has become smaller remains in the island.
    Type: Grant
    Filed: October 29, 1992
    Date of Patent: December 13, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 5367763
    Abstract: A method and apparatus for testing and connecting integrated circuit chips to external packaging and circuitry. A plurality of electrically conductive leads are formed on an electrically insulative substrate by tape automated bonding methods. The leads extend from peripherally disposed test terminals to centrally disposed interconnect pads and are aligned therebetween with bond pads that are disposed near a perimeter of a face of a chip. The leads are connected to the bond pads and are encapsulated with a cement, and the substrate is adhered to the chip face. Electronic characteristics of the chip are tested by channeling electrical signals via the test terminals. The leads are then severed closely peripheral to the bond pads, disconnecting the test terminals from the chip. The chips that pass the testing are connected via the interconnect pads, which may be arranged in a pad grid array, to matching terminals in a package.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: November 29, 1994
    Assignee: Atmel Corporation
    Inventor: Ken Lam
  • Patent number: 5361490
    Abstract: Deformation of TAB tapes due to temperature changes is prevented by thermo-mechanical leads. In one embodiment of the invention, a semiconductor device (30) includes an electronic component (31) and a TAB tape. The tape includes a carrier film (12) and electrical leads (20) formed on the carrier film. The electrical leads are electrically coupled to the electronic component. Also included on the carrier film are thermo-mechanical leads (32) which are formed in opposing regions of the carrier film, regions which are typically void of leads. The thermo-mechanical leads have approximately the same lead pitch as the electrical leads in order to provide a uniform distribution of stresses across the TAB tape upon exposure to varying temperatures.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: November 8, 1994
    Assignee: Motorola, Inc.
    Inventors: Leo M. Higgins, III, Maurice S. Karpman
  • Patent number: 5361486
    Abstract: A system of machining lead frames (7), such as punching, cutting and bending of the leads consists of a number of machining devices (1, 2, 3) placed in series. Transport means (8) are provided for transporting the lead frames between the successive machining device. Each device comprises means for transporting the lead frames in horizontal and vertical direction, a tool carrier driving means for driving the tool carrier (18). Further, a control device (4) is provided for controlling, synchronizing and protecting the operation of the machining devices. The machining devices are purely mechanically driven and the system is a device on a modular basis.
    Type: Grant
    Filed: August 20, 1993
    Date of Patent: November 8, 1994
    Assignee: ASM-FICO Tooling B.V.
    Inventors: Johannes G. T. Harmsen, Willem A. De Boer
  • Patent number: 5357674
    Abstract: A method of manufacturing a printed circuit board (PCB) for interconnecting integrated circuit devices includes a lead frame sandwiched between two multilayer substrates. Integrated circuit devices are mounted on the top of the upper substrate and on the bottom of the lower substrate to provide increased packaging density. Thus, according to the present invention, it is possible to provide a simply constructed electronic component mounting PCB which facilitates the design of circuits, and affords excellent connection reliability, which can readily form a heat radiating structure, and in which the thermal matching with the electronic component is excellent.
    Type: Grant
    Filed: August 4, 1993
    Date of Patent: October 25, 1994
    Assignee: Siemens Components, Inc.
    Inventor: Marvin Lumbard
  • Patent number: 5347709
    Abstract: A lead frame at least provides a semiconductor-element-mounting portion, plural leads and plural auxiliary leads. The auxiliary leads are arranged to be associated with plural leads, while a tie bar is provided and connected among the leads. According to a method of making the lead frame, an IC-chip mounting process, a wire-bonding process, a sealing process, a resin-cutting process and a dambar-cutting process are sequentially effected on the lead frame. After effecting the dambar-cutting process, a thin-plating process is effected so as to form a thin-plated layer, approximately having a thickness of 5 .mu.m to 15 .mu.m, on the leads. Then, the leads are bent by a predetermined bending process. Thereafter, a thick-plating process is effected so as to form an uniform thick-plated layer, approximately having a thickness of 15 .mu.m to 100 .mu.m, on the leads. After effecting the thick-plating process, a trimming process is effected on the leads.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: September 20, 1994
    Assignee: Yamaha Corporation
    Inventors: Yoshihisa Maejima, Seiya Nishimura, Masayoshi Takabayashi, Tokuyoshi Ohta
  • Patent number: 5345670
    Abstract: A magnetic device (10), suitable for attachment to a substrate, includes at least one sheet winding (24) having a pair of spaced-apart terminations (26), each receiving an upwardly rising portion (28) of a lead (12). The sheet winding terminations and upwardly-rising lead portions, together with at least a portion of the sheet windings, are then encapsulated with masses of insulative material (18, 19 and 34). A ferromagnetic core (20,22) surrounds at least a portion of the sheet windings to impart a desired magnetic property to the device.
    Type: Grant
    Filed: December 11, 1992
    Date of Patent: September 13, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Lennart D. Pitzele, Matthew A. Wilkowski
  • Patent number: 5343615
    Abstract: A process for producing a semiconductor device having a package with a semiconductor element molded therein, and a plurality of leads, each constituted by an inner lead located inside the package and an outer lead located outside the package, the leads being arranged in a line at a predetermined pitch, and the semiconductor element being electrically connected to the inner lead of each of the leads, wherein each side edge of each of the outer leads is flat.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: September 6, 1994
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Akihiro Kubota, Junichi Kasai, Masanori Yoshimoto, Keiichi Masaki
  • Patent number: 5341563
    Abstract: The optical module manufacturing apparatus according to the present invention includes a pallet 205 on which the optically operating members and the lead frame are set to be kept in a positional relationship; a wire connection means 202 and 213 for connecting the wires to the members, the frame and the electronic circuits on the frame as the members and the frame remain kept in the positional relationship; conveyors 207, 208 and 209 for conveying the members and the frame to dies 204 after the connection as the members and the frame remain kept in the relationship; and a die-setting means 203 for setting the members and the frame in tile dies through the suction of the members and the frame away from the pallet onto the setting means after the conveyance as the members and the frame remain kept in the relationship.
    Type: Grant
    Filed: October 9, 1992
    Date of Patent: August 30, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsutoshi Kamakura, Akihiko Shioda, Yoshihide Enami, Hisao Go
  • Patent number: 5339518
    Abstract: A quad leadframe (30) for a semiconductor device is made from multiple dual-in-line leadframes (10). Two dual-in-line leadframes (10) are provided, wherein each leadframe has two opposing siderails (12) with a plurality of leads (14) connected to those siderails. The leads have a metal clad layer (16) on lead tips which are distal to the two siderails. Each leadframe also has another two opposing siderails (18) which are not connected to any leads. The two leadframes are stacked on top of one another, wherein one leadframe is rotated by substantially 90.degree. with respect to the other leadframe such that the leads of one leadframe are perpendicular to the leads of the second leadframe to form a quad configuration. The siderails enable alignment of the leadframes to each other. The two leadframes can then be optionally tack welded together at any location along the siderails.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: August 23, 1994
    Assignee: Motorola, Inc.
    Inventors: Truoc T. Tran, Wilhelm Sterlin
  • Patent number: 5338899
    Abstract: An electronic device (10) encased within a moulded package body (11) has a leadframe (12) extending therefrom. In order to protect the leads (16) for the electronic device a guard ring (14) is provided on the leadframe. By making the guard ring independently of the moulded package body and fitting it separately to the leadframe one can deal with packages of any size in a simple manner and irrespective of the material of the package body (11).
    Type: Grant
    Filed: May 14, 1992
    Date of Patent: August 16, 1994
    Assignee: LSI Logic Corporation
    Inventor: Trevor C. Gainey
  • Patent number: 5336564
    Abstract: A process for forming a keeper bar upon TAB tape leads for maintaining position of the leads during excise and form operations, integrated circuit placement, and lead bonding, utilizes the steps of immersing TAB tape into a bath of ultraviolet curable resin; directing ultraviolet radiation onto the TAB tape at location(s) where keeper bars are desired, so as to cure the resin to define the keeper bars; washing away uncured resin; and drying the TAB tape.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: August 9, 1994
    Assignee: Grumman Aerospace Corporation
    Inventor: Boris Moldavsky
  • Patent number: 5333375
    Abstract: An apparatus and method for simultaneously mounting lead strip segments onto each side of a rectangular ceramic substrate. Four lead strip mounting assemblies are equally spaced 90 degrees apart around a central vertically oriented substrate support so that each assembly is perpendicular an edge of a substrate on the support. Lead strip feed assemblies located adjacent each mounting assemblies cuts lead strip segments and feeds the lead strip segments into the mounting assemblies. The four mounting assemblies simultaneously mount the lead strip segments on the substrate.
    Type: Grant
    Filed: September 16, 1993
    Date of Patent: August 2, 1994
    Assignee: Die Tech, Inc.
    Inventors: Richard K. Dennis, Wade D. Myers, James A. Riddle
  • Patent number: 5323532
    Abstract: An apparatus and method (200) for providing a hybrid circuit assembly carrier bracket are included wherein the bracket is constructed and arranged to provide controlled placement of at least a first power transistor (124, 126) and to provide a highly efficient thermal transfer and dissipating arrangement. The bracket is constructed and arranged to provide for placement of at least a first substrate for a hybrid circuit assembly thereon, and includes at least a first power transistor aperture (120, 122) with at least two bracket projections (146, 148) for permitting placement of said transistor on plural electrical contacts (104, 106). The heat generated by components on the circuit board(s) is transferred and dissipated substantially by biasing at least one bracket projection member resiliently against a heat sink (108, 110, 112, 114, 116, 118).
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: June 28, 1994
    Assignee: Motorola, Inc.
    Inventors: Detlef W. Schmidt, John Lubbe