Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Patent number: 9374906
    Abstract: In a method for pre-treating a frame or carrier element for use in the production of a printed circuit board, wherein after the pre-treatment the frame or carrier element is coupled with at least one circuit board element and subjected to at least one processing or treatment step, particularly at an elevated temperature, together with the circuit board element, in particular mounting or populating of the circuit board element, it is provided that the frame or support or carrier element is subjected to a heat treatment at temperatures between 120° C. and 350° C., in particular 200° C. to 300° C., for a time period (ttot) of 5 to 300 seconds, in particular 10 to 200 seconds, whereby frame or carrier elements can be provided, which are reliably stable in terms of shape and dimensions.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: June 21, 2016
    Assignee: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Ljubomir Mareljic, Anderson Zhang
  • Patent number: 9357644
    Abstract: According to one embodiment, a joined structural body for mounting an electronic component on the body which is provided with a first member, a second member and a joining portion. The joining portion is provided between the first member and the second member so as to connect the first member and the second member with each other mechanically. The joining portion contains at least one metal of a tin, an indium or a zinc, and a copper. The content of the metal in the joining portion decreases toward a side of at least one of the first member and the second member, and the content of the copper in the joining portion increases in the same direction as the decreasing direction of the content of the metal.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: May 31, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka Takagi
  • Patent number: 9269836
    Abstract: A method is proposed for coating an optoelectronic chip-on-board module including a flat substrate populated with one or more optoelectronic components having at least one primary optical arrangement and optionally at least one secondary optical arrangement.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 23, 2016
    Assignee: Heraeus Noblelight GmbH
    Inventors: Michael Peil, Florin Oswald, Harald Maiweg
  • Patent number: 9256038
    Abstract: Provided is an optical module. The optical module includes: an optical bench having a first trench of a first depth and a second trench of a second depth that is lower than the first depth; a lens in the first trench of the optical bench; at least one semiconductor chip in the second trench of the optical bench; and a flexible printed circuit board covering an upper surface of the optical bench except for the first and second trenches, wherein the optical bench is a metal optical bench or a silicon optical bench.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 9, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Tak Han, Jang Uk Shin, Sang-Pil Han, Sang Ho Park, Yongsoon Baek
  • Patent number: 9256334
    Abstract: An injection molded product in which an electrical connection between a contact pin and an electrode pattern is sufficient, and a method of manufacturing the same, are provided. The injection molded product comprises: a base film; an electrode pattern, which is formed on the base film; an electrically conductive adhesive, which is formed on an upper surface of the electrode pattern; a contact pin, which contacts the electrically conductive adhesive, is electrically connected to the electrode pattern via the electrically conductive adhesive, and is electrically conductive; and a molded resin, which is injection molded along the base film such that the electrically conductive adhesive and part of the contact pin are embedded.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: February 9, 2016
    Assignee: NISSHA PRINTING CO., LTD.
    Inventors: Seiichi Yamazaki, Toshihiro Higashikawa, Tomohiro Matsuzaki, Masahiko Kariya
  • Patent number: 9236316
    Abstract: The present invention has a tray corresponding to a heat sink, a circuit part is accommodated in an accommodating part of the tray, and the circuit part is potting-sealed with a sealing resin such that external electrodes are exposed. The sealing resin covers and seals a top part of the tray.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 12, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yoshihiro Kashiba, Shohei Ogawa
  • Patent number: 9230892
    Abstract: A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 5, 2016
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventor: Shingo Itoh
  • Patent number: 9212298
    Abstract: The adhesive sheet of the invention comprises a resin composition containing (A) a high-molecular-weight component, (B1) a thermosetting component having a softening point of below 50° C., (B2) a thermosetting component having a softening point of between 50° C. and 100° C. and (C) a phenol resin having a softening point of no higher than 100° C., the composition containing 11 to 22 mass % of the (A) high-molecular-weight component, 10 to 20 mass % of the (B1) thermosetting component having a softening point of below 50° C., 10 to 20 mass % of the (B2) thermosetting component having a softening point of between 50° C. and 100° C. and 15 to 30 mass % of the phenol resin having a softening point of no higher than 100° C., based on 100 mass % of the resin composition.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 15, 2015
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Megumi Kodama, Takahiro Tokuyasu, Tetsurou Iwakura
  • Patent number: 9196562
    Abstract: A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least 10 micrometers (?m), the thick metal layer comprises copper or a copper alloy, and the bonding wire or ribbon comprises copper or a copper-based material.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dirk Siepe, Reinhold Bayerer
  • Patent number: 9166131
    Abstract: A light emitting diode package includes a first lead frame, a second lead frame and an encapsulant. The first lead frame has a die deposition area on the top thereof for disposing LED die. The second lead frame has a contacting face on the top thereof for wire bonding. The die deposition area of the first lead frame has a first adhesion area such that the encapsulant is held by the first adhesion area when enclosing the top and bottom of the first and second lead frames. The light is emitted in all directions.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: October 20, 2015
    Inventor: Tai-Yin Huang
  • Patent number: 9082760
    Abstract: A dual layered lead frame is provided with a die bonding layer and a solder layer. The dual layered lead frame has single lead frames arranged into a matrix layout with a cell gap formed between dual layered lead frame cells. Each dual layered lead frame cell includes a die bonding unit and a solder unit. The die bonding unit and the solder unit include conductive leads forming an insulating clearance between each and every conductive leads respectively. Each conductive lead includes slot holes. The insulating clearance, the slot holes, and the cell gap are filled with the insulating material so as to make the die bonding unit and the conductive lead of the solder unit, as well as the insulating clearance and the slot hole to match with one another and joined closely respectively.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: July 14, 2015
    Assignee: CHANG WAH TECHNOLOGY CO., LTD.
    Inventor: Chia-Neng Huang
  • Patent number: 9076777
    Abstract: A semiconductor device includes a die pad, which includes an upper surface and a lower surface, the upper surface forming a rectangular shape in plan view; a plurality of support pins that support the die pad; a plurality of inner leads arranged around the die pad; a plurality of outer leads connected to each of the inner leads; a semiconductor chip which includes a main surface and a back surface and in which a plurality of electrode pads is formed in the main surface; a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; and a sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires. A first support pin of the plurality of support pins is integrally formed together with the die pad. The first support pin is terminated inside the sealing body.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: July 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiharu Kaneda, Naoko Taniguchi
  • Patent number: 9076783
    Abstract: Methods and systems are disclosed for selectively forming metal layers on lead frames after die attachment to improve electrical connections for areas of interest on lead frames, such as for example, lead fingers and down-bond areas. By selectively forming metal layers on areas of interest after die attachment, the disclosed embodiments help to eliminate anomalies and associated defects for the lead frames that may be caused by the die attachment process. A variety of techniques can be utilized for selectively forming one or more metal layers, and a variety of metal materials can be used (e.g., nickel, palladium, gold, silver, etc.). Further, cleaning can also be performed with respect to the areas of interest prior to selectively forming the one or more metal layers on areas of interest for the leaf frame.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: July 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Rama I. Hegde
  • Patent number: 9069146
    Abstract: Provided is an optical module. The optical module includes: an optical bench having a first trench of a first depth and a second trench of a second depth that is lower than the first depth; a lens in the first trench of the optical bench; at least one semiconductor chip in the second trench of the optical bench; and a flexible printed circuit board covering an upper surface of the optical bench except for the first and second trenches, wherein the optical bench is a metal optical bench or a silicon optical bench.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 30, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Tak Han, Jang Uk Shin, Sang-Pil Han, Sang Ho Park, Yongsoon Baek
  • Publication number: 20150118921
    Abstract: A leadframe for a contact module includes signal contacts arranged in pairs carrying differential signals. Each pair of signal contacts includes a first signal contact and a second signal contact. Each signal contact has a mating beam at an end thereof configured to be electrically connected to a corresponding header contact of a header assembly. Each mating beam includes a stem and a branch extending from the stem. A first paddle extends from the stem and a second paddle extends from the branch. In an initial, stamped orientation, the mating beams are stamped such that the mating beams of the first and second signal contacts within the same pair of signal contacts are angled non-parallel to one another.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Tyco Electronics Corporation
    Inventors: Michael Joseph Vino, IV, Leo Joseph Graham, Michael Christopher D'Imperio, David Allison Trout, Wayne Samuel Davis, Rodney Timothy Yancey, Jeffrey Byron McClinton
  • Publication number: 20150108531
    Abstract: A method of producing a component carrier for an electronic component includes a lead frame section including an electrically conductive material, the lead frame section having a first contact section that forms a first electrical contact element, a second contact section that forms a second electrical contact element, and a reception region that receives the electronic component, at least the reception region and the second contact section being electrically conductively connected to one another, a thermally conductive and electrically insulating intermediate element that dissipates heat from the reception region and electrically insulates the reception region formed at least on an opposite side of the lead frame section from the reception region, and a thermal contact that thermally contacts the electronic component formed at least on a side of the intermediate element facing away from the reception region.
    Type: Application
    Filed: May 7, 2013
    Publication date: April 23, 2015
    Applicant: OSRAM Optp Semiconductors GmbH
    Inventors: Thomas Schwarz, Stefan Grötsch, Michael Zitzlsperger
  • Patent number: 9006038
    Abstract: A method for fabricating a leadframe strip is disclosed. A leadframe pattern is formed from flat sheet of base metal. Additional metal layers are plated on patterned tape of base metal and the leadframe surface is roughed. A first set of leadframe areas is planished. A second set of leadframe areas are offsetted and the tape is cut into strips.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Publication number: 20150085524
    Abstract: A light emitting device includes a support having an interstice and at least one LED located in the interstice and at least one of a waveguide or an optical launch having a transparent material encapsulating the at least one LED located in the interstice.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Ping WANG, Douglas HARVEY, Tyler KAKUDA, Ronald KANESHIRO
  • Patent number: 8973250
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming a wiring layer on a substrate comprising actuator electrodes and a contact electrode. The method further includes forming a MEMS beam above the wiring layer. The method further includes forming at least one spring attached to at least one end of the MEMS beam. The method further includes forming an array of mini-bumps between the wiring layer and the MEMS beam.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Publication number: 20150062837
    Abstract: A lead frame for a premold sensor housing, in which the lead frame includes at least one angled section having essentially no rounding in an area of contact with the premold sensor housing, the area of contact being provided as a positioning area for a sensor element.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: Robert Bosch GmbH
    Inventors: Nico GREINER, Ingo HENKEL, Eckart SCHELLKES
  • Patent number: 8969730
    Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Anthony S. Montevirgen, Emery A. Sanford, Stephen Brian Lynch
  • Patent number: 8950067
    Abstract: An electronic component device having a first sealing frame formed on a main substrate and a second sealing frame formed on a cover substrate, the first and second sealing frames being composed of a Ni film. A bonding section constituted by a Ni—Bi alloy is formed between the first and second sealing frames. For example, a Bi layer is formed on the first sealing frame, and then the first sealing frame and the second sealing frame are heated at a temperature of 300° C. for at least 10 seconds while applying pressure in the direction in which the first sealing frame and the second sealing frame are in close contact with each other, and thus the bonding section, which bonds the first sealing frame to the second sealing frame, is formed.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroki Horiguchi, Yuji Kimura
  • Publication number: 20150027767
    Abstract: A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheila F. Chopin, Varughese Mathew
  • Publication number: 20150001696
    Abstract: Various embodiments provide a method of manufacturing a semiconductor die carrier structure. The method may include providing a die pad configured to carry a semiconductor die thereon; and bending at least one portion of the die pad, wherein the at least one bent portion extends across the die pad.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventor: Chai Chee Meng
  • Publication number: 20150001646
    Abstract: A microphone assembly is provided, wherein the pre-mold comprises a bent leadframe and a mold body, wherein the mold body is mold to at least partially encapsulate the bent leadframe to build the pre-mold comprising a cavity for accommodating a microphone, and wherein the pre-mold comprises a through-hole transmissive for sound waves.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventors: Thomas MUELLER, Horst Theuss, Stefan Uwe Schindler, Dominik Kohl, Jochen Dangelmaier
  • Publication number: 20140367838
    Abstract: A leadframe that includes a die attachment pad and a lead having a bondwire attach portion with a thickness less than 50% of the thickness of an adjacent portion of the lead. Also a method of forming a leadframe includes forming a lead having a bond wire attach portion with an original thickness and coining the bond wire attach portion to a thickness less than 50% of the original thickness. An integrated circuit package and a method of forming an integrated circuit package are also disclosed.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Donald Charles Abbott, Masood Murtuza
  • Publication number: 20140347838
    Abstract: An electronic device includes first to third terminals and a clip. The clip includes first to third joint portions and a connection portion. The first to third joint portions correspond to and are bonded to the first to third terminals, respectively. The connection portion connects the first to third joint portions. One terminal in the first to third terminals has a depressed portion depressed to one side in a predetermined direction to store a conductive bonding material. A variation in positions of the first to third terminals in the predetermined direction is absorbed by deformation of the conductive bonding material when one joint portion in the first to third joint portions corresponding to the one terminal is bonded to the one terminal through the conductive bonding material.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: DENSO CORPORATION
    Inventors: Toshihiro NAGAYA, Nobuhiko OKADA, Hiromasa HAYASHI
  • Publication number: 20140338956
    Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of manufacturing lead frames includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 20, 2014
    Inventors: Dwight L. DANIELS, Stephen R. HOOPER, Alan J. MAGNUS, Justin E. POARCH
  • Patent number: 8887386
    Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: November 18, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
  • Publication number: 20140319663
    Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 30, 2014
    Inventors: Satoshi SHIBASAKI, Koji TOMITA, Masaki YAZAKI, Kazuyuki MIYANO, Atsushi KURAHASHI, Kazuhito UCHIUMI, Masachika MASUDA
  • Patent number: 8869389
    Abstract: An electronic device package 100 comprising a lead frame 105 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 28, 2014
    Assignee: LSI Corporation
    Inventors: Larry Golick, Qwai Hoong Low, John W. Osenbach, Matthew E. Stahley
  • Patent number: 8866502
    Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: October 21, 2014
    Assignee: Broadcom Corporation
    Inventors: Arya Reza Behzad, Ahmadreza Rofougaran, Sam Ziqun Zhao, Jesus Alfonso Castaneda, Michael Boers
  • Publication number: 20140290051
    Abstract: The present invention consists to a method of manufacturing a data carrier (1), comprising a data carrier body (3) and a module (5) fixed above a cavity in said data carrier body (3), said method comprising the following steps:—a first step (101) of providing a module (5),—a second step (102) of applying a preformed first layer (31) on the dielectric substrate (53) of said module (5), said first layer (31) having a hole (33) to receive the electronic chip (55), its wires (57) and the dielectric resin protection (59),—a third step (103) of applying a second layer (35) on the first layer (31), recovering the hole (33) of the first layer (35),—a fourth step (104) of laminating of the module (5), the first and second layers (31, 35),—a fifth step (105) of cutting or pre-cutting at the data carrier format.
    Type: Application
    Filed: September 28, 2011
    Publication date: October 2, 2014
    Applicant: GEMALTO TECHNOLOGIES ASIA LTD
    Inventor: Chi Tung Tsoi
  • Patent number: 8839508
    Abstract: A fabrication method for a low-cost high-frequency electronic device package having waveguide structures formed from the high frequency device to the package lead transition. The package lead transition is optimized to take advantage of waveguide interconnect structure.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 23, 2014
    Assignee: Rosenberger Hochfrequenztechnick GmbH & Co. KG
    Inventors: Eric A. Sanjuan, Sean S. Cahill
  • Patent number: 8837164
    Abstract: There are provided a substrate for mounting a device and a package for housing the device employing the same in which a power semiconductor device can be readily set for a temperature suitable for operation and can thus function in a proper fashion. The substrate for mounting the device includes a support body having, on one main surface of the support body, a device mounting portion for mounting a power semiconductor device, the support body having a plurality of columnar parts that are spaced apart in a thickness direction with respect to the device mounting portion and are arranged apart from each other; and a heat accumulating region which is disposed between the columnar parts and is lower in thermal conductivity than the support body.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: September 16, 2014
    Assignee: Kyocera Corporation
    Inventors: Kazuhiro Kawabata, Kiyoshige Miyawaki, Yoshiaki Ueda, Shinji Nakamoto, Tsutomu Sugimoto
  • Patent number: 8754665
    Abstract: A dual-stage fixture for a circuit tester includes a slide plate that can be slid between at least a first position and a second position. In the first position, an upper stripper plate is spring-loaded, and a full set of test probes, including both long-stroke and short-stroke probes, can contact the circuit board or UUT (unit under test). In the second position, the upper stripper plate becomes fixed in position, and only the long-stroke probes can contact the circuit board. The fixed positioning of the upper stripper plate prevents the short-stroke probes from contacting the circuit board even when there is unbalanced loading of probe pressure between the top and bottom of the circuit board, thereby preventing transient signals from interfering with testing. In addition, a vacuum is applied in this position during a non-powered test.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: June 17, 2014
    Assignee: Circuit Check, Inc.
    Inventors: Clement C. Adams, Matthew Eric Lavik, Gregory J. Michalko, Stuart Eickhoff
  • Publication number: 20140130346
    Abstract: Sensor package 1 and a corresponding manufacturing method, wherein the sensor package 1 includes several components like a magneto resistive sensor 40 and electronic components 30, and the orientation of the elements and components is maintained by a moulding body 200 manufactured in a single moulding step.
    Type: Application
    Filed: January 15, 2014
    Publication date: May 15, 2014
    Applicant: NXP B.V.
    Inventors: Paulus Martinus Catharina HESEN, Roelf Anco Jacob GROENHUIS, Johannes Wilhelmus Dorotheus BOSCH
  • Patent number: 8720047
    Abstract: Described herein are casting and molding methods useful for making microstructured objects. By including a plurality of microfeatures on the surface of an object, other characteristics may be imparted to the object, such as increased hydrophobicity. Some of the casting and molding methods described herein further allow for manufacture of objects having both microfeatures and macro features, for example microfeatures on or within macro features or selected macro feature regions.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: May 13, 2014
    Assignee: Hoowaki, LLC
    Inventors: Ralph A. Hulseman, Robert E. Mammarella, March Maguire
  • Patent number: 8716069
    Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 6, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Yongping Ding
  • Patent number: 8710645
    Abstract: Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: April 29, 2014
    Inventor: Jeng-Jye Shau
  • Patent number: 8701272
    Abstract: A method of forming a power module located on a conductive substrate by providing power conversion circuitry. The method of providing the power conversion circuitry includes forming a magnetic device by placing a magnetic core proximate a conductive substrate with a surface thereof facing a conductive substrate, and placing a conductive clip proximate a surface of the magnetic core. The method of forming the magnetic device also includes electrically coupling ends of the conductive clip to the conductive substrate to cooperatively form a winding therewith about the magnetic core. The method of providing the power conversion circuitry also includes providing at least one switch on the conductive substrate. The method of forming the power module also includes depositing an encapsulant about the power conversion circuitry.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: April 22, 2014
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Mathew A. Wilkowski, Trifon M. Liakopoulos, John D. Weld
  • Patent number: 8701284
    Abstract: A method of manufacturing an electrical connector comprises steps of providing a series of generic lead frames each having an array of contacts arranged in a common generic pattern, removing from one of the generic lead frames a first subset of the contacts to form a first pattern of contacts having a first spaced-apart relationship, removing from another of the generic lead frames a second subset of the contacts to form a second pattern of contacts having a different second spaced-apart relationship, wherein the first and second patterns are selectively obtained from the generic pattern, and loading the first and second patterns of contacts into a housing.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 22, 2014
    Assignee: Tyco Electronics Corporation
    Inventors: Matthew Richard McAlonis, Jeffrey Joe Brown
  • Publication number: 20140098508
    Abstract: A direct-connect orthogonal electrical connection system with improved high frequency performance is provided. A conductive member is provided between first and second components, each having signal and ground conductors. The conductive member is electrically coupled to ground conductors of both the first and second components and may also have openings through which signal conductors of the first and second components may connect. As such, signal conductors may be positioned relative to the conductive member such that a uniform impedance is maintained along a signal path throughout the interconnection, reducing noise and reflections. The signal conductors may be formed with multiple beams of different lengths to create multiple points of contact distributed along an elongated dimension. For example, a third beam may be fused to a mating portion to allow a tolerance for deviations in alignment between two directly connected connectors.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 10, 2014
    Applicant: Amphenol Corporation
    Inventor: John Robert Dunham
  • Publication number: 20140099844
    Abstract: A direct-attach orthogonal electrical connection system with improved high frequency performance is provided. A conductive member is provided between first and second components, each having signal and ground conductors. The conductive member is electrically coupled to ground conductors of both the first and second components and may also have openings through which signal conductors of the first and second components may connect. As such, signal conductors may be positioned relative to the conductive member such that a uniform impedance is maintained along a signal path throughout the interconnection, reducing noise and reflections. The first-type conductive elements may be formed with multiple beams of different lengths to create multiple points of contact distributed along an elongated dimension. For example, a third beam may be fused to a mating portion to allow a tolerance for deviations in alignment between two directly attached connectors.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 10, 2014
    Applicant: Amphenol Corporation
    Inventor: John Robert Dunham
  • Patent number: 8674232
    Abstract: A device-embedded flexible printed circuit board (FPCB) and a method of manufacturing the device-embedded FPCB are provided. The device-embedded FPCB includes: a first conductive layer; a first insulating layer which is disposed on the first conductive layer and includes at least one bump hole and at least one groove; a first plating layer which is formed in the at least one groove of the first insulating layer; and a device which includes at least one bump which is inserted into the at least one bump hole to be connected to the first conductive layer.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Techwin Co., Ltd.
    Inventors: Yang-sik Cho, Sung-taik Hong, Gun-ho Wang
  • Patent number: 8658901
    Abstract: Motor vehicle conductor connection element includes a first flat part and an inlay arranged in the flat part so as to be substantially flush with a surface of the flat part. In order to ensure contacting with different conductors, the flat part is substantially coated with a metal and the inlay is partially coated with the metal.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: February 25, 2014
    Assignee: Auto Kabel Managementgesellschaft mbH
    Inventors: Martin Schloms, Sebastian Martens, Franz-Josef Lietz
  • Publication number: 20140048920
    Abstract: A metal leadframe strip (500) for semiconductor devices comprising a plurality of sites (510) for assembling semiconductor chips, the sites alternating with zones (520) for connecting the leadframe to molding compound runners; the sites (510) having mechanically rough and optically matte surfaces (511, 512); the zones (520) having at least portions with mechanically flattened and optically shiny metal surfaces (521, 522); and the flattened surface portions transitioning into the rough surface portions by a step.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Publication number: 20140036471
    Abstract: Systems and methods are disclosed herein for a low cost, compact size, and thin half-etched leadframe quad-flat no-leads (QFN) package that integrates RF passive elements in the QFN leadframe for linearized PA design and RF FEMs. The integrated RF passive elements in the QFN leadframe may include RF inductors (e.g., meanders lines or spirals) for amplifier bias or RF matching, extension bar of the ground paddle for inter-stage matching or jumper pads for connection. The integrated RF passive elements may also include transmission lines for output power matching, coupled line structures such as RF couplers, RF divider or combiner realized using transmission lines with proper impedance and length, jumper pads for adjusting the bond wire length, etc. The RF parameters of the integrated passive elements are adjustable using different length and number of wire bond for fine tuning the performance of the PAM or the RF FEM.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 6, 2014
    Inventors: Cindy Yuen, Duc Chu
  • Publication number: 20140020926
    Abstract: A lead frame comprises a plurality of electrical connection portions, a frame portion, and a plurality of connections. The frame portion comprises a segment and at least one opening that defines the segment. Each connection connects to at least one of the plurality of electrical connection portions. The plurality of connections are arranged along a direction passing through the at least one opening and the segment. A dimension of the segment in the direction is less than 2.7 millimeters.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 23, 2014
    Inventor: YA-CHING FENG
  • Patent number: RE45143
    Abstract: An apparatus for equalizing voltage across an electrical lighting system, particularly in low voltage landscape lighting systems. The apparatus consists of a plastic cylinder having open ends and containing two or more connectors for connecting a homerun wire from a transformer to wire leads from the various light fixtures in the lighting system. The wire leads are of uniform length to ensure that each light fixture is ecu equally distant from the transformer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: September 23, 2014
    Assignee: The Toro Company
    Inventor: Nate Mullen