Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Publication number: 20090247242
    Abstract: A continuous housing (100) and integral user interface (101) is disclosed. The housing comprising a continuous housing having a cavity (117) to receive an electrical component and to surround the component on a plurality of sides. The housing further comprises, an integral user interface portion incorporated into a continuous housing portion.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: MOTOROLA INC
    Inventors: JASON P. WOJACK, Joseph L. Allore, Gary R. Weiss
  • Publication number: 20090243055
    Abstract: A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads and is formed a plurality of contact faces with height differences, a second protrusion portion is protruded from each of the second inner leads. Therefore, the wires connected to the stacked chips, the first protrusion portion of the first inner leads, and the second protrusion portion of the second inner leads can be shorten. And, the wire sweep and short-circuit can be prevented during molding process. In addition, the present invention also discloses a leadframe and manufacturing method for the leadframe and its semiconductor packaging structure.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 1, 2009
    Inventor: Chin-Ti Chen
  • Patent number: 7570135
    Abstract: A method is provided for producing a piezoelectric vibrator having an airtight terminal comprised of an annular stem, a lead disposed to pass through the stem and formed of a conductive material, and a filler for fixing the lead in the stem, and the piezoelectric vibrator having a vibrating piece connected to the lead of the airtight terminal and a case bonded to the airtight terminal to cover the vibrating piece. The method comprises an airtight terminal production process that produces the airtight terminal on a lead frame, and a piezoelectric vibrator assembly process that assembles the piezoelectric vibrator using the produced airtight terminal and on the same lead frame on which the airtight terminal is produced.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: August 4, 2009
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Nishino, Hiroaki Uetake, Yuki Hoshi
  • Patent number: 7563647
    Abstract: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 21, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Henry D. Bathan, Il Kwon Shim, Jeffrey D. Punzalan, Zigmund Ramirez Camacho
  • Patent number: 7546675
    Abstract: A method for manufacturing wireless communication devices for use in tracking or identifying other items comprises a number of cutting techniques that allow the size of the antenna for the wireless communication device. Further, the chip for the wireless communication device is nested so as to be flush with the surface of the substrate of the wireless communication device. Rollers cut the tabs that form the antenna elements. In a first embodiment, a plurality of rollers are used, each of effecting a different cut whose position may be phased so as to shorten or lengthen the antenna element. In a second embodiment, the rollers are independently positionable to shorten or lengthen the antenna element.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: June 16, 2009
    Inventors: Ian J Forster, Patrick F King
  • Patent number: 7547581
    Abstract: It is suppressed that a whisker occurs on a lead for external connection. A lead for external connection is formed of the alloy (42Alloy) of Fe and Ni, and a plating film which includes alloy of Sn and Cu is formed on the surface. Next, using a heat-treat furnace, the heat treatment at the temperature beyond melting-point T0 of the plating film is performed, and the plating film is melted. At this time, the temperature beyond T0 is held for 20 seconds or more. The grain boundary of the plating film can be vanished by the above-mentioned heat treatment. Hereby, the internal stress of the plating film can be eased, and the generation of the whisker can be suppressed.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 16, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yumi Imamura, Kenji Yamamoto, Tomohiro Murakami
  • Publication number: 20090140725
    Abstract: An integrated circuit includes a magnetic field sensor and an injection molded magnetic material enclosing at least a portion of the magnetic field sensor.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 4, 2009
    Applicant: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • Publication number: 20090106974
    Abstract: A method of producing an overmolded electronic assembly including a circuit board and a flexible circuit interconnect by fixturing the assembly in a mold cavity such that a portion of the flexible circuit protrudes from the mold, and providing a compressible elastomeric interface between the mold and the flexible circuit to seal off the mold cavity and protect the flexible circuit from damage due to the clamping force of the mold. The portion of the flexible circuit within the mold cavity is pre-coated with a material that ensures good adhesion with the molding compound, and a heat exchanger thermally coupled to the portion of the flexible circuit that protrudes from the mold protects the flexible circuit from damage due to thermal conduction from the mold and mold compound.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 30, 2009
    Inventors: Scott D. Brandenburg, David A. Laudick, Gary E. Oberlin
  • Publication number: 20090091013
    Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.
    Type: Application
    Filed: September 15, 2008
    Publication date: April 9, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshiyuki Fukuda, Yoshihiro Tomita, Hisashi Umeda, Yasutake Yaguchi
  • Patent number: 7508054
    Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: March 24, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
  • Patent number: 7503112
    Abstract: Methods of manufacturing lead frame connectors for use in connecting optical sub-assemblies to printed circuit boards in optical transceiver modules are disclosed. The lead frame connectors are formed by first stamping a selected configuration of conductors in a conductive ribbon. Each of the conductors can then be secured in a fixed position with respect to each other. A casing having a first part and a second part can then be molded about the conductors such that each of the conductors forms an electrical contact restrained in a fixed position with respect to the first part and a contact point extending from the second part. The conductors can be bent into any desired position to allow the electrical contacts to be connected to the optical sub assembly and the contact points to be connected to the printed circuit board.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: March 17, 2009
    Assignee: Finisar Corporation
    Inventors: Donald A. Ice, Darin James Douma
  • Publication number: 20090056121
    Abstract: An electronic component package includes: a main body including a plurality of layer portions that are stacked and that have their respective side surfaces, the main body having a side surface including the side surfaces of the layer portions; and wiring disposed on the side surface of the main body. Each of the layer portions has at least one electronic component chip and a plurality of electrodes disposed on the side surface of the layer portion.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 5, 2009
    Applicants: HEADWAY TECHNOLOGIES, INC., SAE MAGNETICS (H.K.) LTD.
    Inventors: Yoshitaka Sasaki, Tatsushi Shimizu
  • Patent number: 7497011
    Abstract: A hoop molding method comprises forming, in the frame portions, connection portions that link, to the frame portions, at least one molded portion of the at least one bent molded portion or at least another molded portion other than the at least one bent molded portion such that it is displaceable in a direction toward another molded portion along the width direction of the parent material, and displacing the at least one molded portion of the at least one bent molded portion or the at least another molded portion other than the at least one bent molded portion toward the another molded portion after the bending.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Koji Suzuki, Fusatomo Miyake
  • Patent number: 7495461
    Abstract: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 24, 2009
    Assignee: Cascade Microtech, Inc.
    Inventors: Leonard Hayden, John Martin, Mike Andrews
  • Publication number: 20090044402
    Abstract: A method for manufacturing a pre-molding leadframe strip with compact components is disclosed. The method forms a leadframe strip with an array of component regions, each component region including two metal parts for using as a chip-attached portion, a wire-bonded portion and two external electrical connection conductors. Next, the leadframe strip is plated with a metal layer having high conductivity and die bonding adhesion. Finally, a pre-molded structure on each of the component regions is formed to surround all the other portions of the leadframe strip with an exception of only the two external electrical connection conductors through a multiplicity of pre-molding processes, each pre-molding process molding the leadframe strip at an interval of one or more than one component regions.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 19, 2009
    Inventor: Jau-Shyong Chen
  • Publication number: 20090045492
    Abstract: A lead frame is provided which can prevent a short circuit between wires and the ends of adjacent leads, the short circuit being caused by wire sweep during the injection of molding resin, in a configuration where the electrodes of a semiconductor chip and the leads disposed around the semiconductor chip. The lead having sides substantially perpendicular to the direction of a resin flow has an end whose upstream side relative to the resin flow is constricted.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 19, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Akira Oga
  • Publication number: 20090039486
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Application
    Filed: April 26, 2006
    Publication date: February 12, 2009
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20090042339
    Abstract: Packaged integrated circuits and methods to form a packaged integrated circuit are disclosed. A disclosed method comprises attaching an integrated circuit to a substrate, coupling a first end of a bond wire directly to the substrate without an intervening bonding pad and a second end of the bond wire to a contact of the integrated circuit, encapsulating the integrated circuit and the bond wire, and removing the substrate to expose the first end of the bond wire.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 12, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saat Shukri Embong, Suhairi Mohmad, Mohd Hanafi Bin Mohd Said
  • Publication number: 20090038829
    Abstract: A printed circuit board for population with surface-mounted devices is provided simultaneously with a lead frame, which has a three-dimensional shape and which is surrounded by a plastic.
    Type: Application
    Filed: June 8, 2007
    Publication date: February 12, 2009
    Inventors: Erik Reischl, Peter Leng
  • Patent number: 7484291
    Abstract: A method of manufacturing a disk drive for use with a host electronic unit (HEU). The HEU including a printed circuit board having a socket and HEU disk drive circuitry. The method includes providing a lead frame. The lead frame is a single component having material continuity rather than an assembly of subcomponents. The method includes forming a plurality of leads in the lead frame by removing material of the lead frame, and attaching the lead frame to a housing body. The housing body defines a housing periphery sized and configured to be engaged within the socket. The leads extend to the housing periphery. The method includes attaching a disk drive electrical component to the housing body, and electrically connecting the disk drive electrical component to at least one of leads. The disk drive circuitry is located on the HEU printed circuit board rather than within the housing periphery.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: February 3, 2009
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel R. Ostrander, William W. Garrett
  • Publication number: 20090014854
    Abstract: Provided are a lead frame and a semiconductor package including the same. The lead frame includes a first lead frame portion including a plurality of first leads; an adhesive member disposed such that the first leads are adhered to one surface of the adhesive member; and a second lead frame portion including a plurality of second leads disposed such that the second leads are adhered to the other surface of the adhesive member, wherein the second leads are arranged so as not to overlap with the first leads. The lead frame may optionally include a die pad on which a semiconductor chip is installed.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 15, 2009
    Applicant: Samsung Techwin Co., Ltd.
    Inventors: Se-hoon Cho, Jeung-il Kim, Sang-moo Lee
  • Patent number: 7475460
    Abstract: A method for producing an airtight terminal having an annular stem, a lead passing through the stem and formed of a conductive material, and a filler for fixing the lead in the stem includes (1) a lead contour formation step of disposing a base and a lead formation portion on a plate- or strip-shaped conductive material and forming a contour of the lead on the lead formation portion with at least one end of the lead connected to the base, (2) a filler shaping and sintering step of filling the lead having a contour with the filler in a predetermined position and shaping and sintering the filler, (3) a stem mounting step of mounting the stem to a perimeter of the sintered filler, (4) a firing step of heating, melting, and cooling the sintered filler in the stem and bringing the lead into close contact with the stem to fix the lead to the stem through the filler, (5) a metal film formation step of forming a metal film on a surface of the lead, and (6) a cutting step of separating the one end of the lead from the
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: January 13, 2009
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Nishino, Hiroaki Uetake, Yuki Hoshi
  • Publication number: 20090008755
    Abstract: A structure of an SMD (surface mount device) diode frame is provided that comprises a plastic seat and a plurality of metal pins. One side of the plastic seat has a concave functional area and the other side of the plastic seat corresponding to the functional area has a plurality of concave reserved holes. The functional area and the reserved holes are respectively formed via a forming bolt and a positioning bolt in a mold. If the forming bolt and the positioning bolt abut against the metal pins respectively, the preciseness of the size of the functional area is increased and the overflow of the material of the plastic seat is decreased. Furthermore, the yield of the manufacturing processes is improved.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 8, 2009
    Applicant: I-CHIUN PRECISION INDUSTRY CO., LTD.
    Inventor: WAN-SHUN CHOU
  • Publication number: 20080303127
    Abstract: A cap-less package comprises: a metallic die pad part; a submount mounted on the die pad part; an optical semiconductor element mounted on the submount; an insulating member fixed to the die pad part; a lead electrode inserted in the insulating member; and a wire connecting the lead electrode to the semiconductor optical element, wherein the submount, the optical semiconductor element, a portion of the lead electrode closer to the optical semiconductor element than to the insulating member, and the wire are located opposite the die pad part.
    Type: Application
    Filed: May 22, 2008
    Publication date: December 11, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Junji Fujino
  • Publication number: 20080296746
    Abstract: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 4, 2008
    Applicants: NEC ELECTRONICS CORPORATION, HITACHI CABLE PRECISION CO., LTD.
    Inventors: Akimi SAIKI, Hiroyuki SHOJI, Gousuke TAKAHASHI, Noriyuki HASEGAWA, Fumio TAKANO, Kouji SATO
  • Publication number: 20080289853
    Abstract: In a composite body, a frame body to be connected to a first major surface of a substrate body includes a frame member made of an insulating material and a plurality of connection members formed by bending thin metal plates. The frame member includes a through-hole at the approximate center thereof and extends along a peripheral portion of the first major surface of the substrate body so as to define a frame shape. Each of the plurality of connection members has a first strip and a second strip continuously connected to opposed ends of a middle strip. The connection members are disposed in the frame member so as to face each other with the through-hole therebetween. Each of the first strip and the second strip of the connection member is exposed on a corresponding one of the two major surfaces extending around the through-hole of the frame member.
    Type: Application
    Filed: August 6, 2008
    Publication date: November 27, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Norio SAKAI, Mitsuyoshi NISHIDE
  • Publication number: 20080290884
    Abstract: This invention discloses a probe card assembly with adjustable ZIF connectors. The probe card assembly comprises a substrate, a plurality of ZIF connectors and a plurality of adjustable fastening means for assembling and disassembling the ZIF connectors on the substrate. The substrate is a disc-like plate, having a first surface, a second surface, a plurality of concave sections disposed on the second surface and a plurality of first through holes perpendicular to the first surface. The first through holes are circularly arranged toward the substrate center. Pairs of first contacts are provided on the first surface adjacent to both sides of first through holes. A plurality of terminals are protruded from the second surface of the substrate for contacting and testing the wafer. The ZIF connectors are also circularly arranged toward the substrate center.
    Type: Application
    Filed: August 13, 2007
    Publication date: November 27, 2008
    Inventor: Yuan-Chi Lin
  • Patent number: 7456646
    Abstract: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: November 25, 2008
    Assignee: Cascade Microtech, Inc.
    Inventors: Leonard Hayden, John Martin, Mike Andrews
  • Publication number: 20080285251
    Abstract: A packaging substrate with fiat bumps for an electronic device and a method of manufacturing the same relate to the production of the packaging substrate for an electronic device, which comprises base islands and pins structurally and wherein the base islands and pins which all exhibit flat bump shape distribute on the front face of the substrate; the bottom side of the bumps, namely the rear faces of the base islands and pins are contiguous in the same substrate; in the packaging body of a single electronic device to be formed in later procedure, one or more base island may be included, the pins may arrange on one single side of the base island, also may arrange on the both sides or three sides of the base island, or may surround the base island so as to form the structure of one or more circuits of pins.
    Type: Application
    Filed: April 6, 2006
    Publication date: November 20, 2008
    Applicant: Jiangsu Changiang Electronics Technology Co., Ltd.
    Inventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang
  • Patent number: 7448129
    Abstract: A peel-off device for an electronic-part delivery system has a front end portion and a recess that is indented inwardly from the front end portion, that is formed through upper and lower surfaces of the front end portion and that has a width larger than that of an electronic part of predetermined specification.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: November 11, 2008
    Assignee: Asustek Computer, Inc.
    Inventors: Cheng-Wei Chiu, Kuo-Chou Cheng, Chin-Chan Chen, En-Hsien Lee, Wei-Sheng Hung
  • Publication number: 20080266828
    Abstract: A lead frame has multiple regions having different wetting characteristics on its surface. For example, one region is formed to handle silver plating while another has less wetting ability. A boundary between the regions causes a wetting force difference that inhibits molten solder flow between regions during solder die bonding.
    Type: Application
    Filed: March 24, 2008
    Publication date: October 30, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xuesong XU, Meijiang Song, Jinzhong Yao
  • Publication number: 20080258276
    Abstract: A method to assemble a non-leaded semiconductor package (1) comprises the following steps. A carrier tape (13) is attached to a metal foil (12). A plurality of leadframes (3) is formed in the metal foil (12), each leadframe (3) comprising a die pad (4) laterally surrounded by a plurality of contact leads (5). A semiconductor die (2), including an active surface with a plurality of die contact pads (7), is attached to each die attach pad (4) and electrically connected to the leadframe (3) by a plurality of bond wires (9) connecting the die contact pads (7) and the lead contact areas (6) of the contact leads (5). A plurality of leadframes (3), each including a wire bonded semiconductor die, are encapsulated with mold material (10). The carrier tape (13) is removed and the non-leaded semiconductor packages (1) separated.
    Type: Application
    Filed: February 26, 2004
    Publication date: October 23, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Min Wee Low, Tian Siang Yip
  • Publication number: 20080244901
    Abstract: Positioning marks are formed on both sides of each printing block on a tape carrier for TAB. A long-sized circuit board is transported by a roll-to-roll system in screen printing. When an optical sensor detects a positioning mark, transportation of the long-sized circuit board is stopped. Thereafter, the screen printing of a solder resist is performed to the printing block of the long-sized circuit board by a screen printing device.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Applicant: NITTO DENKO CORPORATION
    Inventor: Makoto TSUNEKAWA
  • Patent number: 7425470
    Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: September 16, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Neo Chee Peng, Tan Hock Chuan, Chew Beng Chye, David Chai Yih Ming, Michael Tan Kian Shing
  • Publication number: 20080198568
    Abstract: An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a distal end. The proximal end has a second thickness less than the first thickness. The distal end is disposed between the first and second inner surfaces. The distal end is undulated such that the distal end has an effective thickness greater than the second thickness.
    Type: Application
    Filed: April 24, 2008
    Publication date: August 21, 2008
    Inventors: Roger A. Mock, Erich W. Gerbsch
  • Publication number: 20080189931
    Abstract: The present invention uses a frame with one or more axial ribs extending from a spine onto which two or more discrete two-terminal electronic components, such as capacitors, resistors, or inductors, can be attached. The function of the frame is to align and space the electronic components in a single device or array that allows the two-terminals of each component to be separately contacted or soldered to a PC board during final assembly into a circuit. The frame may use friction or a bonding agent to hold the components to the frame. Additionally, the base of the frame forms a single surface for the pick and place equipment used in circuit board assembly. The frame and any bonding agent must be capable of sustaining high temperature soldering operations to form electrical contacts in the circuit assembly operation.
    Type: Application
    Filed: April 22, 2008
    Publication date: August 14, 2008
    Applicant: VISHAY VITRAMON INC.
    Inventor: JOHN BULTITUDE
  • Publication number: 20080182434
    Abstract: An electronics package is described in which a quad flat no lead (QFN) electronic package has top and bottom surfaces. The bottom surface includes bottom contact pads arranged in a first pattern for electrical connection to corresponding package contact pads of an underlying circuit structure. The top surface includes top contact pads arranged in a second pattern for electrical connection to corresponding bottom contact pads of an overlying electronic package.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 31, 2008
    Applicant: ANALOG DEVICES, INC.
    Inventor: Thomas M. Goida
  • Patent number: 7405467
    Abstract: A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Cyntec Co., Ltd.
    Inventors: Chun-Tiao Liu, Da-Jung Chen, Chun-Liang Lin, Jeng-Jen Li, Cheng Chieh Hsu, Chau Chun Wen
  • Publication number: 20080174981
    Abstract: A lead frame and a method of manufacturing said lead frame is provided wherein a base material with first and second planar sides is first selectively etched from the first side thereof to a predetermined etching level to create etched areas. The etched areas on the first side of the said base material are then filled with a filling compound and thereafter, the base material is etched from the second side to the etching level to expose the filling compound on the second side.
    Type: Application
    Filed: July 6, 2007
    Publication date: July 24, 2008
    Inventors: Say Teow CHAN, Yue Gen YU, Hong GU, Dawei XING, Yun ZHAO
  • Publication number: 20080172860
    Abstract: A small radio frequency IC tag which can obtain sufficiently long communication distance with radio wave in the microwave band even if an antenna is made small and the radio frequency IC tag is embedded in metal material. An O-shaped antenna is formed to narrow the width of a neck part in which an IC chip is mounted and widen the width of radiating electrodes constituting radiating part of radio wave. The radiating electrodes are formed into offset structure on right and left sides of the feeding point so that areas of right and left radiating parts of the feeding point in which the IC chip is mounted are unsymmetrical. Further, a ground electrode is provided so that a dielectric body is held between the radiating electrodes and the ground electrode and the radiating electrode is connected to the ground electrode at the side of the dielectric body.
    Type: Application
    Filed: March 13, 2008
    Publication date: July 24, 2008
    Inventors: Isao Sakama, Minoru Ashizawa
  • Publication number: 20080158846
    Abstract: The present invention describes a pre-fabricated chip mount and a method for making the pre-fabricated mount. The mount includes a mount body and a protective ring attached to the body by a plurality of tabs. The mount also includes a plurality of inner leads in electrical communication with the wires of at least one leadframe and a receiving area for an integrated circuit chip. The present invention also describes chips mounted on the pre-fabricated mount and methods for mounting, wire-bonding and encapsulating the chip in the mount. The mounts of the present invention can also be adapted to accommodate multiple chips and multi-level bonding schemes to the chips.
    Type: Application
    Filed: March 4, 2008
    Publication date: July 3, 2008
    Inventor: Robert A. Martin
  • Publication number: 20080157309
    Abstract: A lead frame includes a lead frame main body having a plurality of die pad portions each having a chip mounting surface on which a semiconductor chip is mounted, a plurality of lead portions provided to surround the plurality of die pad portions respectively, and a frame portion for supporting the plurality of die pad portions and the plurality of lead portions, an adhesive film pasted on a lower surface of the lead frame main body by pressing, and a first metal film provided on surfaces of the plurality of lead portions and connected electrically to the semiconductor chip respectively, wherein second metal films whose thickness is substantially equal to a thickness of the first metal film are provided to the chip mounting surface of the plurality of die pad portions respectively.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 3, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Akinobu Hojo
  • Publication number: 20080122048
    Abstract: A stamped leadframe for a leadless package and a method of manufacturing the same are provided wherein the leadframe has at least a die pad, a frame, tie bars connecting the die pad to the frame and a plurality of leads. Each lead comprises a first portion and a second portion, and the second portion is connected substantially parallel to and displaced relative to the first portion by a distance that is less than the thickness of the first portion. Portions of the tie-bars and/or die pad may be similarly displaced.
    Type: Application
    Filed: August 25, 2006
    Publication date: May 29, 2008
    Inventors: Tat Chi Chan, Man Shing Cheng
  • Patent number: 7370414
    Abstract: Methods of manufacturing lead frame connectors for use in connecting optical sub-assemblies to printed circuit boards in optical transceiver modules. The lead frame connectors are formed by first stamping a selected configuration of conductors in a conductive ribbon. The conductors are bent as necessary and passed in a reel-to-reel manner through an insert injection molding process to form an electrically insulating casing about the conductors. After the molding process, the ribbon is singulated to obtain individual lead frame connectors. The individual conductors encased in the casing can be electrically separated by punching out a connecting conductive structure through a hole formed in the casing. The connecting conductive structure mechanically secures the conductors to each other during the molding process and, when punched out, substantially eliminate stubs that could otherwise degrade the RF performance of the lead frame connectors.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: May 13, 2008
    Assignee: Finisar Corporation
    Inventor: Donald A. Ice
  • Patent number: 7367119
    Abstract: Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon thereby defining a cantilever structure, depositing a second metal layer at least partially over the first metal layer, and at least partially over a cone structure of the silicon to define the tip structure. The silicon can then be removed from beneath the cantilever and from within the deposited second metal layer by etching, thereby leaving a low-mass metal tip associated with a metal cantilever. An alternative embodiment, the silicon can be removed from beneath the cantilever by etching, but endpointed such that at least a portion of the cone structure remains beneath the second metal layer. The silicon/metal tip can have good wear characteristics and a slightly higher mass.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: May 6, 2008
    Assignee: Nanochip, Inc.
    Inventor: Nickolai Belov
  • Patent number: 7367120
    Abstract: A method of manufacturing a solid-state imaging device. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element. The wirings are made of thin metal plate leads, the base is made up of a resin molded member in which the thin metal plate leads are embedded, and at least a part of a side edge face of the thin metal plate leads is embedded in the base. The rigidity of the base is enhanced by the thin metal plate leads, thus reducing a curl and a warp of the base.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 6, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Mutsuo Tsuji, Kouichi Yamauchi
  • Patent number: 7363704
    Abstract: A method of manufacturing an RFID tag includes forming through-holes on a sheet to embed a plurality of electronic components, such as IC chips; forming a substrate by sticking a bottom plate sheet to the sheet, and forming recesses; embedding the electronic components into the recesses; printing antenna patterns on the substrate such that the antenna patterns are connected to electrodes of the electronic components; covering the substrate with a cover sheet; and a slitting step of cutting out individual RFID tags.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kobayashi, Naoki Ishikawa, Takatoyo Yamakami, Masumi Katayama, Syunji Baba
  • Publication number: 20080083973
    Abstract: There is provided a lead frame for an optical semiconductor device, an optical semiconductor device using such lead frame, and a manufacturing method for these, where the optical semiconductor device exhibits favorable brightness over a long period of time by preventing discoloration and degeneration of a plating layer provide on the lead frame and a resulting reduction in a reflection coefficient for light emitted from a light emitting element, even when using silicone resin as a sealing resin. An Ag—Au alloy plating layer 22 is formed on the surface of a pure Ag plating layer 21 on a lead frame 10 sealed chloroplatinic acid-containing silicon resin, so as to prevent direct contact between the layer 21 and the silicone resin. This suppresses the formation of AgCl due to a reaction with a hardening catalyst of the silicon resin, thereby preventing the Ag plating layer from turning a blackish-brown color.
    Type: Application
    Filed: March 7, 2007
    Publication date: April 10, 2008
    Inventors: Tomoyuki Yamada, Tomohiro Futagami, Keishiro Kawano
  • Patent number: 7354804
    Abstract: A method of fabricating a lead frame for a semiconductor device. The lead frame has a lead electrically connected to a semiconductor chip within sealing resin and sealed into the sealing resin such that at least a part of its lower surface is exposed from a lower surface of the sealing resin. The method includes a punching step for forming the lead by punching processing in a direction from the lower surface to its upper surface and a coining step for subjecting the lead to coining processing from the side of the upper surface after the punching processing.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: April 8, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Ichiro Kishimoto
  • Patent number: 7350293
    Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Kazuaki Ano