Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Patent number: 7346976
    Abstract: The method for manufacturing a suspension for disc drive includes a process for manufacturing a semi-finished suspension product integrally including a base plate, a rigid body portion of a load beam, and a pair of connecting portions connecting the base plate and the rigid body portion. The method also includes a process for fixing a spring member, formed independently of the semi-finished suspension product, to the base plate and the rigid body portion of the semi-finished product, and a process for cutting off the connecting portions, projecting individually from the opposite sides of the spring member, from the base plate and the rigid body portion after the spring member is fixed to the semi-finished suspension product.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 25, 2008
    Assignee: NHK Spring Co., Ltd.
    Inventors: Yasuji Takagi, Koji Uozumi, Masao Hanya, Noriyuki Saito
  • Patent number: 7339262
    Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Dae-Woo Son, Sa-Yoon Kang, Kwan-Jai Lee
  • Patent number: 7308752
    Abstract: An optical pickup apparatus is described which includes a movable unit with an objective lens, a focus servo coil for moving the moveable unit containing the objective lens in the optical-axis direction, and tracking servo coils for moving the moveable unit containing the objective lens in the horizontal directions, and a liquid crystal element disposed for correcting the refractive index. Springs simultaneously provide support for the moveable unit and feed power to the liquid crystal element, the focus servo coil, and the tracking servo coils. A method for making said optical pickup apparatus is described. Two sheets, each having four springs extending across an opening formed by punching, are disposed parallel to each other at a predetermined distance. On these sheets, a fixed unit and a movable unit are formed by insert-molding. Excess portions of the metal sheets are removed, and a through-hole is formed so that connected portions of the wirings, lying side by side, are disconnected.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: December 18, 2007
    Assignee: Sony Corporation
    Inventor: Tetsu Tanaka
  • Publication number: 20070271777
    Abstract: An apparatus, system, and method are disclosed for maintaining orientation of a manufactured part during a manufacturing process. The apparatus, system, and method include uncoiling a carrier from at least one supply reel and feeding the carrier into a manufacturing machine used by a manufacturing process to form a manufactured part. The apparatus, system, and method include forming the manufactured part onto at least one prong protruding from the carrier. The at least one prong and the carrier maintain orientation of the manufactured part with respect to the carrier.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 29, 2007
    Inventors: Bart J. Storrs, Michael A. Griffin
  • Patent number: 7299546
    Abstract: An electronic module and a method for manufacturing an electronic module, in which an installation base is used, which includes an insulating-material layer (1) and a conductive layer on the surface of the insulating-material layer. The conductive layer also covers the installation cavity of a component (6). The component (6) is set in the installation cavity, in such a way that the contact zones face towards the conductive layer and electrical contacts are formed between the contact zones of the component (6) and the conductive layer. After this, conductive patterns (14) are formed from the conductive layer, to which the to which the component (6) is attached.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 27, 2007
    Assignee: Imbera Electronics OY
    Inventors: Risto Tuominen, Petteri Palm
  • Patent number: 7299544
    Abstract: Disclosed is an apparatus for separating culls coupled to a lead frame when a semiconductor chip is molded. The apparatus includes a lower plate, on which culls coupled to a lead frame are placed, an upper plate pressing culls placed on the lower plate in order to separate culls from the lead frame, a pilot pin installed in the upper plate by passing through the upper plate in order to press culls together with the upper plate when the upper plate presses the culls, and a sensor unit installed adjacent to the movement path of the pilot pin so as to detect a movement of the pilot pin. When culls are separated, faults of articles caused by a molding material insufficiently filled in a mold are checked through detecting a movement of the pilot pin.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: November 27, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Su Gueon Lee
  • Publication number: 20070257377
    Abstract: A package structure including a first carrier, a second carrier, at least a first electronic component and at least a second electronic component is provided. The second carrier is electrically connected to the first carrier. The first electronic component is disposed on the first carrier and electrically connected to the first carrier. The second electronic component is disposed on the second carrier and electrically connected to the second carrier.
    Type: Application
    Filed: July 7, 2006
    Publication date: November 8, 2007
    Inventors: Da-Jung Chen, Yi-Cheng Lin, Bau-Ru Lu, Yi-Min Fang, Chau-Chun Wen, Chun-Tiao Liu
  • Patent number: 7278202
    Abstract: A surface mount resistor includes an elongated piece of resistive material having strips of conductive material attached to its opposite ends. The strips of conductive material are separated to create an exposed central portion of the resistive material therebetween. According to the method the resistive strip is attached to a single co extensive strip of conductive material and a central portion of the conductive material is removed to create the exposed central portion of the resistive strip.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 9, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Joel J. Smejkal, Steve E. Hendricks
  • Publication number: 20070193027
    Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.
    Type: Application
    Filed: January 11, 2007
    Publication date: August 23, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
  • Patent number: 7247520
    Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: July 24, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7237724
    Abstract: A smart card and a method for manufacturing the same wherein the smart card is composed of a printed circuit board, having a top surface and a bottom surface, a plurality of circuit components attached to the top surface of the printed circuit board, a filler board, attached to the top surface of the printed circuit board, a bottom overlay attached to the bottom surface of the printed circuit board, a top overlay positioned above the top surface of the printed circuit board and a thermosetting polymeric layer positioned between the top surface of the printed circuit board and the top overlay.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: July 3, 2007
    Inventor: Robert Singleton
  • Patent number: 7234231
    Abstract: A manufacturing method of an optical coupling device includes, preparing an elongated lead frame on which a plurality of tie bars are placed between a pair of side rails that are mutually in parallel with each other so as to orthogonally cross the tie bars, with a plurality of lead terminals being placed in a staggered form in a manner so as to orthogonally cross the tie bars, and laterally cutting the elongated lead frame to prepare a plurality of strap-shaped lead frames, in such a manner that the length of protrusion of a cut end of each of the side rails from each of the tie bars is made longer than the length of protrusion of a lead terminal from each of the tie bars.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: June 26, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideya Takakura, Kazuo Kusuda, Hiroyuki Shoji
  • Patent number: 7230829
    Abstract: An overmolded electronic assembly includes a substrate, a plurality of surface mount technology (SMT) integrated circuit (IC) chips, a plurality of heat sinks, a backplate and an overmold material. The substrate includes a plurality of conductive traces formed on a first surface of the substrate. The IC chips each include an active front side and a backside and the IC chips are electrically coupled to one or more of the traces. The heat sinks are each in thermal contact with the backside of a different one of the IC chips and are independent of each other. The backplate is attached to a second surface of the substrate, which is opposite the first surface of the substrate. The overmold material covers the first surface of the substrate and maintains the heat sinks in thermal contact with an associated one of the IC chips.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: June 12, 2007
    Assignee: Delphi Technologies, Inc.
    Inventors: Larry M Mandel, David A. Laudick
  • Patent number: 7228622
    Abstract: A method and machine-readable medium are described for a flexible tape constructed of a material suitable to convey electronic devices through an entire manufacturing process without removing the electronic packages from the tape. According to one embodiment, part receiving areas are located within the tape. Each part receiving area is suitable to hold an electronic device. A retention channel encompasses each part receiving area. The retention channel extends substantially an entire length along each edge of each part receiving area. The retention channel comprises an upper tab and a lower tab wherein the upper tab is flush with an upper surface of the flexible tape and extends into the part receiving area and the lower tab extends below a lower surface of the flexible tape and into the part receiving area.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventor: Jeffrey Watson
  • Patent number: 7225537
    Abstract: Memory Cards containing Integrated Circuits and other electronic components (e.g. resistors) in a variety of form factors having high quality external surfaces of polycarbonate, synthetic paper (e.g. Teslin), or other suitable material (e.g. PVC) can be made through use of injection molded thermoplastic material or thermosetting material that becomes the core layer of said Memory Cards and similar devices. The object of the invention is to provide the following properties to Memory Cards: rapid production cycle, high volume manufacturing throughput, security, electronics protection, better tamper resistance, durability, and highly reliable complex electronics encapsulation, achieved through a process utilizing low temperature and low pressure.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: June 5, 2007
    Assignee: Cardxx, Inc.
    Inventor: Paul Reed
  • Patent number: 7219421
    Abstract: A coated heat spreader for a die includes a body and a coating on a surface of the body, wherein the outermost coating is an organic surface protectant. An IC package includes a die thermally coupled to a heat spreader coated with an organic surface protectant. A PCB assembly including a die thermally coupled to a heat spreader coated with an organic surface protectant, where the die is part of an IC package or is directly attached to the PCB. A method of making a coated heat spreader includes coating the organic surface protectant onto a surface of the heat spreader.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Joan K. Vrtis, Joni G. Hansen, Thomas J. Fitzgerald, Carl L. Deppisch
  • Patent number: 7204017
    Abstract: A manufacturing method of a modularized leadframe, using a first mold set to contact and hold the upper surface of rows of multiple block leads, using a second mold set to contact and hold at least one selected surface of the lower surface of leads, the second mold set has a protruding part between each row of leads so that the upper surface of the protruding part be in close contact with the inner surface of the first mold set. The hollow space between the mold sets is then injected with packaging materials such that a leadframe structure having packaged and fixed leads therein and surfaces for wire-bonding and soldering is obtained. A packaging material filling space is formed in the leadframe after removing the first and the second mold sets.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: April 17, 2007
    Assignee: Optimum Care International Tech. Inc.
    Inventors: Jeffrey Lien, Shihlin Chang
  • Patent number: 7204010
    Abstract: A load sensor plate (100) is adapted for manufacture by stamping spaced apart openings (110) through a thin blank to define flexure beams (112) beside the openings (110); and forming the blank with spaced apart columnar walls (102), (106) joined by a web (104) having the openings (110) and the flexure beams (112) whereby, an applied load (116) exerted on one of the columnar walls (102) is distributed among the flexure beams (12), and another of the columnar walls (106) bears an opposing force (118) that resists the applied load (118).
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: April 17, 2007
    Assignee: Measurement Specialties, Inc.
    Inventor: Damon Germanton
  • Patent number: 7185425
    Abstract: By forming a terminal at a tip of a lead part of a lead frame, and by fixing this terminal and a connecting pad which was formed on an upper surface of a first printed circuit board, the lead frame is attached to the first printed circuit board. By cutting off a frame part and a tie bar part from the lead frame which was attached to the first printed circuit board, the lead part is separated, and forming is applied to the lead part so as for its tip to be extended over the first printed board. After the lead part which is expanded upward is inserted into a through-hole which was opened in a second printed circuit board, by soldering the lead part and the through-hole, the first printed circuit board and the second printed circuit board are electrically connected.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: March 6, 2007
    Assignees: Fujitsu Ten Limited, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takashi Ohta, Kazuaki Yamada, Kiyoshi Tsujii, Hidekazu Manabe
  • Patent number: 7181835
    Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: February 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
  • Patent number: 7174627
    Abstract: A known good die is economically fabricated. A tested integrated circuit is provided which includes a die having a bonding location on an upper surface and a lead. An upper portion of the integrated circuit package is removed or ground away to expose the bonding location. The lead is removed leaving the die and exposed bonding location to provide a known good die. The backside portion of the integrated circuit package is removed or ground away to expose the backside of the die. A contact pad is disposed on the bonding location. The bonding wire and exterior lead are also removed or ground away. The upper portion of the bonding ball is removed to provide a flattened bonding location. Preferably, the tested integrated circuit package provided is a thin small outline integrated circuit package (TSOP), and advantageously may be a packaged flash memory integrated circuit.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: February 13, 2007
    Assignee: Irvine Sensors Corporation
    Inventor: Keith D. Gann
  • Patent number: 7174626
    Abstract: A method of making a lead finish incorporating mechanically flattening the plated coating of metal leads. This may be accomplished by mechanical means such as rolling, stamping, peening, coining, forging, or other suitable flattening techniques.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: February 13, 2007
    Assignee: Intersil Americas, Inc.
    Inventors: Mark A. Kwoka, Jack H. Linn
  • Patent number: 7152316
    Abstract: To provide a hybrid integrated circuit device in which the rear surface of a circuit board is exposed to the outside and a method of manufacturing the same. Here, leads are fixed to the surface of the circuit board along one side thereof. A method of manufacturing a hybrid integrated circuit device includes the steps of forming an electric circuit which includes a conductive pattern formed on a surface of a circuit board and a circuit element electrically connected to the conductive pattern, fixing a lead to a pad formed of the conductive pattern, housing the circuit board in a cavity of molds, and fixedly supporting the lead by clamping the lead between the molds, and performing sealing by filling inside of the cavity with sealing resin with the rear surface of the circuit board made in contact with an inside bottom surface of the molds.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: December 26, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Haruhiko Mori, Masaru Kanakubo, Hideyuki Sakamoto
  • Patent number: 7134311
    Abstract: A device for fabricating a lead frame, by press forming, provided with a die having a flat face, on which a lead frame to be fabricated by press forming is to be placed, and a concavity, which is dented relative to the flat face, the die possessing a fabricating face extending from the bottom of the concavity to the flat face through a slant, which is interposed between the bottom of the concavity and the flat face, the fabricating face contributing the fabrication of a lead frame by press forming, and a punch having punching faces formed so as to be opposite to the fabricating faces of the die for the fabrication of the lead frame by press forming, at least one of the die and the punch being movable so as to hold the lead frame between the fabricating face of the die and the punching face of the punch for the fabrication of the lead frame by press forming, wherein the bottom of the concavity of the die has a bottom concavity formed therein, which is dented relative to the bottom, and the punch has a front en
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: November 14, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masahiro Iwabuchi
  • Patent number: 7131192
    Abstract: This invention is a method of manufacturing printed circuit boards using a contact block packaging to provide and support electrical contact blocks relative to a printed circuit board panel. The contact block packaging is situated adjacent to the printed circuit board panel, so that electrical contact blocks of the contact block packaging are aligned with circuit boards of the printed circuit board panel, but breakaway stems supporting the electrical contact blocks are offset from webbing of the printed circuit board panel. The electrical contact blocks are then soldered to the printed circuit boards. Thereafter, the breakaway stems of the contact block packaging and the webs of the printed circuit board panel are broken, so that the electronic contact blocks are decoupled from the rest of the contact block packaging and the printed circuit boards are decoupled from the rest of the printed circuit board panel.
    Type: Grant
    Filed: June 5, 2004
    Date of Patent: November 7, 2006
    Assignee: Motorola, Inc.
    Inventor: Robert Stanford
  • Patent number: 7132734
    Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: November 7, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7127805
    Abstract: A system and apparatus are described for a flexible tape constructed of a material suitable to convey electronic devices through an entire manufacturing process without removing the electronic packages from the tape. According to one embodiment, part receiving areas are located within the tape. Each part receiving area is suitable to hold an electronic device. A retention channel encompasses each part receiving area. The retention channel extends substantially an entire length along each edge of each part receiving area. The retention channel comprises an upper tab and a lower tab wherein the upper tab is flush with an upper surface of the flexible tape and extends into the part receiving area and the lower tab extends below a lower surface of the flexible tape and into the part receiving area.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventor: Jeffrey Watson
  • Patent number: 7127794
    Abstract: According to one embodiment of the invention, a method for auto-boating includes supporting a tape substrate having first and second end portions on a boat, sandwiching the first and second end portions between respective ones of a pair of end sleeves and the boat, coupling a boat clip to the boat, and removing the end sleeves from between the first and second end portions and the boat clip.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: October 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Gerald M. Cruz, Jerry G. Cayabyab, Edward R. De la Rosa
  • Patent number: 7117587
    Abstract: A method for fabricating a substrate, which includes a plurality of chip package substrates. One combined PCB includes a multi-layer rigid PCB and a soft PCB. The multi-layer rigid PCB is fixed on the soft PCB. At least one grooves or a pair is formed on an upper surface of the multi-layer rigid PCB. A portion of the multi-layer rigid PCB between the grooves is milled to expose a corresponding portion of the soft PCB to define an exposed area. The combined PCB is drilled through along two opposite sides of the grooves and the corresponding exposed area of the soft PCB. Breakable parts are formed at a center of the corresponding portion of the soft PCB and two opposite outside edges of the grooves.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: October 10, 2006
    Assignee: Lite-On Semiconductor Corp.
    Inventors: Huei-Jen Chen, Evan Liu, Yvon Chen
  • Patent number: 7114248
    Abstract: A method of handling an electrical component is disclosed. The method includes initiating a first engagement between the electrical component and a conveyor, initiating a second engagement between a tool and the electrical component without altering the first engagement, and performing a tooling operation on the electrical component with the tool.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Morley J. Weyerman
  • Patent number: 7112252
    Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Timothy J. Allen, Jerry M. Brooks
  • Patent number: 7107671
    Abstract: A method of processing a strip of lead frames is disclosed. The method includes engaging the strip with a lead frame advancement system, advancing the strip to a tooling member, and performing a tooling operation on the strip.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: September 19, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Morley J. Weyerman
  • Patent number: 7103969
    Abstract: The described embodiments relate to methods and systems for forming die packages. In one exemplary embodiment, the method for forming die packages contacts interface areas of a die assembly to keep the interface areas free of an insulative material. The method distributes a flowable insulative material around portions of the die assembly.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Frank J. Bretl, Gary Powell, Donald L. Michael, Jefferson P. Ward, Joseph E. Scheffelin, Mohammad Akhavain
  • Patent number: 7094619
    Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Komoto, Toshiaki Tanaka, Norio Fujimura
  • Patent number: 7082681
    Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. The stub contacts may be formed by trimming the leads of an existing vertical surface mount package. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: August 1, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Walter L. Moden, Warren M. Farnworth
  • Patent number: 7082678
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a first end to a second end such that a portion of each lead exhibits a generally arcuate shape. The first end may be coupled with a printed circuit board and the second end may be coupled with a semiconductor die. The generally arcuately shaped portion of the leads may include a portion which exhibits a constant radius. The generally arcuately shaped portion may also be formed from a plurality of conductor segments including, for example, at least one generally arcuately shaped segment. The semiconductor die and at least a portion of the leads may be encapsulated with an insulating material.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: August 1, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ronnie M. Harrison, David J. Corisis
  • Patent number: 7069653
    Abstract: A method of establishing an electric connection between electric terminals of a semiconductor component as part of an electric module and additional parts of the electric module by using a punched grid having internal terminal ends and external terminal ends that are electrically connected to the internal terminal ends by metal strip conductors, the semiconductor component and the punched grid are joined so that at least two electric terminals of the semiconductor component are positioned on corresponding internal terminal ends so that a slip-proof mounting of the semiconductor component on the two internal terminal ends is then possible, this mechanical mounting at the same time establishing an electric connection between the electric terminals of the semiconductor component and the internal terminal ends, whereby a metal strip grid, e.g.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: July 4, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Rainer Topp, Dirk Balszunat, Stephan Ernst, Achim Henkel, Doerte Eimers-Klose, Reinhard Milich
  • Patent number: 7064420
    Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: June 20, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Byung Joon Han, Byung Hoon Ahn, Zheng Zheng
  • Patent number: 7059042
    Abstract: A sheet-like thermally conductive resin composition containing 70 to 95 wt. % inorganic filler and 5 to 30 wt. % thermosetting resin composition, a lead frame as a wiring pattern, and an electrically conductive heat sink with a metal pole placed therein are superposed, heated and compressed, and thus are combined to form one body. Consequently, a thermally conductive circuit board with a flat surface is obtained in which a grounding pattern is grounded to the heat sink inside the insulating layer. Thus, the grounding pattern and the heat sink can be connected electrically with each other in an arbitrary position inside the insulating layer of the thermally conductive circuit board. Accordingly, there are provided a thermally conductive circuit board with high heat dissipation, high conductivity and high ground-connection reliability, a method of manufacturing the same, and a power module allowing its size to be reduced and its density to be increased.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo, Yoshihisa Yamashita
  • Patent number: 7056448
    Abstract: A method for forming a circuit pattern includes at least a step (a) of subjecting a non-conductor to electroless copper plating to form a copper film and a step (b) of etching the copper film so as to form a circuit pattern. As a catalyst for the electroless copper plating, a silver colloidal solution is used containing as essential components at least the following: (I) silver colloidal particles; (II) one or more of ions of metal having an electric potential which can reduce silver ions to metal silver in the solution and/or ions which result from oxidation of the ion at the time of reduction of the silver ions; and (III) one or more of hydroxycarboxylate, condensed phosphate and/or amine carboxylate ions. The silver colloidal particles (I) are produced by the ion (II) of the metal having an electric potential which can reduce silver ions to metal silver. The circuit pattern may be formed on a printed wiring board.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: June 6, 2006
    Assignee: Daiwa Fine Chemicals Co., Ltd.
    Inventors: Yoshiaki Okuhama, Keigo Obata, Masakazu Yoshimoto, Shingo Kitamura, Seiichiro Nakao, Osamu Masuyama, Hidenori Tsuji
  • Patent number: 7056769
    Abstract: The existing IC cards have a disadvantage of difficulty of mass production because an IC chip is supplied on a substrate one at a time. The present invention provides a method of manufacturing by placing a positioning jig having a plurality of openings each of which has a size fit with a semiconductor device, providing a plurality of semiconductor devices on said jig to house the devices into the openings, and fixing on a substrate then cutting the substrate to provide independent electronic devices. When the semiconductor device is in a form of chip, a support member attached to the chip will facilitate the handling of chips.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: June 6, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 7055241
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a first end to a second end such that a portion of each lead exhibits a generally arcuate shape. The first end may be coupled with a printed circuit board and the second end may be coupled with a semiconductor die. The generally arcuately shaped portion of the leads may include a portion which exhibits a constant radius. The generally arcuately shaped portion may also be formed from a plurality of conductor segments including, for example, at least one generally arcuately shaped segment. The semiconductor die and at least a portion of the leads may be encapsulated with an insulating material.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: June 6, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ronnie M. Harrison, David J. Corisis
  • Patent number: 7051428
    Abstract: A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit supplies one of the pre-cut dicing tape and the general dicing tape and attaches it to a wafer according to the direction of rotation of a tape loader. Accordingly, without an additional pre-cut dicing tape attaching unit, either of the pre-cut dicing tape and the general dicing tape can be attached to the back side of the wafer by one and the same unit.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Kwon Jeong, Dong-Kuk Kim
  • Patent number: 7043831
    Abstract: A method for fabricating an interconnect for semiconductor components includes the steps of: providing a substrate; forming a metal layer on the substrate; etching projections in the metal layer; etching the metal layer to form patterns of leads; etching recesses in the substrate to cantilever the leads and form contacts for electrically engaging bumped contacts on a component; and then forming conductors to the leads. With the substrate comprising silicon, insulating layers can also be formed on the substrate, and within the recesses, for electrically insulating the leads and the conductors. With the conductors formed on a same surface of the substrate as the contacts, the same etching process can be used to form the conductors and the leads.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram
  • Patent number: 7032290
    Abstract: A brush holder incorporates a terminal integral part, which has a coupling portion. The coupling portion couples the terminals with each other. The brush holder has a resin body and a plurality of terminals. The resin body has an opening. The terminals are embedded in the resin body. The terminals are coupled to each other by the coupling portion as an integral part before being embedded in the resin body. The coupling portion is exposed from the opening of the resin body. The terminals are separated from each other by cutting the coupling portion, which is exposed from the opening of the resin body. A coating member coats the opening of the resin body to insulate each terminal.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: April 25, 2006
    Assignee: ASMO Co., Ltd.
    Inventors: Yoshinobu Hirano, Kenji Obata, Masakuni Masuda
  • Patent number: 7028397
    Abstract: A semiconductor chip, substrate employing plural bonding steps to ensure complete bonding particularly of peripheral edges. Embodiments include placing an adhesive layer on a chip mounting substrate positioned on a first supporting device, pressing a semiconductor chip against the chip mounting substrate to bond the semiconductor chip temporarily to the chip mounting substrate temporarily bonded chip on a second supporting device, and applying chip to straighten warpage and to bond the chip entirely to the chip mounting substrate.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: April 18, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shunichi Abe, Tetsuya Uebayashi, Naoki Izumi, Akira Yamazaki
  • Patent number: 7024765
    Abstract: A method of manufacturing a surface-emitting backlight is provided with the steps of forming a lead frame and resin-made molded case by insert molding, attaching light sources, which are red, blue and green LED dies, to contacts of the lead frame provided in a hollow space of the molded case, forming a light guide section by filling the hollow space with a transparent or semitransparent resin, and thereafter attaching a reflector sheet, and lens sheets (or diffuser sheets) in accordance with the applications of the backlight.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: April 11, 2006
    Assignee: Ryoden Trading Company, Limited
    Inventor: Yasufumi Sakakibara
  • Patent number: 7013559
    Abstract: The present invention features a novel design for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: March 21, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7012321
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 14, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Patent number: 6996897
    Abstract: method for making a mount for at least two electronic devices forming a first mounting surface (210) from a material (240), and forming a second mounting surface (220) from the material (240). The first mounting surface (210) is connected to, but spaced from, the second mounting surface (220) by a mounting surface distance (250). The method further comprises reducing the mounting surface distance (250).
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: February 14, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Frank J. Mosna, Jr., Alexander J. Elliott, William M. Strom