Assembling Bases Patents (Class 29/830)
  • Patent number: 10283492
    Abstract: Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 7, 2019
    Assignee: Invensas Corporation
    Inventor: Nader Gamini
  • Patent number: 10274998
    Abstract: The invention relates to a holding component with a riser card for receiving an expansion component for a computer system. The riser card comprises a first mating plug connector on a first side of a bottom plate of the holding component. Further, the riser card comprises a first plug connector on a second side of the bottom plate opposite the first side. The holding component is adapted to receive the expansion component by establishing a plug connection of a second plug connector of the expansion component and the first mating plug connector on the holding component, wherein the holding component comprises a slot bracket, which is adapted to receive a slot angle of the expansion component. Furthermore, the invention relates to a support component for receiving at least one holding component and to an assembly comprising a chassis of a server module and of a holding component as well as of a support component.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Ronny Hesse
  • Patent number: 10256117
    Abstract: There is provided a method for manufacturing a wiring substrate with a through electrode, the method including providing a device substrate having a through hole, an opening of the through hole being blocked by a current supply path and the wiring substrate including the device substrate as a core layer with the through electrode; and disposing a first metal in the through hole to form the through electrode by electroplating, in a depth direction of the through hole, using the current supply path.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Sony Corporation
    Inventors: Shun Mitarai, Shusaku Yanagawa, Hiroshi Ozaki
  • Patent number: 10231345
    Abstract: Embodiments of the present invention provide an attachment apparatus and an attachment method for a conductive adhesive. The attachment apparatus includes: a carrier stage, which is provided with at least one working surface, the working surface being configured to support a printed circuit board and provided with a groove, and the groove being provided with a plurality of adsorption holes on its bottom surface; a vacuum adsorption device being connected to each of the plurality of adsorption holes; and an attaching mechanism provided above the carrier stage, and configured to attach the conductive adhesive to a predetermined region of the printed circuit board, and the predetermined region being a region of the printed circuit board to be squeeze connected to a flexible printed circuit board or a chip on film.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hanwei Tu, Minghui Liu, Hongjie Ding, Xikui Hao, Pengcheng Wang
  • Patent number: 10219374
    Abstract: A printed wiring board includes a first insulating layer, a second conductor layer including first and second circuits, a second insulating layer covering the second conductor layer on the first insulating layer, a third conductor layer including first and second circuits, a third insulating layer covering the third conductor layer on the second insulating layer, a fourth conductor layer including first circuit, a second via conductor connecting the first circuits in the second and third conductor layers through the second insulating layer, and a first skip via conductor penetrating through the second circuit in the third conductor layer and connecting the second circuit in the second conductor layer and the first circuit in the fourth conductor layer through the second and third insulating layers. The second and third conductor layers are formed such that the second conductor layer has thickness t2 larger than thickness t3 of the third conductor layer.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 26, 2019
    Assignee: IBIDEN CO., LTD.
    Inventor: Teruyuki Ishihara
  • Patent number: 10212836
    Abstract: One aspect relates to an electrical bushing for a medically implantable device, including an electrically insulating base body and an electrical conducting element. The conducting element includes a cermet, and the base body and the conducting element are connected by a sintered bond with a hermetic seal against the base body. The conducting element extends from a first surface of the base body through the base body to a second surface of the base body. The conducting element has first and second electrically conductive areas, and at least one of the electrically conductive areas is at least partially superimposed by a layer-like contact element, including a metal, so that the conducting element is connected in an electroconductive manner via the contact element. The contact element is an electrochemically created layer, such that it has a porous structure, wherein the porosity of the contact element is not more than 20%.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 19, 2019
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Robert Dittmer, Frank Krüger
  • Patent number: 10123411
    Abstract: A printed wiring board includes an insulating sheet, a conductive layer formed on one main surface of the insulating sheet, and an insulating film laminated with an adhesive layer on the main surface of the insulating sheet formed with the conductive layer. The position of an end part of the insulating film is located outside the position of an end part of the adhesive layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 6, 2018
    Assignee: FUJIKURA LTD.
    Inventor: Kazutoshi Matsumura
  • Patent number: 10096491
    Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 9, 2018
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Wei-Chung Hsiao, Ming-Chen Sun, Liang-Yi Hung
  • Patent number: 10088877
    Abstract: A board card module including a case, a main board, and an expansion card is provided. The case has an accommodating space. The main board is fixed to the case and located in the accommodating space. The main board has a connecting port. The expansion card is detachably pivoted to the case and located in the accommodating space. The expansion card has a terminal set and the expansion card is rotatable relative to the case to insert the terminal set into or separate the terminal set from the connecting port.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 2, 2018
    Assignee: Wistron Corporation
    Inventors: Fu-Lung Lu, Cheng-An Lu
  • Patent number: 10034393
    Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Douglas A. Baska, Daniel M. Dreps, Rohan U. Mandrekar, Roger D. Weekly
  • Patent number: 9958909
    Abstract: A housing design and method of providing electromagnetic compatibility (EMC) by mitigating a slot antenna in a corner region of a housing, the corner profile including an electrically conductive insert that has a spring bias, such as a spring or coated plastic member, in a corner of the housing.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 1, 2018
    Assignee: General Electric Company
    Inventors: Bernd Sporer, Klaus Weinmann, Oleg Schneider
  • Patent number: 9942976
    Abstract: A boss-type metal-based sandwich rigid-flex board and preparation method thereof are disclosed. The boss-type metal-based sandwich rigid-flex board comprises a rigid sub-plate, a flexible sub-plate, a dielectric layer, and a metal core layer, wherein the metal core layer has front and back sides on which at least one metal boss and at least one heat dissipation area are arranged respectively, the dielectric layer, and the rigid sub-plate and/or the flexible sub-plate are sequentially stacked on the front and back sides of the metal core layer respectively, and each of the rigid sub-plate, the flexible sub-plate and the dielectric layer is provided with a first window area fit with the metal boss, and a second window area corresponding to the heat dissipation area. The boss-type metal-based sandwich rigid-flex board (with a metal boss and a heat dissipation area arranged on the front side) prepared according to the present disclosure uses a metal core layer for heat dissipation.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 10, 2018
    Assignees: Guangzhou Fastprint Circuit Tech Co., Ltd., Shenzhen Fastprint Circuit Tech Co., Ltd., Yixing Silicon Valley Electronics Technology Co., Ltd.
    Inventors: Bei Chen, Bo Xu, Xinman Mo
  • Patent number: 9941232
    Abstract: An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 10, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Satoshi Shiraki, Koichi Tanaka, Masahiro Kyozuka, Tomohiro Suzuki
  • Patent number: 9915982
    Abstract: A display device is provided which suppresses cost increases attributable to design changes and so forth for things disposed on the inside of a product when a plurality of products of different screen size are developed, or when the screen size is changed. A display device 5 includes a display panel 11, a first board attachment component 13, a display panel board 18, a second board attachment component 21, a main board 22, a third board attachment component 23, and a power supply board 24. The main board 22 stores a plurality of display programs that produce an image to be displayed on the display panel 11, according to the screen size of the display panel 11. The first board attachment component 13, the display panel board 18, the second board attachment component 21, the main board 22, the third board attachment component 23, and the power supply board 24 are disposed in this order, starting from the display panel 11 side, on the rear side of the display panel 11.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 13, 2018
    Assignee: FURUNO ELECTRIC COMPANY LIMITED
    Inventors: Kenichi Murakami, Daigo Dohi
  • Patent number: 9911565
    Abstract: Provided are approaches for modularized power distribution. In one approach, an apparatus may include a module extending into an interior cavity of a housing assembly through an opening formed in a base section of the housing assembly. The module may include a component grid at one end for receiving one or more components (e.g., fuses, relays, circuit breakers, diodes, etc.), and a wiring alignment cover at an opposite end operable with a terminal. The apparatus may further include a mechanical sealing element disposed along one or more surfaces of the module to provide a seal between the module and the base section defining the opening. In another approach, a plurality of modules may be disposed within a plurality of openings formed in the base section. In another approach, the apparatus may include a bracket configured to releasably connect the base section and the cover.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: March 6, 2018
    Inventors: Geoffrey Schwartz, Justin Kaufman, Dana Scribner, Matt McWhinney
  • Patent number: 9888568
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 6, 2018
    Assignee: CRANE ELECTRONICS, INC.
    Inventors: Ernest Clyde Parker, Philip Joseph Lauriello
  • Patent number: 9881813
    Abstract: A mounting structure, including: a first component that has a first bump; a second component that has a second bump; a mounting component that has a primary mounting surface and a secondary mounting surface; a first solder that connects an electrode on the primary mounting surface and the first bump; a second solder that connects an electrode on the secondary mounting surface and the second bump; and a reinforcing resin that covers a part of the first solder and that is not in contact with the primary mounting surface.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hirohisa Hino, Yasuhiro Suzuki, Masato Mori, Naomichi Ohashi
  • Patent number: 9817271
    Abstract: A display panel is provided. The display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of thin film transistors, a plurality of metal wires, a protection layer, a first alignment layer, and a plurality of agglomerates. The first substrate has at least a display area and a non-display area located outside the display area. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The thin film transistors and the metal wires are disposed on the first substrate, the protection layer overlaying at least a portion of the metal wires. The first alignment layer is disposed on the protection layer for exposing a first surface of the protection layer. The agglomerates are disposed on at least a portion of the first surface.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 14, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Chu-Chun Cheng, Yu-Ju Chen, I-Hua Huang, Wan-Shan Yang, Chun-Teng Chen, Chen-Kuan Kao, Kuei-Ling Liu
  • Patent number: 9807890
    Abstract: The present disclosure is related to electronic modules for electronic components and methods for manufacturing the same. In one embodiment, an electronic module is formed using a first substrate having a first component area and a second substrate having a second component area. One or more electronic components may be attached to both the first component area and the second component area. The second substrate is mounted over the first substrate such that the second component area faces the first component area. An overmold covers the first component area and the second component area so as to cover the electronic components on both the first component area and the second component area. In this manner, the number of electronic components within the electronic module that can be mounted on an area of a printed circuit board (PCB) is increased.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 31, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Thong Dang, Mohsen Haji-Rahim, Joseph Byron Bullis
  • Patent number: 9804592
    Abstract: An optimization device, that optimizes a process procedure for each of a plurality of process machines in a substrate process system in which circuit substrates can be transported on two paths, including a first process for setting a process procedure for each of the process machines so as to optimize a total process time that is the sum of a process time for each of the plurality of process machines for a circuit substrate being transported on one of the two paths, and a process time for each of the plurality of process machines for a circuit substrate being transported on the other of the two paths; and a second process for setting a process procedure for each of the process machines so as to optimize the process times.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: October 31, 2017
    Assignee: FUJI MACHINE MFG. CO., LTD.
    Inventor: Kazuya Fukao
  • Patent number: 9796018
    Abstract: Provided is a silver powder which has an appropriate viscosity range at the time of paste production, can be easily kneaded, and prevents the occurrence of flakes. The silver powder to be used has a specific surface area ratio SAB/SAS of 0.5 to 0.9, wherein SAB is a specific surface area measured by the BET method, and SAS is a specific surface area calculated from a mean primary-particle diameter DS measured with a scanning electron microscope. Furthermore, the silver powder preferably has a degree of aggregation of 1.5 to 5.0, the degree being obtained in such a manner that a volume median diameter D50 measured by laser diffraction scattering is divided by the foregoing Ds.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 24, 2017
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventors: Toshiaki Terao, Yuji Kawakami
  • Patent number: 9791900
    Abstract: An expansion card mounting assembly includes a mounting structure and a circuit board coupled to the mounting structure. Expansion cards are mounted on a top side and a bottom side of the circuit board and secured at opposite ends by a moveable plate of the expansion card mounting assembly. The mounting structure includes an opening along a length of the expansion cards that allows air to flow over the expansion cards in multiple directions including a vertical direction. The moveable plate and mounting structure are configured to allow a position of the moveable plate on the mounting structure to be adjusted to mount expansion cards having different lengths in the expansion card mounting assembly.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 17, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Strickland Beall, Felipe Enrique Ortega Gutierrez, Brandyn David Giroux, Darin Lee Frink, Jason Alexander Harland, Roey Rivnay, Max Jesse Wishman, Yangtzu Lee Andrew Lee
  • Patent number: 9755341
    Abstract: A flexible printed circuit board (FPCB) connector includes a housing having a first mating interface configured for mating with a first FPCB and a second mating interface configured for mating with a second FPCB. A plurality of jumper conductors are held by the housing. The jumper conductors have first mating ends at the first mating interface being configured for mating with the first FPCB and the jumper conductors having second mating ends at the second mating interface being configured for mating with the second FPCB. The first mating interface is configured to be mated to the first FPCB at any location along a length of the first FPCB including locations remote from an end of the first FPCB.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 5, 2017
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Kyle Gary Annis, Dustin Carson Belack
  • Patent number: 9748217
    Abstract: A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 29, 2017
    Assignee: The University of Tokyo
    Inventor: Takayuki Ohba
  • Patent number: 9713258
    Abstract: An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Young Hoon Kwark
  • Patent number: 9691634
    Abstract: A method for creating electrically or thermally conductive vias in both vertical and horizontal orientations in a dielectric material has the steps of: (a) depositing a powder comprising metallic particles on a planar surface of a dielectric material having through or blind vias; (b) drying the deposited powder of metallic particles; (c) polishing the powder of metallic powders into the through or blind vias; (d) repeating steps (a)-(c) on a reverse side of the dielectric material; and (e) repeating steps (a)-(d) until no unfilled vias are detected.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 27, 2017
    Assignee: Abexl Inc.
    Inventor: Fred Koelling
  • Patent number: 9692100
    Abstract: A flat cable includes a plurality of resin layers that are flexible and stacked together, a line conductor, and grounding conductors. The flat cable includes a triplate line in which both surfaces of the line conductor oppose the corresponding grounding conductors, and a microstrip line in which only one of the surfaces of the line conductor opposes the corresponding grounding conductor. A width of the line conductor in the microstrip line is greater than a width of the line conductor in the triplate line, and the flat cable is bent at a position where the microstrip line is provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 27, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takahiro Baba, Nobuo Ikemoto
  • Patent number: 9673139
    Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 6, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshige Hirano, Michinari Tetani, Masakazu Hamada, Nobuaki Tarumi
  • Patent number: 9648758
    Abstract: A method for producing a circuit board comprising the following steps:—providing at least one first element of the circuit board to be produced, more particularly a multilayer core element;—applying an adhesion-preventing material to a region of the first element to be subsequently exposed;—applying at least one additional layer to the first element;—connecting the first element and the at least one additional layer; and—removing a portion of the additional layer to expose the region of the first element, wherein in the additional layer corresponding to the portion to be subsequently removed, the material of the additional layer is cut through on at least one edge of the portion to be subsequently removed.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 9, 2017
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Siegfried Götzinger, ShuYing Yao, Mikael Tuominen, Beck Han
  • Patent number: 9627799
    Abstract: A cable connector comprises a mating board, a plurality of cables, an organizer and a binding material. The mating board comprises a board body and a plurality of conductive portions provided on the board body. The cables are respectively electrically connected to the conductive portions. The organizer comprises an upper cap, a lower cap and a spacer interposed between the upper cap and the lower cap. The upper cap, the lower cap and the spacer cooperatively define a filling space that includes upper cable passages and lower cable passages respectively extending along the front-rear direction and respectively receiving the cables so as to allow the plurality of cables to pass through the filling space. The binding material is filled in the filling space of the organizer and fixes the plurality of cables to the organizer.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 18, 2017
    Assignee: Molex, LLC
    Inventors: Ting Chang Tseng, Yao Ting Wang
  • Patent number: 9627785
    Abstract: An electrical distribution center includes a bracket. A mounting plate is secured to the bracket and includes an aperture having a perimeter. An electrical connector is disposed within the aperture and includes locating structure that is captured between the perimeter and the bracket to align and to retain the electrical connector relative to the bracket. One locating structure includes spring arms that cooperate with notches provided by the aperture. Another locating structure includes an edge captured beneath a periphery of the aperture. The mounting plate is snap-fit to the bracket over the electrical connectors.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 18, 2017
    Assignee: Delphi Technologies, Inc.
    Inventors: Gustavo Eric Melchor Saucedo, Jesus R. Morales
  • Patent number: 9613841
    Abstract: An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: April 4, 2017
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 9609767
    Abstract: In at least some embodiments, an apparatus is provided that comprises a frame and a cover removably attached to the frame. The apparatus further comprises a geared latch assembly attached to the cover, the geared latch assembly having a geared latch. If the geared latch is rotated from a first position to a second position, the cover moves linearly from a closed state to an open state.
    Type: Grant
    Filed: December 5, 2015
    Date of Patent: March 28, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin D. Conn, Robert Martinez
  • Patent number: 9538663
    Abstract: A method for manufacturing a combined wiring board includes providing a metal frame having an accommodation opening portion, positioning a wiring board in the accommodation opening portion of the metal frame, and subjecting the metal frame to plastic deformation such that a sidewall of the wiring board is connected to a sidewall of the metal frame inside the accommodation opening portion of the metal frame.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: January 3, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Michimasa Takahashi
  • Patent number: 9536857
    Abstract: A heating header of a semiconductor mounting apparatus includes: a first material; and a second material, the second material being bonded to the first material and coming into contact with a first semiconductor chip when the first semiconductor chip is compressed, wherein a contact surface of the second material with the first semiconductor chip is a curved surface that is convex toward the first semiconductor chip side, and the contact surface of the second material with the first semiconductor chip becomes a planar surface when each temperature of the first material and the second material reaches a melting temperature of a solder that is formed between a first terminal of the first semiconductor chip and a second terminal of a second semiconductor chip.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 3, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Takumi Masuyama, Norio Kainuma
  • Patent number: 9508619
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Takuya Tsurume, Hiroki Adachi, Nozomi Horikoshi, Hisashi Ohtani
  • Patent number: 9505180
    Abstract: Producing a composite structure comprising fibre reinforced material impregnated with liquid resin by means of vacuum assisted resin transfer moulding, by method of: providing a forming structure comprising a rigid mould part and a second mould part; placing the fibre material in the rigid mould part; sealing the second mould part against the rigid mould part, forming a mould cavity; connecting a source of uncured fluid resin to at least one resin inlet communicating with the mould cavity; connecting at least one vacuum outlet communicating with the mould cavity; evacuating the interior of the forming structure through at least one vacuum outlet, measuring at least one vacuum outlet airflow level; supplying uncured resin from the source of uncured resin to the mould cavity through at least one resin inlet so as to fill the mould cavity with resin; and curing the resin in order to form the composite structure.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: November 29, 2016
    Assignee: LM GLASFIBER A/S
    Inventor: Karsten Schibsbye
  • Patent number: 9484275
    Abstract: A semiconductor module comprising a plurality of electrically conductive top plates, an electrically conductive base plate, a plurality of semiconductor chips installed on the base plate, a first power supply connected to the plates, a second power supply connected to the plates and an electrically insulating outer casing component. The semiconductor chips are individually in contact with the top plates. Each semiconductor chip comprises a first electrode electrically coupled with the base plate, and a second electrical pole electrically coupled with the corresponding top plate. The first power supply connecting plate is equipped with protruding parts that are individually in electrical contact with the top plates. The second power supply connecting plate is electrically connected to the base plate. The outer casing component is used to integrate the first power supply connecting plate and the second power supply connecting plate. The outer casing component comprises at least one opening.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: November 1, 2016
    Assignee: GE ENERGY POWER CONVERSION TECHNOLOGY LTD
    Inventors: Fei Xu, Pengcheng Zhu, Yingqi Zhang
  • Patent number: 9451709
    Abstract: A damage index predicting system is for predicting a damage-related index of solder joints of an electronic device having the solder joints that electrically connect an electronic component to a mounting circuit board and one or more detection solder joints that are designed so as to have a shorter life than the solder joints. The system includes: a database configured to store a fracture relationship between the detection solder joints and the solder joints; a fracture detector configured to detect fracture of the detection solder joints; and a processor configured to calculate a prediction value of the damage-related index of the solder joints based on information relating to the fracture of the detection solder joints obtained by the fracture detector and the fracture relationship stored in the database.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Monda, Minoru Mukai, Kenji Hirohata
  • Patent number: 9440440
    Abstract: A liquid ejecting apparatus includes a liquid ejecting unit that has an ejecting unit for ejecting liquid; a first wiring that transmits a driving signal for driving the ejecting unit to the liquid ejecting unit; a first connector that is provided in the liquid ejecting unit, and electrically connects the first wiring; a second wiring that transmits an ejecting control signal for controlling a supply of the driving signal to the ejecting unit to the liquid ejecting unit; and a second connector that is provided in the liquid ejecting unit, and electrically connects the second wiring, in which the liquid ejecting unit is located between the first connector and the second connector.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: September 13, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Kyohei Date
  • Patent number: 9426879
    Abstract: For providing an electric connection box including a metal core board, which can limit increase of a size thereof and be prevented from bending along the slit, the electric connection box 10 includes a metal core board 1, in which a plurality of core metal plates 21, 22 is laminated and insulation resin is filled between each of the plurality of core metal plates 21, 22. The plurality of core metal plates 21, 22 are provide with slits 3A, 3B to divide the core metal plates 21, 22 to a plurality of separate plates 21a, 21b, 22a, 22b and be filled with insulation resin. The slits 3A, 3B is formed not to overlap each other on the same one line when viewing in a vertical direction about the metal core board 1. The electric connection box 10 distributes electric power inputted from a plurality of power systems to each separate plates 21a, 21b, 22a, 22b.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: August 23, 2016
    Assignee: YAZAKI CORPORATION
    Inventors: Manabu Ooishi, Maki Sugiura, Kazuhiro Yamamoto, Kenji Ogawa
  • Patent number: 9414524
    Abstract: A circuit board assembly for installation in a cabinet includes a first standards based size first mounting frame portion having a PCB mounted thereto. A second mounting frame portion is connected to the first mounting frame portion having no portion of the PCB connected thereto. A combination size of the first and second mounting frames defines a larger second standards based size. Multiple heat transfer components may be connected to the first or second mounting frame portion provide a conduction/convection cooling path. The first mounting frame portion may include a first false board edge and the second mounting frame portion includes one or more false board edge(s) positioned laterally and oppositely directed to the first false board edge. The first and second false board edges are slidably received in opposed slots created in a cabinet.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: August 9, 2016
    Assignee: Artesyn Embedded Computing, Inc.
    Inventors: George Paul Zemke, Suzanne Marye Wong
  • Patent number: 9399143
    Abstract: An antenna for an implantable medical device (IMD) is provided that is formed on the same substrate as the telemetry circuitry for the IMD. The telemetry circuitry is formed on a portion of the substrate within the interior of a housing for the IMD, while at least one antenna is formed on an exterior portion of the substrate on the exterior of the housing to allow for far field telemetry. At least one electrical interconnect is formed on the substrate for connecting the antenna to the telemetry circuitry, where the electrical interconnect may comprise a controlled impedance line to minimize loss. A conformally-shaped hermetic cover, such as a ceramic material, may be formed in a desired shape around the exterior portion of the substrate and antenna and cofired together to form a monolithic structure encasing the antenna and exterior portion of the substrate.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 26, 2016
    Assignee: Medtronic, Inc.
    Inventors: Joyce K. Yamamoto, Quentin Scott Denzene, Michael William Barror
  • Patent number: 9385512
    Abstract: An electrical junction box for distributing electric power in a vehicle includes a metal core substrate provided with a core metal assembly having two core metal plates arranged with a gap, an insulating layer embedded in the gap and covering surfaces of the core metal plates to integrate the core metal plates, and electronic components. Electric power from a battery is inputted into the core metal plate, and electric power from an alternator is inputted into the core metal plate. The electronic components are provided with a plurality of attaching portions soldered or screwed to the metal core substrate. At least one of the attaching portions is attached to the core metal plate, and at least one of the attaching portions is attached to the core metal plate.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 5, 2016
    Assignee: Yazaki Corporation
    Inventors: Manabu Ooishi, Maki Sugiura, Kazuhiro Yamamoto, Kenji Ogawa
  • Patent number: 9385098
    Abstract: An integrated circuit package is described including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 5, 2016
    Assignee: NVIDIA Corporation
    Inventors: Leilei Zhang, Zuhair Bokharey
  • Patent number: 9383382
    Abstract: A microelectromechanical sensor that in one embodiment includes a supporting structure, having a substrate and electrode structures anchored to the substrate; and a sensing mass, movable with respect to the supporting structure so that a distance between the sensing mass and the substrate is variable. The sensing mass is provided with movable electrodes capacitively coupled to the electrode structures. Each electrode structure comprises a first fixed electrode and a second fixed electrode mutually insulated by a dielectric region and arranged in succession in a direction substantially perpendicular to a face of the substrate.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: July 5, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Barbara Simoni, Carlo Valzasina
  • Patent number: 9380711
    Abstract: A substrate manufacturing method includes an inner layer circuit forming step for partially removing metal films from an insulating base material (2), on both surfaces of which the metal films are stuck, and forming an inner layer circuit (3); and an insulating layer forming step for applying first insulating resin (4) to each of both the surfaces of the insulating base material (2) with an inkjet system and forming an insulating layer (5). In the insulating layer forming step, a via hole (6) from which the inner layer circuit (3) is partially exposed is formed simultaneously with the application of the first insulating resin (4). Consequently, a step of separately forming a via hole with a laser or the like is unnecessary, expenses are relatively low, and it is possible to simplify a manufacturing process.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 28, 2016
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Shukichi Takii, Noriaki Taneko, Shigeru Michiwaki, Mitsuho Kurosu, Yuichiro Naya
  • Patent number: 9362127
    Abstract: A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first region and the second region; wherein the first region and the second region are configured such that an adhesive force between the second region and the porous metal layer is lower than an adhesive force between the first region and the porous metal layer.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Krenzer, Thomas Kunstmann, Eva-Maria Hess, Manfred Frank
  • Patent number: 9349703
    Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
  • Patent number: 9324690
    Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck