Assembling Bases Patents (Class 29/830)
  • Patent number: 11821938
    Abstract: A rigid-flex printed circuit board (PCB) includes at least one rigid PCB including at least one electrical component, a flex circuit, and a built-in diagnostic circuit. The flex circuit includes at least one end connected to the at least one rigid PCD. The flex circuit includes at least one signal trace configured to deliver an electrical signal to the at least one electrical component. The built-in diagnostic circuit is configured to detect a fault in the rigid-flex PCB.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: November 21, 2023
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Gomathi Ganesh Narayanan
  • Patent number: 11825725
    Abstract: An electronic apparatus includes a display panel including a base substrate including an active area and a peripheral area adjacent to the active area, pixels on the active area, pads on the peripheral area and arranged in a first direction, signal lines connecting the pixels to the pads, and a vernier mark on the peripheral area and spaced apart from the pads and the signal lines, a circuit board on the display panel and including a base film, and leads on the base film and overlapping with the pads in a plan view, and a conductive adhesive member extending in the first direction and between the display panel and the circuit board to connect the pads to the leads. The conductive adhesive member overlaps with the vernier mark when viewed in a second direction intersecting the first direction.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: November 21, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun-yong An, Yun-kyeong In, Junwon Choi, Wonmi Hwang
  • Patent number: 11798887
    Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Tarek Ibrahim, Kristof Darmawikarta, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman
  • Patent number: 11784140
    Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11778738
    Abstract: A printed circuit board assembly includes a main printed circuit board including a first main signal line and a first dielectric having a first permittivity; a sub printed circuit board including a first sub signal line and a second dielectric having a second permittivity smaller than the first permittivity; and a first connection block configured to connect the first main signal line of the main printed circuit board and the first sub signal line of the sub printed circuit board.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hoon Hwangbo
  • Patent number: 11764198
    Abstract: A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 19, 2023
    Assignee: EV Group E. Thallner GmbH
    Inventor: Markus Wimplinger
  • Patent number: 11764344
    Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: September 19, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang
  • Patent number: 11749514
    Abstract: The invention relates to methods for drawing-off liquid from individual droplets which are in a predefined arrangement on a flat substrate and have sedimented material enclosed in them. A mask of an absorbent material comprising a pattern of indentations or holes which corresponds at least partially to the regular arrangement of the individual droplets, or a stiff, rigid plate of an absorbent material is positioned above the flat substrate in such a way that the droplets come into contact with the absorbent material peripherally so that liquid is drawn off there-into. The invention also relates to a mask of an absorbent material with a substantially rectangular shape which has a predefined pattern of indentations or holes for the purpose of separating liquid and sedimented material enclosed therein.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: September 5, 2023
    Inventors: Martin Schürenberg, Alexander Vossgröne
  • Patent number: 11721793
    Abstract: A display device includes: a display module; a driving chip assembly electrically connected to the display module and including a driving chip and a heat dissipator at least partially surrounding the driving chip; and a main circuit board electrically connected to the driving chip assembly and contacting the heat dissipator.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: August 8, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yeongsang Suh
  • Patent number: 11721882
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 8, 2023
    Assignee: MediaTek Inc.
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
  • Patent number: 11706873
    Abstract: A method for manufacturing a multilayer wiring substrate includes forming a resist layer having mask pattern, forming a conductor layer having conductor pattern using the resist layer, removing the resist layer, forming an insulating layer on the conductor layer such that the insulating layer is laminated on the conductor layer, forming a subsequent resist layer having mask pattern such that the subsequent resist layer is formed on the insulating layer, and forming a subsequent conductor layer having conductor pattern using the subsequent resist layer. The forming of the resist layer includes conducting first correction in which formation position of entire mask pattern of the resist layer is corrected with respect to reference position, and conducting second correction in which shape of the mask pattern of the resist layer is corrected with respect to reference shape, and the forming of the subsequent resist layer does not include conducting the second correction.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: July 18, 2023
    Assignee: IBIDEN CO., LTD.
    Inventor: Shigeto Iyoda
  • Patent number: 11682526
    Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer, first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween in the ceramic body, and first and second external electrodes disposed on external surfaces of the ceramic body and electrically connected to the first and second electrodes. At least one of the first and second external electrodes includes a first electrode layer including a first glass and a second electrode layer disposed on the first electrode layer and including a second glass. The first glass contains a larger amount of barium-zinc (Ba—Zn) than the second glass, and the second glass contains a larger amount of silicon (Si) than the first glass.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hye Min Bang, Bum Su Kim, Hyun Hee Gu, Hee Sang Kang
  • Patent number: 11670613
    Abstract: An arrangement, a method of manufacturing component carriers and a component carrier are provided. The arrangement includes a central carrier structure having a front side and a back side, a first layer stack having a first surface structure made of another material than the interior of the first layer stack and covered by a first release layer which is attached to the front side, and a second layer stack covered by a second release layer which is attached to the back side.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 6, 2023
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Mikael Tuominen, Nick Xin, Seok Kim Tay
  • Patent number: 11650570
    Abstract: A card manufacturing system includes a locating device and a separation device. A laminate sheet comprising a plurality of cards is received by the locating device and is imaged using first and second imaging modalities. The first imaging modality identifies a location of each of the plurality of information carrying cards within the laminate sheet and the second imaging modality images at least one graphic formed on a surface of the laminate sheet. A position of the at least one graphic with respect to at least one information carrying card is determined and the plurality of cards are removed from the laminate sheet using information corresponding to the location of each of the plurality of information carrying cards when the position of the at least one graphic with respect to the information carrying cards is within a predetermined range.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 16, 2023
    Assignee: Idemia America Corp.
    Inventor: Mark A. Cox
  • Patent number: 11621491
    Abstract: A chip antenna includes a first substrate, a second substrate overlapping the first substrate, a first patch, provided on a first surface of the first substrate, operating as a feed patch, a second patch, provided on the second substrate, operating as a radiation patch, at least one feed via penetrating through the first substrate in a thickness direction and configured to provide a feed signal to the first patch, and a ground pad provided on the other surface of the first substrate. The first substrate comprises a ceramic sintered material. The ceramic sintered material comprises an Mg2SiO4 phase, an MgAl2O4 phase, and a CaTiO3 phase, and a content of the CaTiO3 phase in the ceramic sintered material ranges from 5.1 mol % to 15.1 mol %.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 4, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Yeong Kim, Chin Mo Kim, Ji Hyung Jung, Sung Nam Cho, Sung Yong An
  • Patent number: 11622446
    Abstract: A wiring substrate includes a resin insulating layer, a conductor pad formed on the resin insulating layer, a coating insulating layer formed on the resin insulating layer such that the coating insulating layer is covering the conductor pad, and a metal post connected to the conductor pad and protruding from the coating insulating layer such that a gap is formed between the metal post and the conductor pad at a peripheral edge of the metal post. The coating insulating layer is formed such that the coating insulating layer has an interposed portion formed in the gap between the metal post and the conductor pad at the peripheral edge of the metal post.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 4, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Isao Ohno, Tomoya Daizo, Yoji Sawada, Kazuhiko Kuranobu
  • Patent number: 11610714
    Abstract: A slow wave inductive structure includes a first substrate. The slow wave inductive structure further includes a first conductive winding over the first substrate. The slow wave inductive structure further includes a second substrate over the first substrate, wherein a distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m, and the second substrate comprises polysilicon or doped silicon. The slow wave inductive structure further includes a second conductive winding on an opposite side of the second substrate from the first conductive winding.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 11605766
    Abstract: A light-emitting module includes: a light-transmitting lightguide plate; light sources disposed on the lightguide plate, each light source including a light-emitting element and a cover member including a first resin and provided beside a lateral surface of the light-emitting element, with first and second electrodes exposed through the cover member; a light-reflecting member provided on the lightguide plate and provided around the light sources, with the cover members of exposed through the light-reflecting member, wherein the light-reflecting member includes a second resin having a higher hardness than the first resin; a support layer covering the light-reflecting member and the cover members, with the first electrodes and the second electrodes exposed through the support layer, wherein the support layer includes a third resin having a higher hardness than the first resin; and a wiring layer provided on the support layer and connected to the first electrodes and the second electrodes.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: March 14, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Takayoshi Wakaki
  • Patent number: 11554585
    Abstract: A liquid ejecting head includes wiring members including a first-wiring member having a first-output terminal portion extending in a first-direction and a first-input terminal portion extending in the first-direction, and a second-wiring member having a second-output terminal portion extending in the first-direction and a second-input terminal portion extending in the first-direction; and a first-wiring substrate coupled to the first and second input terminal portions, in which a center of the first-output terminal portion is located in the first-direction with respect to a center of the second-output terminal portion in plan view, a center of the first-input terminal portion is disposed in a second-direction opposite to the first-direction with respect to the center of the first-output terminal portion in the plan view, and a center of the second-input terminal portion is disposed in the first-direction with respect to the center of the second-output terminal portion in the plan view.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 17, 2023
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Okui
  • Patent number: 11545412
    Abstract: A package structure including a circuit board and a heat generating element is provided. The circuit board includes a plurality of circuit layers and a composite material layer. A thermal conductivity of the composite material layer is between 450 W/mK and 700 W/mK. The heat generating element is disposed on the circuit board and electrically connected to the circuit layers. Heat generated by the heat generating element is transmitted to an external environment through the composite material layer.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 3, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Ching Sheng Chen, Ra-Min Tain, Ming-Hao Wu, Hsuan-Wei Chen
  • Patent number: 11540388
    Abstract: Disclosed are a flexible circuit board component and a display device. The flexible circuit board component includes a flexible circuit board and a foam structure. The flexible circuit board includes a first area and a second area which are arranged in a first direction and connected to each other. The foam structure is located on a side of the first area in the flexible circuit board, and includes a first foam and a second foam, and in the first direction, the second foam is located between the first foam and the second area. After the flexible circuit board component is affixed to a non-light-emitting display side of a display panel, in a direction perpendicular to an interface of the foam structure and the flexible circuit board, a height of the second foam on a side adjacent to the second area is less than a height of the first foam.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: December 27, 2022
    Assignees: WUHAN TIANMA MICROELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventor: Wei Shi
  • Patent number: 11532906
    Abstract: A power delivery system for a hardware processor includes a motherboard (MB), a voltage regulator (VR), an elastomer computer socket, and a plurality of power delivery paths within the socket. The socket connects the MB to the processor and comprises a first set of power pins that is connected to the processor by surface mount elements, and a second set of power pins that is not connected to the processor by surface mount elements. The plurality of electrical power delivery paths deliver VR power from the second set of C power pins to the first set of power pins for power delivery to the processor. The alignment frame aligns the processor, the plurality of power pins, and the MB. The plurality of power paths alone may meet the power demands of the processor. If not, a power plane from the MB provides additional power.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Yi Huang, Fernando Gonzalez Lenero, Liwei Zhao
  • Patent number: 11523493
    Abstract: An electronic control unit includes: a wiring substrate having a first surface on which a conductor wire is formed; a first electronic component that is implemented on the first surface of the wiring substrate, and has a large heat generation amount; a second electronic component that is implemented on the first surface of the wiring substrate, and has a heat generation amount smaller than the first electronic component; and a resin that covers the first electronic component, the second electronic component, and the first surface of the wiring substrate, and a second surface of the wiring substrate that is opposite to the first surface. A distance between an outer surface of the resin immediately below the first electronic component, and the second surface of the wiring substrate is longer than a distance between an outer surface of the resin immediately above the second electronic component, and the first surface of the wiring substrate.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 6, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Miki Hiraoka, Ryosuke Ishida, Yoshio Kawai
  • Patent number: 11495525
    Abstract: A module has electronic components mounted to a Printed Circuit Board (PCB) with multiple patterned conductive layers connecting to conductive slot metal around a conductive slot. A groove is cut through a top molding encapsulant above and into the conductive slot but does not cut through a bottom molding encapsulant. A terminal pin is inserted into the groove and pushed down into the conductive slot. When heated, embedded solder previously applied to the conductive slot metal flows between the end of the terminal pin and the conductive slot metal to form a solder bond. An end of the PCB past the conductive slot has no metal traces, preventing shorts. Epoxy can be placed into the groove around the terminal pin or a hole formed in the terminal pin to increase strength of the anchored terminal pin. The molding around the groove protects terminal pins from shorting from the side.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 8, 2022
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Lourdito M. Olleres, Shi Wo Chow
  • Patent number: 11482437
    Abstract: A method for manufacturing a printed wiring board which includes: Step (A) of laminating an adhesive sheet including a support and a resin composition layer bonded to the support to an inner layer board so that the resin composition layer is bonded to the inner layer board; Step (B) of thermally curing the resin composition layer to form an insulating layer; and Step (C) of removing the support, in this order, in which the support satisfies a condition (MD1): a maximum expansion coefficient EMD in an MD direction at 120° C. or more is less than 0.2% and a condition (TD1): a maximum expansion coefficient ETD in a TD direction at 120° C. or more is less than 0.2% below, when being heated under predetermined heating conditions, does not lower the yield even when the insulating layer is formed by thermally curing the resin composition layer with a support attached to the resin composition layer.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 25, 2022
    Assignee: Ajinomoto Co., Inc.
    Inventors: Masanori Ohkoshi, Hirohisa Narahashi, Eiichi Hayashi
  • Patent number: 11457532
    Abstract: A method for manufacturing a circuit board comprises steps of providing a single-sided board comprising a first insulating base, a copper layer, and at least one first conductive structure; providing a laminated board comprising a metal layer, a third insulating base, a metal shielding layer, and a second insulating base; forming a wiring layer by the metal layer comprising at least one signal wire and at least one connecting pad; defining at least one second through hole each passing through the second insulating base, the metal shielding layer, and the third insulating base; forming a second conductive structure in each second through hole; providing a double-sided board comprising a wiring layer, a fourth insulating base, a first copper foil; and at least one third conductive structure; pressing the single-sided board, at least one middle structure, and the double-sided board in that sequence to form the circuit board.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 27, 2022
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Fu-Yun Shen, Ming-Jaan Ho, Hsiao-Ting Hsu, Lin-Jie Gao
  • Patent number: 11445596
    Abstract: A circuit board includes an open substrate and a heat dissipation block. The open substrate includes a substrate body, an opening and at least one first fixing portion and at least one second fixing portion. The substrate body has a top surface and a bottom surface. The opening is in the substrate body and has a first sidewall and a second sidewall opposite to the first sidewall. The first fixing portion and the second fixing portion extends from the substrate body toward the opening, in which the first fixing portion and the second fixing portion are respectively protruded from the first sidewall and the second sidewall. The heat dissipation block is directly clamped between the first fixing portion and the second fixing portion.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: September 13, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Chin-Sheng Wang, Pei-Chang Huang
  • Patent number: 11439023
    Abstract: A system for providing selective adhesion printed circuit board (PCB) production comprises a conveyor mechanism, a curing system, and a computer. The conveyor mechanism is configured to convey a series of selective adhesion blanks, wherein each selective adhesion blank is utilized to produce a PCB and includes a flexible film, a substrate, a conductive layer, and a curable adhesive. The conductive layer is formed from electrically conductive material and adhered to the substrate. The curable adhesive is positioned between the flexible film and the conductive layer and is configured to selectively bond with the conductive layer when the curable adhesive is cured. The curing system is configured to cure the curable adhesive. The computer includes a processing element configured or programmed to: receive a plurality of PCB designs, and direct the curing system to cure the curable adhesive of a plurality of selective adhesion blanks for each PCB design.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 6, 2022
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Jonathan Douglas Hatch, Stephen McGarry Hatch
  • Patent number: 11424563
    Abstract: A method for manufacturing a board-to-board connecting structure, including providing a first circuit board, including a first dielectric layer, a second dielectric layer stacked on the first dielectric layer, and a first wiring layer sandwiched between the first dielectric layer and the second dielectric layer. A second circuit board is provided, including a third dielectric layer, a fourth dielectric layers stacked on the third dielectric layer, and a second wiring layer sandwiched between the third dielectric layer and the fourth dielectric layer. The first step and the fourth dielectric layer are bonded through a first adhesive layer. The third step and the dielectric layer are bonded through a second adhesive layer. The second step and the fourth step are bonded through the conductive layer.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: August 23, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO.,LTD, GARUDA TECHNOLOGY CO., LTD
    Inventors: Xiao-Feng Zheng, Xiao-Peng Rong
  • Patent number: 11416690
    Abstract: A memory card reader body includes proposed, on an internal face, a receiving recess to receive a memory card connector. The receiving recess has electrically conductive tracks forming a protective mesh for the memory card connector. The conductive tracks are such that they also extend on an external face of the memory card reader body through vias passing through the internal and external faces.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 16, 2022
    Assignee: BANKS AND ACQUIRERS INTERNATIONAL HOLDING
    Inventors: Stephane Pavageau, Jean-Jacques Delorme, Johann Jadeau
  • Patent number: 11417255
    Abstract: The present invention discloses a driving circuit for a display panel and a display device. The driving circuit includes a driving circuit board configured to carry a driving circuit, and first pads located on the driving circuit. The first pads are connected through a detachable connector.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 16, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Jianfeng Shan
  • Patent number: 11416729
    Abstract: The present invention relates to a metal card manufacturing method including the steps of: preparing a metal sheet having a given size capable of accommodating a plurality of individual cards; forming holes on at least one or more edges of stacked sheets formed by stacking a plurality of sheets inclusive of adhesive sheets and an inlay sheet on which antenna coils are printed, the plurality of sheets having the same size capable of accommodating the plurality of individual cards as each other; fitting the holes formed on the stacked sheets to pins located on a loading plate; placing the metal sheet on top of the stacked sheets; forming a metal card sheet through lamination among the metal sheet and the stacked sheets; and cutting the metal card sheet along individual card outlines of the plurality of individual cards.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 16, 2022
    Assignees: Kona I Co., Ltd., Kona M Co., Ltd.
    Inventors: Ki Sung Nam, Han Seon Kim, Suk Ku Lee
  • Patent number: 11411351
    Abstract: A separable and reconnectable connector for semiconductor devices is provided that is scalable for devices having very small contact pitch. Connectors of the present disclosure include signal pins shielded by pins electrically-coupled to ground. Embodiments provide one or more signal pins in a contact array electrically-shielded by at least one ground pin coupled to a ground plane. Embodiments thereby provide signal pins, either single-ended or a differential pair, usable to transmit signals with reduced noise or cross-talk and thus improved signal integrity. Embodiments further provide inner ground planes coupled to connector ground pins to shield pairs of differential signal pins without increasing the size of the connector. Inner grounding layers can be formed within isolation substrates incorporated into connector embodiments between adjacent pairs of signal pins.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: August 9, 2022
    Assignee: GITech, Inc.
    Inventor: John Williams
  • Patent number: 11395412
    Abstract: The disclosure relates to systems and methods for using additive manufacturing techniques for fabricating ball grid array (BGA) surface mounting pads (SMP), and surface mounted technology devices (SMT) package sockets. More specifically, the disclosure relates to additive manufacturing methods for additively manufactured electronic (AME) circuits such as a printed circuit board (PCB), and/or flexible printed circuit (FPC), and/or high-density interconnect printed circuit board (HDIPCB) each having integrated raised and/or sunk BGA SMP, and or surface mounting sockets for SMT device(s) defined therein, and methods of coupling surface mounted devices such as BGA and/or SMT thereto.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: July 19, 2022
    Assignee: Nano Dimension Technologies, LTD.
    Inventors: Daniel Sokol, Aviram Lancovici
  • Patent number: 11372392
    Abstract: A computer-implemented method of internally printing a biostructure on a damaged area of a patient. The method includes: assembling a first bioprinter capsule and a first cartridge capsule to form an assembled bioprinter internally within the patient based, at least in part, on directing one or more magnetic fields towards a first bioprinter capsule and a first cartridge capsule, moving the assembled bioprinter to the internally damaged area of the patient based, at least in part, on altering the one or more external magnetic fields directed towards the assembled bioprinter, and printing, via the assembled bioprinter, a first biostructure onto the internally damaged area of the patient based, at least in part, on altering the one or more external magnetic fields directed towards the assembled bioprinter, wherein the one or more external magnetic fields are sequentially altered to incrementally move the assembled bioprinter along at least one plane.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sarbajit K. Rakshit, Mukundan Sundararajan
  • Patent number: 11370174
    Abstract: A printer pressing assembly for forming material layers is provided. The printer pressing assembly includes a support assembly having a support surface, a driver and a press stop. The driver is able to change an elevation of the support surface relative to an elevation of the press stop. A nozzle is capable of dispensing a material onto the support surface. Further, a press is positionable opposite to the support surface and capable of moving relative to the support. Additionally, the press stop is capable of being elevated above the support surface so as to engage an abutment surface of the press to set a pre-determined distance between the contact surface of the press and the support surface.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 28, 2022
    Assignee: IO Tech Group Ltd.
    Inventors: Michael Zenou, Ziv Gilan
  • Patent number: 11369049
    Abstract: An electromagnetic shielding element and, transmission line assembly and electronic structure package using the same are provided. The electromagnetic shielding element is applied to the transmission line assembly and the electronic structure package to shield electromagnetic noise. The electromagnetic shielding element includes a quantum well structure, and the quantum well structure includes at least two barrier layers and at least one carrier confined layer located between the two barrier layers. Each barrier layer has a thickness between 0.1 nm and 500 nm, and the thickness of the carrier confined layer is between 0.1 nm and 500 nm. The electromagnetic shielding element absorbs electromagnetic wave noise to suppress electromagnetic interference.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 21, 2022
    Assignee: HOTEK MATERIAL TECHNOLOGY CO., LTD.
    Inventors: Hao-Wei Fong, Ming-Goo Chien, Chia-Yu Wu
  • Patent number: 11357108
    Abstract: A printed circuit board connector for orthogonal mating of two or more printed circuit boards. The connector utilizes interior perimeter trace connections of a main printed circuit board and internal trace connections of a mating printed circuit board in conjunction with external trace connections. The main board may utilize surface connections, where both external trace connections and internal trace connections are exposed on a surface of the main board to couple to the mating board. The main board may include a slot or pocket, allowing for the partial insertion of the mating board into the main board, with internal trace connections disposed within the slot or pocket. The slot or pocket may extend through the main board, such that the internal trace connections are disposed along a side of the pocket to couple with corresponding internal trace connections of the mating board.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: June 7, 2022
    Assignee: Battelle Memorial Institute
    Inventors: Andrew M. Schimmoeller, Jeffrey A. Friend
  • Patent number: 11352297
    Abstract: The invention provides novel methods and novel additive compositions and use thereof in a wide range of concrete production for improving properties of concrete materials, such as durability and aestheticity. The methods and compositions of the invention may be applied in a variety of cement and concrete components in the infrastructure, construction, pavement and landscaping industries.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 7, 2022
    Assignee: SOLIDIA TECHNOLOGIES, INC.
    Inventors: Ahmet Cuneyt Tas, Deepak Ravikumar, Jason E. Bryant
  • Patent number: 11350530
    Abstract: A process for producing a backplane circuit board (20) having an internal face (142) adapted to be connected to connectors (13) of circuit boards (12) and an external face (143) adapted to be connected to an external connector (15), blind holes (146, 148) opening on the internal face (142) and external face (143) of the backplane circuit board (20), wherein bonding layers (31, 32) having zones (41, 42) cleared of material facing the blind holes are used between the printed circuits (21, 22, 23).
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 31, 2022
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventors: François Guillot, Patrice Chetanneau
  • Patent number: 11345790
    Abstract: Described herein are techniques for reducing resin squeeze-out including a method comprising receiving a first component and a second component, where the first component is configured to be joined to the second component at an overlap area using an adhesive layer to form a structure having a ledge. The method further comprises applying the adhesive layer to the overlap area on the first component. The method further comprises selectively curing a portion of the adhesive layer adjacent to the ledge. The method further comprises forming the structure by combining the first component, the second component, and the adhesive layer and curing a remainder of the adhesive layer.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 31, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sarah K. Czaplewski-Campbell, Eric J. Campbell
  • Patent number: 11329029
    Abstract: A semiconductor package includes a first semiconductor chip including a first chip body portion and a first chip rear bump disposed in a region recessed into the first chip body portion, and a second semiconductor chip stacked on the first semiconductor chip and including a second chip body portion and a second chip front bump protruding from the second chip body portion. The first chip rear bump includes a lower metal layer and a solder layer disposed on the lower metal layer. The second chip front bump is bonded to the solder layer. The second chip front bump is disposed to cover at least the solder layer on a bonding surface of the second chip front bump and the solder layer.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Ho Cho
  • Patent number: 11272620
    Abstract: The present disclosure relates to the technical field of circuit boards, and provides an embedded circuit board and a method for manufacturing the embedded circuit board. The embedded circuit board includes: a first outer wiring board, a base board, and a second outer wiring board. The base board has at least one groove, the first outer wiring board, the base board and the second outer wiring board define through holes to form a resonant chamber. A minimal distance between the side walls of the groove and the side walls of the adjacent through holes is 50 um-400 um. An electronic device is received in the groove.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: March 8, 2022
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Lixiang Huang, Zedong Wang, Hua Miao
  • Patent number: 11266013
    Abstract: A rigid-flex printed circuit board includes an inner circuit substrate, two adhesive sheet layers formed on the inner circuit substrate, two shielding structures, and two outer circuit layers. The inner circuit substrate is divided into a flexible area, a first and second rigid area. Each shielding structure includes a copper layer, a metal seed layer formed on the copper layer, a flexible dielectric layer formed on the metal seed layer, and a backing adhesive sheet layer formed on the flexible medium layer. The backing adhesive sheet layer is pressed on the adhesive sheet layer and the inner circuit substrate located in the flexible area. Each outer circuit layer is formed on the copper layer, located in the first rigid area and the second rigid area and electrically connected to the inner circuit substrate.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: March 1, 2022
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventor: Wei-Xiang Li
  • Patent number: 11251171
    Abstract: Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Michael Rifani, Robert J. Munoz, Thomas P. Thomas, John Mark Matson, Kursad Kiziloglu
  • Patent number: 11234325
    Abstract: A printed circuit board including a set of five layers encompassing a breakout area is described. The set includes a first ground layer, a first signal layer having a first conductive layer within the breakout area, a second ground layer having conductive material, a second signal layer having a second conductive layer within the breakout area, and a third ground layer. The second ground layer having a void forming a differential pair being two parallel traces, and being separated into a first portion positioned within the breakout area and a second portion outside of the breakout area. The differential pair having a first width and a first spacing within the breakout area and a second width and second spacing outside of the breakout area, with the second width greater than the first width. The first and second conductive layers forming a first ground plane and a second ground plane.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 25, 2022
    Assignee: Infinera Corporation
    Inventors: Aneesh Kachroo, Mithun Gopal V V, Navneeth Jayaraj
  • Patent number: 11219128
    Abstract: A laminated structure includes an interconnect structure including first and second product areas and a first interconnect layer, and a first insulating layer formed on the interconnect structure. The first product area includes an opening penetrating the first insulating layer, and the second product area includes an annular groove penetrating the first insulating layer. The laminated structure further includes an electronic component mounted inside the opening in the first product area with an annular gap formed between the electronic component and a wall surface defining the opening, an insulating member located inside the groove in the second product area, a second insulating layer that fills the annular gap and the groove, and covers the first insulating layer, the electronic component, and the insulating member, and a second interconnect layer formed on the second insulating layer, and electrically connected to the first interconnect layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 4, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Izumi Tanaka
  • Patent number: 11212914
    Abstract: The present disclosure provides a circuit board, including a substrate on which a first conductive layer and an electronic device are disposed, wherein the first conductive layer is disposed on a first surface of the substrate, and wherein a bottom end of the electronic device is disposed on the first conductive layer through the substrate. The present disclosure provides a display device.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 28, 2021
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xingjun Shu, Jianwu Wu, Xi Chen, Xinda Li, Shengwei Yang, Yadong Zhang, Jianye Tang, Jiaqiang Wang
  • Patent number: 11191164
    Abstract: A mold includes a mold base material and a rugged structure located at a main surface of the mold base material. The rugged structure includes a plurality of linearly shaped projected portions for forming wiring, and a circularly shaped projected portion for forming a pad portion, in which a light-shielding layer is provided at a top portion flat surface of the circularly shaped projected portion for forming the pad portion.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 30, 2021
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Ryohei Kasai, Tadashi Furukawa, Ryo Furugen, Teppei Sotoda, Tetsushi Hosoda, Ayako Furuse
  • Patent number: 11191159
    Abstract: A printed circuit board connector for orthogonal mating of two or more printed circuit boards. The connector utilizes interior perimeter trace connections of a main printed circuit board and internal trace connections of a mating printed circuit board in conjunction with external trace connections. The main board may utilize surface connections, where both external trace connections and internal trace connections are exposed on a surface of the main board to couple to the mating board. The main board may include a slot or pocket, allowing for the partial insertion of the mating board into the main board, with internal trace connections disposed within the slot or pocket. The slot or pocket may extend through the main board, such that the internal trace connections are disposed along a side of the pocket to couple with corresponding internal trace connections of the mating board.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: November 30, 2021
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Andrew M. Schimmoeller, Jeffrey A. Friend