Assembling Bases Patents (Class 29/830)
  • Patent number: 10964633
    Abstract: A wiring substrate includes: a wiring layer; an insulating layer covering the wiring layer, and including a first opening portion exposing the wiring layer and a second opening portion exposing the wiring layer, wherein a diameter of the second opening portion is larger than that of the first opening portion; a first metal layer formed in the first opening portion and the second opening portion, and having a recess in the second opening portion; and a second metal layer that is formed on the first metal layer formed in the first opening portion and the second opening portion, wherein a portion of the second metal layer fills the recess. The first metal layer and the second metal layer serve as connection terminals to be electrically connected to an electronic component.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 30, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Hikaru Tanaka
  • Patent number: 10954119
    Abstract: A MEMS micromirror includes a mirror surface driving structure which is positioned on a substrate and includes two L-shaped structures in head-to-tail arrangement. Each L-shaped structure includes a second torsion beam, an L-shaped transverse plate and a second comb-shaped structure. The first driving electrode is provided on the substrate at a position under a head end of the L-shaped transverse plate, the head end of the L-shaped transverse plate is rotatable with support of the second torsion beam, and a tail end of the L-shaped transverse plate is connected with the second comb-shaped structure. The micromirror surface layer is disposed above the mirror surface driving structure, the first torsion beam is fixed by the substrate and supports two sides of the micromirror surface layer, and two sides, corresponding to the second comb-shaped structures, of the micromirror surface layer are provided with first comb-shaped structures, respectively.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 23, 2021
    Assignee: INSTITUTE OF GEOLOGY AND GEOPHYSICS CHINESE ACADEMY OF SCIENCES (IGGCAS)
    Inventors: Hang Li, Chen Sun, Lianzhong Yu
  • Patent number: 10950463
    Abstract: A method of manufacturing a component carrier is disclosed. The method includes providing an electrically insulating layer structure having a front side and a back side, wherein the front side is covered by a first electrically conductive layer structure and the back side is covered by a second electrically conductive layer structure, carrying out a first opening process, such as a first laser drilling, through the first electrically conductive layer structure and into the electrically insulating layer structure from the front side to thereby form a blind hole in the electrically insulating layer structure, and thereafter carrying out a second opening process, such as a second laser drilling, through the second electrically conductive layer structure and through the electrically insulating layer structure from the back side to thereby extend the blind hole into a through hole, in particular a laser through hole, with substantially trapezoidal shape.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 16, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Abderrazzaq Ifis
  • Patent number: 10873145
    Abstract: Aspects of the embodiments are directed to a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements. In embodiments, the PCB is part of a dual inline memory module. The conductive layer can be fashioned such that it extends out from the PCB and returns over the circuit elements to define an air gap between the conductive layer and the surface of the PCB and/or the surface of the circuit elements. In embodiments, a connection adaptor can be used to accommodate various PCB thicknesses so that the PCB can be electrically connected to an edge connector.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Guoliang Ying, Na Chen, Liguang Du
  • Patent number: 10874018
    Abstract: A printed wiring board includes a laminate including first conductor pads on first surface side of the laminate and second conductor pads on second surface side of the laminate, and a solder resist layer formed on the first surface side of the laminate and having openings formed such that the openings are exposing the first conductor pads respectively. The laminate includes a resin insulating layer and has first surface on the first surface side and second surface on the second surface side on the opposite side with respect to the first surface of the laminate, and the second conductor pads are embedded in the second surface of the laminate such that the second conductor pads have surfaces exposed from the second surfaces of the laminate respectively and that the surfaces of the second conductor pads are protruding from the second surface of the laminate.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 22, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Hiroyuki Ban, Haiying Mei
  • Patent number: 10839537
    Abstract: A camera module with a fixed near field focus is configured to capture a single image. That single image is segmented by an image divider a number of regions. A focus metric determiner then determines a focus metric for each of the regions. A depth map generator maps the focus metric into a depth value for each of the regions and combines the depth values to generate a depth map.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: November 17, 2020
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Duncan Hall
  • Patent number: 10798841
    Abstract: An electronic apparatus includes a housing, a first substrate, and at least one substrate module. The housing includes side plates and a bottom plate. The side plates define the inside space having a bottom opening. The side plates include a first side plate and a second side plate connected to the first side plate. The first side plate has a protrusion protruding toward the inside space of the housing. The bottom plate is connected to the side plates to close the bottom opening. The first substrate is provided in the inside space to face the bottom plate. The at least one substrate module is provided on the first substrate in the inside space. The substrate connecting member is provided on the first substrate to face the second side plate and has a hole into which the protrusion of the first side plate is inserted.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: October 6, 2020
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventor: Takashi Fujiki
  • Patent number: 10764995
    Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 1, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jin-Wei You, Chun-Lung Chen
  • Patent number: 10749414
    Abstract: A motor driving device that converts alternating-current power to direct-current power and drives a motor, the motor driving device including a printed circuit board having a first plate surface and a second plate surface, having an inverter module and an inverter module provided on the first plate surface, having a first power pattern provided on the second plate surface and connected to the inverter module, having a second power pattern provided on the second plate surface and connected to the inverter module, and having a jumper portion to connect the first power pattern and the second power pattern. A cross-sectional area of the jumper portion is larger than a cross-sectional area of the first power pattern or the second power pattern.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 18, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norikazu Ito, Takuya Shimomugi, Masahiro Fukuda
  • Patent number: 10691232
    Abstract: A pressing pad for assembling a display module by applying a pressure to a flexible display panel to attach the flexible display panel to a window member and a method of assembling a display module, the pressing pad including a first pressing part that applies a first pressure onto a display area of the flexible display panel; a second pressing part that applies a second pressure onto a pad area of the flexible display panel, the second pressure being less than the first pressure and the pad area of the flexible display panel being adjacent to the display area of the flexible display panel; and a support part that supports the first and second pressing parts, wherein the second pressing part has a height from the support part that is less than a height of the first pressing part.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Namkung, Yonghoon Won, Yonghoon Chun
  • Patent number: 10681812
    Abstract: A flexible connector includes a unitary connector block having first and second board-facing areas. The first and second board-facing areas are longitudinally spaced from each other on a chosen surface of the connector block. The connector block includes a block body transversely separating the chosen surface from an opposing surface oppositely facing from the chosen surface. The connector block includes a flexible connector bridge longitudinally interposed between the first and second board-facing areas. A first connector port is located within the first board-facing area. A second connector port is located within the second board-facing area. A connector trace extends through at least a portion of the block body between the first and second board-facing areas. The connector trace electrically connects the first and second connector ports. Methods of making and using the flexible connector are also included.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 9, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Jeffrey David Hartman
  • Patent number: 10672693
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Patent number: 10665452
    Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
  • Patent number: 10651526
    Abstract: A flexible flat cable and a manufacturing method thereof are provided. The flexible flat cable includes a plurality of ground parts comprising a conductive material disposed at intervals, a plurality of signal transmission parts comprising a conductive material disposed between the plurality of ground parts, an outer skin covering the signal transmission parts and the ground parts, and a conductive adhesive layer disposed between the ground parts and the signal transmission parts and the outer skin part, the signal transmission part comprising an insulating member and a strip line disposed within the insulating member and the ground part comprising a ground member having the same cross section as the strip line and a conductive adhesive block coupled to the ground member with the conductive adhesive layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-hee Bae, Young-kun Kwon
  • Patent number: 10631406
    Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chih-Cheng Lee
  • Patent number: 10531577
    Abstract: A method of manufacturing a component carrier is provided. The method includes forming a through hole between a first main surface and a second main surface of an electrically insulating layer structure by removing material from at least one of the main surfaces of the electrically insulating layer structure, in particular by irradiating at least one of the main surfaces of the electrically insulating layer structure with at least one laser shot, wherein the at least one main surface from which material is removed, in particular which is to be irradiated, is not covered by an electrically conductive layer structure at least in a surface region in which the through hole is to be formed, and subsequently at least partially filling the through hole and at least partially covering the main surfaces of the electrically insulating layer structure by an electrically conductive filling medium.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 7, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Gernot Grober
  • Patent number: 10511076
    Abstract: An RF coupler having: a pair of input ports; a pair of output ports; and a coupling region for coupling: a portion of an input signal at a first one of the input ports to first of the pair of output ports and another portion of the input signal fed to the first one of the input ports a second one of the output ports; and one portion of an input signal fed to a second one of the input ports to the second of the pair of output ports and another portion of the input signals fed to the second one of the input ports to the second one of the output ports. The coupling region comprises a plurality of serially connected, vertically stacked, coupling sections. Each one of a plurality of electrically conductive layers is disposed between a pair of the vertically stacked coupling sections.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: December 17, 2019
    Assignee: Raytheon Company
    Inventors: Christopher M. Laighton, Susan C. Trulli, Elicia K. Harper
  • Patent number: 10497667
    Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Xin-Hua Huang, Kuan-Liang Liu, Kuo Liang Lu, Ping-Yin Liu
  • Patent number: 10453787
    Abstract: An electronic module assembly including a via spanning multiple layers in a wafer based module is described. The electronic module assembly can include a first layer deposited upon a substrate, a second layer deposited on a top surface of the first layer, and the via spanning multiple layers. The via can include a first bottom that is formed on a top surface of the first layer and a first sidewall that upstands from the first bottom and extending at least through the second layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 22, 2019
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Maurice S. Karpman, Nicole S. Mueller, Gary B. Tepolt, Russell Berman
  • Patent number: 10283492
    Abstract: Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 7, 2019
    Assignee: Invensas Corporation
    Inventor: Nader Gamini
  • Patent number: 10274998
    Abstract: The invention relates to a holding component with a riser card for receiving an expansion component for a computer system. The riser card comprises a first mating plug connector on a first side of a bottom plate of the holding component. Further, the riser card comprises a first plug connector on a second side of the bottom plate opposite the first side. The holding component is adapted to receive the expansion component by establishing a plug connection of a second plug connector of the expansion component and the first mating plug connector on the holding component, wherein the holding component comprises a slot bracket, which is adapted to receive a slot angle of the expansion component. Furthermore, the invention relates to a support component for receiving at least one holding component and to an assembly comprising a chassis of a server module and of a holding component as well as of a support component.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Ronny Hesse
  • Patent number: 10256117
    Abstract: There is provided a method for manufacturing a wiring substrate with a through electrode, the method including providing a device substrate having a through hole, an opening of the through hole being blocked by a current supply path and the wiring substrate including the device substrate as a core layer with the through electrode; and disposing a first metal in the through hole to form the through electrode by electroplating, in a depth direction of the through hole, using the current supply path.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Sony Corporation
    Inventors: Shun Mitarai, Shusaku Yanagawa, Hiroshi Ozaki
  • Patent number: 10231345
    Abstract: Embodiments of the present invention provide an attachment apparatus and an attachment method for a conductive adhesive. The attachment apparatus includes: a carrier stage, which is provided with at least one working surface, the working surface being configured to support a printed circuit board and provided with a groove, and the groove being provided with a plurality of adsorption holes on its bottom surface; a vacuum adsorption device being connected to each of the plurality of adsorption holes; and an attaching mechanism provided above the carrier stage, and configured to attach the conductive adhesive to a predetermined region of the printed circuit board, and the predetermined region being a region of the printed circuit board to be squeeze connected to a flexible printed circuit board or a chip on film.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hanwei Tu, Minghui Liu, Hongjie Ding, Xikui Hao, Pengcheng Wang
  • Patent number: 10219374
    Abstract: A printed wiring board includes a first insulating layer, a second conductor layer including first and second circuits, a second insulating layer covering the second conductor layer on the first insulating layer, a third conductor layer including first and second circuits, a third insulating layer covering the third conductor layer on the second insulating layer, a fourth conductor layer including first circuit, a second via conductor connecting the first circuits in the second and third conductor layers through the second insulating layer, and a first skip via conductor penetrating through the second circuit in the third conductor layer and connecting the second circuit in the second conductor layer and the first circuit in the fourth conductor layer through the second and third insulating layers. The second and third conductor layers are formed such that the second conductor layer has thickness t2 larger than thickness t3 of the third conductor layer.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 26, 2019
    Assignee: IBIDEN CO., LTD.
    Inventor: Teruyuki Ishihara
  • Patent number: 10212836
    Abstract: One aspect relates to an electrical bushing for a medically implantable device, including an electrically insulating base body and an electrical conducting element. The conducting element includes a cermet, and the base body and the conducting element are connected by a sintered bond with a hermetic seal against the base body. The conducting element extends from a first surface of the base body through the base body to a second surface of the base body. The conducting element has first and second electrically conductive areas, and at least one of the electrically conductive areas is at least partially superimposed by a layer-like contact element, including a metal, so that the conducting element is connected in an electroconductive manner via the contact element. The contact element is an electrochemically created layer, such that it has a porous structure, wherein the porosity of the contact element is not more than 20%.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 19, 2019
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Robert Dittmer, Frank Krüger
  • Patent number: 10123411
    Abstract: A printed wiring board includes an insulating sheet, a conductive layer formed on one main surface of the insulating sheet, and an insulating film laminated with an adhesive layer on the main surface of the insulating sheet formed with the conductive layer. The position of an end part of the insulating film is located outside the position of an end part of the adhesive layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 6, 2018
    Assignee: FUJIKURA LTD.
    Inventor: Kazutoshi Matsumura
  • Patent number: 10096491
    Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 9, 2018
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Wei-Chung Hsiao, Ming-Chen Sun, Liang-Yi Hung
  • Patent number: 10088877
    Abstract: A board card module including a case, a main board, and an expansion card is provided. The case has an accommodating space. The main board is fixed to the case and located in the accommodating space. The main board has a connecting port. The expansion card is detachably pivoted to the case and located in the accommodating space. The expansion card has a terminal set and the expansion card is rotatable relative to the case to insert the terminal set into or separate the terminal set from the connecting port.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 2, 2018
    Assignee: Wistron Corporation
    Inventors: Fu-Lung Lu, Cheng-An Lu
  • Patent number: 10034393
    Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Douglas A. Baska, Daniel M. Dreps, Rohan U. Mandrekar, Roger D. Weekly
  • Patent number: 9958909
    Abstract: A housing design and method of providing electromagnetic compatibility (EMC) by mitigating a slot antenna in a corner region of a housing, the corner profile including an electrically conductive insert that has a spring bias, such as a spring or coated plastic member, in a corner of the housing.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 1, 2018
    Assignee: General Electric Company
    Inventors: Bernd Sporer, Klaus Weinmann, Oleg Schneider
  • Patent number: 9942976
    Abstract: A boss-type metal-based sandwich rigid-flex board and preparation method thereof are disclosed. The boss-type metal-based sandwich rigid-flex board comprises a rigid sub-plate, a flexible sub-plate, a dielectric layer, and a metal core layer, wherein the metal core layer has front and back sides on which at least one metal boss and at least one heat dissipation area are arranged respectively, the dielectric layer, and the rigid sub-plate and/or the flexible sub-plate are sequentially stacked on the front and back sides of the metal core layer respectively, and each of the rigid sub-plate, the flexible sub-plate and the dielectric layer is provided with a first window area fit with the metal boss, and a second window area corresponding to the heat dissipation area. The boss-type metal-based sandwich rigid-flex board (with a metal boss and a heat dissipation area arranged on the front side) prepared according to the present disclosure uses a metal core layer for heat dissipation.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 10, 2018
    Assignees: Guangzhou Fastprint Circuit Tech Co., Ltd., Shenzhen Fastprint Circuit Tech Co., Ltd., Yixing Silicon Valley Electronics Technology Co., Ltd.
    Inventors: Bei Chen, Bo Xu, Xinman Mo
  • Patent number: 9941232
    Abstract: An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 10, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Satoshi Shiraki, Koichi Tanaka, Masahiro Kyozuka, Tomohiro Suzuki
  • Patent number: 9915982
    Abstract: A display device is provided which suppresses cost increases attributable to design changes and so forth for things disposed on the inside of a product when a plurality of products of different screen size are developed, or when the screen size is changed. A display device 5 includes a display panel 11, a first board attachment component 13, a display panel board 18, a second board attachment component 21, a main board 22, a third board attachment component 23, and a power supply board 24. The main board 22 stores a plurality of display programs that produce an image to be displayed on the display panel 11, according to the screen size of the display panel 11. The first board attachment component 13, the display panel board 18, the second board attachment component 21, the main board 22, the third board attachment component 23, and the power supply board 24 are disposed in this order, starting from the display panel 11 side, on the rear side of the display panel 11.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 13, 2018
    Assignee: FURUNO ELECTRIC COMPANY LIMITED
    Inventors: Kenichi Murakami, Daigo Dohi
  • Patent number: 9911565
    Abstract: Provided are approaches for modularized power distribution. In one approach, an apparatus may include a module extending into an interior cavity of a housing assembly through an opening formed in a base section of the housing assembly. The module may include a component grid at one end for receiving one or more components (e.g., fuses, relays, circuit breakers, diodes, etc.), and a wiring alignment cover at an opposite end operable with a terminal. The apparatus may further include a mechanical sealing element disposed along one or more surfaces of the module to provide a seal between the module and the base section defining the opening. In another approach, a plurality of modules may be disposed within a plurality of openings formed in the base section. In another approach, the apparatus may include a bracket configured to releasably connect the base section and the cover.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: March 6, 2018
    Inventors: Geoffrey Schwartz, Justin Kaufman, Dana Scribner, Matt McWhinney
  • Patent number: 9888568
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 6, 2018
    Assignee: CRANE ELECTRONICS, INC.
    Inventors: Ernest Clyde Parker, Philip Joseph Lauriello
  • Patent number: 9881813
    Abstract: A mounting structure, including: a first component that has a first bump; a second component that has a second bump; a mounting component that has a primary mounting surface and a secondary mounting surface; a first solder that connects an electrode on the primary mounting surface and the first bump; a second solder that connects an electrode on the secondary mounting surface and the second bump; and a reinforcing resin that covers a part of the first solder and that is not in contact with the primary mounting surface.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hirohisa Hino, Yasuhiro Suzuki, Masato Mori, Naomichi Ohashi
  • Patent number: 9817271
    Abstract: A display panel is provided. The display panel includes a first substrate, a second substrate, a liquid crystal layer, a plurality of thin film transistors, a plurality of metal wires, a protection layer, a first alignment layer, and a plurality of agglomerates. The first substrate has at least a display area and a non-display area located outside the display area. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The thin film transistors and the metal wires are disposed on the first substrate, the protection layer overlaying at least a portion of the metal wires. The first alignment layer is disposed on the protection layer for exposing a first surface of the protection layer. The agglomerates are disposed on at least a portion of the first surface.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 14, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Chu-Chun Cheng, Yu-Ju Chen, I-Hua Huang, Wan-Shan Yang, Chun-Teng Chen, Chen-Kuan Kao, Kuei-Ling Liu
  • Patent number: 9807890
    Abstract: The present disclosure is related to electronic modules for electronic components and methods for manufacturing the same. In one embodiment, an electronic module is formed using a first substrate having a first component area and a second substrate having a second component area. One or more electronic components may be attached to both the first component area and the second component area. The second substrate is mounted over the first substrate such that the second component area faces the first component area. An overmold covers the first component area and the second component area so as to cover the electronic components on both the first component area and the second component area. In this manner, the number of electronic components within the electronic module that can be mounted on an area of a printed circuit board (PCB) is increased.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 31, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Thong Dang, Mohsen Haji-Rahim, Joseph Byron Bullis
  • Patent number: 9804592
    Abstract: An optimization device, that optimizes a process procedure for each of a plurality of process machines in a substrate process system in which circuit substrates can be transported on two paths, including a first process for setting a process procedure for each of the process machines so as to optimize a total process time that is the sum of a process time for each of the plurality of process machines for a circuit substrate being transported on one of the two paths, and a process time for each of the plurality of process machines for a circuit substrate being transported on the other of the two paths; and a second process for setting a process procedure for each of the process machines so as to optimize the process times.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: October 31, 2017
    Assignee: FUJI MACHINE MFG. CO., LTD.
    Inventor: Kazuya Fukao
  • Patent number: 9796018
    Abstract: Provided is a silver powder which has an appropriate viscosity range at the time of paste production, can be easily kneaded, and prevents the occurrence of flakes. The silver powder to be used has a specific surface area ratio SAB/SAS of 0.5 to 0.9, wherein SAB is a specific surface area measured by the BET method, and SAS is a specific surface area calculated from a mean primary-particle diameter DS measured with a scanning electron microscope. Furthermore, the silver powder preferably has a degree of aggregation of 1.5 to 5.0, the degree being obtained in such a manner that a volume median diameter D50 measured by laser diffraction scattering is divided by the foregoing Ds.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 24, 2017
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventors: Toshiaki Terao, Yuji Kawakami
  • Patent number: 9791900
    Abstract: An expansion card mounting assembly includes a mounting structure and a circuit board coupled to the mounting structure. Expansion cards are mounted on a top side and a bottom side of the circuit board and secured at opposite ends by a moveable plate of the expansion card mounting assembly. The mounting structure includes an opening along a length of the expansion cards that allows air to flow over the expansion cards in multiple directions including a vertical direction. The moveable plate and mounting structure are configured to allow a position of the moveable plate on the mounting structure to be adjusted to mount expansion cards having different lengths in the expansion card mounting assembly.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 17, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Strickland Beall, Felipe Enrique Ortega Gutierrez, Brandyn David Giroux, Darin Lee Frink, Jason Alexander Harland, Roey Rivnay, Max Jesse Wishman, Yangtzu Lee Andrew Lee
  • Patent number: 9755341
    Abstract: A flexible printed circuit board (FPCB) connector includes a housing having a first mating interface configured for mating with a first FPCB and a second mating interface configured for mating with a second FPCB. A plurality of jumper conductors are held by the housing. The jumper conductors have first mating ends at the first mating interface being configured for mating with the first FPCB and the jumper conductors having second mating ends at the second mating interface being configured for mating with the second FPCB. The first mating interface is configured to be mated to the first FPCB at any location along a length of the first FPCB including locations remote from an end of the first FPCB.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 5, 2017
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Kyle Gary Annis, Dustin Carson Belack
  • Patent number: 9748217
    Abstract: A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 29, 2017
    Assignee: The University of Tokyo
    Inventor: Takayuki Ohba
  • Patent number: 9713258
    Abstract: An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Young Hoon Kwark
  • Patent number: 9692100
    Abstract: A flat cable includes a plurality of resin layers that are flexible and stacked together, a line conductor, and grounding conductors. The flat cable includes a triplate line in which both surfaces of the line conductor oppose the corresponding grounding conductors, and a microstrip line in which only one of the surfaces of the line conductor opposes the corresponding grounding conductor. A width of the line conductor in the microstrip line is greater than a width of the line conductor in the triplate line, and the flat cable is bent at a position where the microstrip line is provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 27, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takahiro Baba, Nobuo Ikemoto
  • Patent number: 9691634
    Abstract: A method for creating electrically or thermally conductive vias in both vertical and horizontal orientations in a dielectric material has the steps of: (a) depositing a powder comprising metallic particles on a planar surface of a dielectric material having through or blind vias; (b) drying the deposited powder of metallic particles; (c) polishing the powder of metallic powders into the through or blind vias; (d) repeating steps (a)-(c) on a reverse side of the dielectric material; and (e) repeating steps (a)-(d) until no unfilled vias are detected.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 27, 2017
    Assignee: Abexl Inc.
    Inventor: Fred Koelling
  • Patent number: 9673139
    Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 6, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshige Hirano, Michinari Tetani, Masakazu Hamada, Nobuaki Tarumi
  • Patent number: 9648758
    Abstract: A method for producing a circuit board comprising the following steps:—providing at least one first element of the circuit board to be produced, more particularly a multilayer core element;—applying an adhesion-preventing material to a region of the first element to be subsequently exposed;—applying at least one additional layer to the first element;—connecting the first element and the at least one additional layer; and—removing a portion of the additional layer to expose the region of the first element, wherein in the additional layer corresponding to the portion to be subsequently removed, the material of the additional layer is cut through on at least one edge of the portion to be subsequently removed.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 9, 2017
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Siegfried Götzinger, ShuYing Yao, Mikael Tuominen, Beck Han
  • Patent number: 9627799
    Abstract: A cable connector comprises a mating board, a plurality of cables, an organizer and a binding material. The mating board comprises a board body and a plurality of conductive portions provided on the board body. The cables are respectively electrically connected to the conductive portions. The organizer comprises an upper cap, a lower cap and a spacer interposed between the upper cap and the lower cap. The upper cap, the lower cap and the spacer cooperatively define a filling space that includes upper cable passages and lower cable passages respectively extending along the front-rear direction and respectively receiving the cables so as to allow the plurality of cables to pass through the filling space. The binding material is filled in the filling space of the organizer and fixes the plurality of cables to the organizer.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 18, 2017
    Assignee: Molex, LLC
    Inventors: Ting Chang Tseng, Yao Ting Wang
  • Patent number: 9627785
    Abstract: An electrical distribution center includes a bracket. A mounting plate is secured to the bracket and includes an aperture having a perimeter. An electrical connector is disposed within the aperture and includes locating structure that is captured between the perimeter and the bracket to align and to retain the electrical connector relative to the bracket. One locating structure includes spring arms that cooperate with notches provided by the aperture. Another locating structure includes an edge captured beneath a periphery of the aperture. The mounting plate is snap-fit to the bracket over the electrical connectors.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 18, 2017
    Assignee: Delphi Technologies, Inc.
    Inventors: Gustavo Eric Melchor Saucedo, Jesus R. Morales