Assembling Bases Patents (Class 29/830)
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Patent number: 9027238Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.Type: GrantFiled: December 6, 2011Date of Patent: May 12, 2015Assignee: Ibiden Co., Ltd.Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
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Patent number: 9027247Abstract: A method and structure for forming an ink jet printhead can include the use of a transfer pad to transfer an adhesive solution to an ink jet printhead substrate. The adhesive solution can be placed within a patterned recess of a cliché and then an upper surface of the adhesive solution can be gelled. A surface of the transfer pad contacts the gelled upper surface and transfers the adhesive solution to the ink jet printhead substrate. During the transfer, a lower surface of the adhesive solution gels. During contact with the ink jet printhead substrate, the gelled lower surface adheres to the ink jet printhead substrate while the gelled upper surface releases from the transfer pad.Type: GrantFiled: October 22, 2012Date of Patent: May 12, 2015Assignee: Xerox CorporationInventors: Xuejin Wen, Mark A. Cellura
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Publication number: 20150124415Abstract: Embodiments of the present application relate generally to personal electronics, portable electronics, wearable electronics, and more specifically to a structure and method for a protective covering for a wearable device. Interior and exterior structures of the wearable device are configured to be flexed into a configuration and to retain the configuration after the flexing. Interior structure may include a first flexible substrate having a first relaxation structure and a second flexible substrate having a second relaxation structure. Components or other structures may be connected with the first and/or second flexible substrates. The first and second relaxation structures may be positioned relative to each other to define a flexure point. At least one flexible and electrically non-conductive cover, that may undergo shirking, may conformally cover at least a portion of the interior structure. A flexible overmolding may be formed over the cover and may comprise the exterior structure.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: AliphComInventors: Dileep Goyal, Andrew Dawn, William Maginn, Hari Chakravarthula
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Publication number: 20150124420Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.Type: ApplicationFiled: November 4, 2013Publication date: May 7, 2015Inventors: Alexander Heinrich, Peter Scherl, Magdalena Hoier, Hans-Joerg Timme
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Patent number: 9021693Abstract: A method of manufacturing a printed circuit board, including: applying a dry film on a carrier and then patterning the dry film to form holes for forming metal bumps; forming an upper circuit layer including metal bumps charged in the holes and connection pads on the dry film; forming an insulation layer on the dry film; forming a build-up layer including a lower circuit layer on the insulation layer; removing the carrier; and removing the dry film.Type: GrantFiled: May 22, 2012Date of Patent: May 5, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Yong An, Jae Joon Lee
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Patent number: 9021690Abstract: A method of manufacturing a printed circuit board having a buried solder bump, including: preparing a carrier on which a circuit layer, a solder bump, and a circuit pattern formed on the solder bump are formed; pressing the carrier into an insulating layer so that the circuit layer, the solder bump and the circuit pattern are buried in the insulating layer; and removing the carrier.Type: GrantFiled: September 9, 2011Date of Patent: May 5, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Myung Sam Kang
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Patent number: 9021691Abstract: A method for introducing electrical insulations in a printed circuit board includes selectively introducing groove-shaped recesses between different regions of an electrically conductive layer on a substrate along a machining path using a thermal energy input such that end portions of each of the recesses or different ones of the recesses are joined to one another. The end portions are introduced parallel to one another without overlap such that a strip-shaped region of the conductive layer is initially retained between the end portions so as to insulate the different regions.Type: GrantFiled: March 23, 2011Date of Patent: May 5, 2015Assignee: LPKF Laser & Electronics AGInventor: Jan van Aalst
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Patent number: 9021692Abstract: A printed wiring board includes a resin insulation layer having a first surface and a second surface on an opposite side of the first surface, the resin insulation layer having an opening for a first via conductor, a pad formed on the first surface of the resin insulation layer and provided to mount an electronic component, a first conductive circuit formed on the second surface of the resin insulation layer, and a first via conductor formed in the opening and connecting the pad and the first conductive circuit. The pad has an embedded portion embedded in the resin insulation layer and a protruding portion protruding from the resin insulation layer, and the embedded portion has an external shape which is greater than an external shape the protruding portion.Type: GrantFiled: November 29, 2011Date of Patent: May 5, 2015Assignee: Ibiden Co., Ltd.Inventors: Satoru Kawai, Kenji Sakai, Liyi Chen
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Patent number: 9022602Abstract: Modular multichannel light sources connector systems and methods are provided. A lighting assembly includes substrates, each with a respective plurality of ports and conductive path configurations. Each path configuration includes a plurality of conductive paths between the respective plurality of ports. At least two conductive path configurations are the same. A connector couples one of a plurality of first ports on a first substrate to one of a plurality of second ports on a second substrate. A multichannel power supply's outputs are each coupled to an associated conductive path on the first substrate. A first light source is coupled to two conductive paths on the first substrate, and to a first output. A second light source is coupled to two conductive paths on the second substrate, corresponding to the conductive paths on the first substrate, and to a second output, different from the first output.Type: GrantFiled: June 24, 2013Date of Patent: May 5, 2015Assignee: OSRAM SYLVANIA Inc.Inventors: Nicholas Lekatsas, Biju Antony, David Lidrbauch
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Publication number: 20150117022Abstract: The present invention is directed to the use of light emitting diode (LED) lighting in flexible strips, where the color of the lighting emitted from the flexible strip is consequential to the encapsulation process and heat from the lights is adequately dissipated.Type: ApplicationFiled: October 24, 2014Publication date: April 30, 2015Inventor: Ariel Meir
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Publication number: 20150116629Abstract: A method for manufacturing an electronic device is provided, including the following steps. First, an outer frame is provided, wherein the outer frame comprises the first frame member and the second frame member. Next, the first frame member is connected to the second frame member by welding to form a connected structure, wherein a welded portion is formed between the first frame member and the second frame member. Then, a punch pin and a punch base are provided. Next, the connected structure is placed on the punch base. Finally, the connected structure is punched by the punch pin.Type: ApplicationFiled: March 14, 2014Publication date: April 30, 2015Applicant: Wistron Corp.Inventor: Shu-hua DAI
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Patent number: 9018539Abstract: The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.Type: GrantFiled: June 4, 2012Date of Patent: April 28, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Han Ul Lee
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Patent number: 9015930Abstract: Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.Type: GrantFiled: April 28, 2010Date of Patent: April 28, 2015Assignee: Nikon CorporationInventors: Hidehiro Maeda, Satoshi Katagiri
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Patent number: 9015932Abstract: It is to provide an electronic component connecting method capable of performing dehumidification within a short time without giving a thermal influence to an electronic component which has already been mounted on a wiring board. When a first connection terminal group 5 formed on a connection area 3 of a rigid board 1 is connected to a flexible board 2 where a second connection terminal group 6 has been formed by employing a thermosetting resin in an electrically conductive manner, since a connection area 3 which is heated in a step for thermally hardening the thermosetting resin is locally preheated, moisture, and oils and fats contained in the connection area 3 among such moisture, and oils and fats, which have been absorbed in the rigid board 1 are dehumidified. Thereafter, the thermosetting resin interposed between the first connection terminal group 5 and the second connection terminal group 6 is thermally hardened.Type: GrantFiled: December 26, 2007Date of Patent: April 28, 2015Assignee: Panasonic CorporationInventors: Tadahiko Sakai, Hideki Eifuku
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Publication number: 20150109083Abstract: A base is a platform that supports a component off the ground in a solar energy installation. The specific configuration of a base can vary based on the intended component, for example whether it holds a transformer or power component. Multiple bases are mechanically and/or electrically connected to form a system of bases in the field. Proper placement of bases and engagement of those bases is facilitated by mating alignment mechanisms such that one base can be lowered “fit” with another. A method of positioning components includes positioning a base and aligning and lowering a second base alongside the first such that the bases engage.Type: ApplicationFiled: October 13, 2014Publication date: April 23, 2015Inventor: Dean Solon
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Publication number: 20150107101Abstract: Fabricating preassembled optoelectronic interconnect structures is provided, which have an optical waveguide link with first and second optoelectronic circuits attached to first and second ends of the waveguide link. The optoelectronic circuits include active optical componentry which facilitates optical signal communication across the optical waveguide link. Further, first and second pluralities of electrical contacts are associated with the first and second optoelectronic circuits, respectively, to facilitate electrically, operatively connecting the interconnect structure between first and second components of an electronic assembly as, for instance, a single, field-replaceable unit. The first and second components of the electronic assembly may be, for instance, stacked electronic components of the electronic assembly, or laterally offset components of a substantially planar electronic assembly.Type: ApplicationFiled: November 11, 2014Publication date: April 23, 2015Inventors: Casimer M. DeCUSATIS, Rajaram B. KRISHNAMURTHY, Michael ONGHENA, Anuradha RAO
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Patent number: 9013882Abstract: A high-frequency module has a multilayer board formed by laminating a plurality of sheets made of a thermoplastic resin material and subjecting the laminated sheets to thermocompression bonding, and an IC chip placed in a cavity provided in the multilayer board. A gap is provided between a side of the IC chip and an inner wall of the cavity. The multilayer board includes a via-hole conductor provided near the inner wall of the cavity for preventing the resin sheets from being softened and flowing into the cavity upon thermocompression bonding.Type: GrantFiled: July 11, 2014Date of Patent: April 21, 2015Assignee: Murata Manufacturing Co., Ltd.Inventors: Naoki Gouchi, Takahiro Baba
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Patent number: 9009954Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes forming the Z-directed component in a cavity formed by a constraining material that defines the outer shape of the Z-directed component. The constraining material is dissipated to release the Z-directed component from the constraining material and the Z-directed component is fired.Type: GrantFiled: June 20, 2012Date of Patent: April 21, 2015Assignee: Lexmark International, Inc.Inventors: Keith Bryan Hardin, Paul Kevin Hall, Zachary Charles Nathan Kratzer, Qing Zhang
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Publication number: 20150103541Abstract: This invention relates to an optical device, more particularly, to a method for manufacturing an optical device substrate in which an optical device can be arranged in a various manner.Type: ApplicationFiled: October 14, 2014Publication date: April 16, 2015Inventors: Bum Mo Ahn, Seung Ho Park
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Publication number: 20150103525Abstract: A method of making a light emitting diode (LED) lamp is disclosed. Included are steps of: providing a metal heat sink having a cylindrical portion formed with flat planar surfaces extending longitudinally around the outer surface; providing flat LED boards that are attached to the flat planar surfaces; providing a circular LED board mounted to the top end of the cylindrical portion; providing a turret connector board with electrical connection ports to electrically join the LED boards; providing a driver circuit board and electrically connecting it to the turret connector board; connecting the flat LED boards to the driver circuit board; securing the circular LED board to the top open-end; and securing the flat LED boards to the flat planar surfaces. Optional steps include: providing a mounting plate of heat conducting metal; applying thermal compound; providing and installing a transparent cover; providing and attaching a mount to the incandescent lamp.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: LED Waves, Inc.Inventors: Larry W. Rowley, Joel Slavis
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Patent number: 9003648Abstract: The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.Type: GrantFiled: December 28, 2007Date of Patent: April 14, 2015Assignee: Ormet Circuits, Inc.Inventor: Ken Holcomb
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Patent number: 9003649Abstract: A fluid cooled electrical assembly that includes a metal box, having a bottom wall, side walls and a top wall. A set of straight-edged pins, each smaller than 3 mm across in widest dimension, extend down from the top wall and up from the bottom wall. Also, electrical components are mounted on top of the top wall and on bottom of the bottom wall.Type: GrantFiled: January 25, 2012Date of Patent: April 14, 2015Assignee: Maxq Technology, LLCInventors: Guillermo L. Romero, Joe L Martinez, Jr.
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Patent number: 9003653Abstract: A method for producing a ceramic multilayer circuit system, and a corresponding multilayer circuit system are provided. An embodiment of the method includes sequential deposition of a plurality of circuit layers of the multilayer circuit system on a substrate using a powder spray method; pressing of the deposited plurality of circuit layers; and thermal sintering of the pressed plurality of circuit layers. The individual circuit layers have electrically conductive areas made of at least one conductive material and electrically insulating areas made of at least one ceramic material.Type: GrantFiled: February 7, 2008Date of Patent: April 14, 2015Assignee: Robert Bosch GmbHInventors: Juergen Egerter, Walter Roethlingshoefer, Markus Werner
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Publication number: 20150099948Abstract: A flexible embedded sensor array includes a first substrate, an electrically conductive pad disposed on at least a portion of the first substrate, and a plurality of sensors disposed on at least a portion of electrically conductive pads. Further, the flexible embedded sensor array includes an electrically non-conductive adhesive material disposed in proximity to one or more of the plurality of sensors, a second substrate, and an electrical contact disposed between at least a portion of the sensor and at least a portion of the second substrate.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: General Electric CompanyInventors: Christopher James Kapusta, Eric Patrick Davis, Jason Harris Karp
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Patent number: 8997342Abstract: A method of fabricating a multilayer electronic support structure comprising electroplating copper substructures, laying a dielectric pre-preg comprising a polymer resin over the copper substructures, and pressing to pressures of 200 to 600 PSI against a release film having a higher hardness than the resin of the prepreg but a lower hardness than the cured resin, and heating through a curing cycle while maintaining pressure.Type: GrantFiled: October 15, 2012Date of Patent: April 7, 2015Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang
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Patent number: 8997343Abstract: A method for manufacturing multilayer printed circuit board includes step below. A metal substrate is provide, the metal substrate includes a number of substrate unit. A first insulating layer is formed on one surface of the metal substrate. The first insulating layer has a number of first through holes. An electrically conductive circuit is formed in each substrate unit. A second insulating layer is formed on the other surface of the metal substrate. The second insulating layer has a number of second through holes. A first metal cylinder is formed in a first through hole and a second metal cylinder is formed in a second through hole. The number of substrate units are folded and laminated, the connected and aligned first metal cylinder and the second metal cylinder communicates the electrically conductive circuits.Type: GrantFiled: May 17, 2011Date of Patent: April 7, 2015Assignee: Zhen Ding Technology Co., Ltd.Inventor: Chien-Pang Cheng
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Patent number: 8997344Abstract: A method for manufacturing an interposer including forming a first insulating layer comprising an inorganic material on a supporting substrate, forming a first wire in the first insulating layer, forming a second insulating layer on a first side of the first insulating layer, forming a second wire with a longer wire length and a greater thickness than the first wire on the second insulating layer, and removing the supporting substrate.Type: GrantFiled: July 15, 2011Date of Patent: April 7, 2015Assignee: Ibiden Co., Ltd.Inventors: Hajime Sakamoto, Shuichi Kawano, Daiki Komatsu, Hiroshi Segawa
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Patent number: 8997340Abstract: A method of manufacturing an insulating sheet, the method including providing a reinforcement material having a thermoplastic resin layer stacked thereon; stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate; and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate.Type: GrantFiled: September 21, 2011Date of Patent: April 7, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
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Publication number: 20150089804Abstract: Electrified access-control technology devices for a door, particularly electrified locks for a door, having embedded circuitry therein, and methods of making the same. One or more printed circuit boards (PCBs) having various electronic circuitry are secured inside a housing that encases an access-control device, particularly a lock, for a door. The one or more PCB(s) may be embedded on an internal surface of the housing such that the embedded PCB resides inside the housing along with the lock itself. The embedded PCB(s) avoid interference of both any working components of the lock inside the housing and any openings residing in the housing.Type: ApplicationFiled: December 10, 2014Publication date: April 2, 2015Inventors: Daniel J. Picard, Robert C. Hunt, Scott B. Lowder
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Patent number: 8991039Abstract: A process for manufacturing a multilayer article, the article comprising two crosslinked semiconductive layers separated by and bonded to an insulation layer, the semiconductive layers formed from a peroxide-crosslinkable olefin elastomer and the insulation layer comprising composition comprising a silane-grafted olefinic elastomer, the process comprises the steps of: (A) injecting the silane-grafted olefinic elastomer between the two crosslinked semiconductive layers so as to have direct contact with each semiconductive layer, and (B) crosslinking the silane-grafted olefinic elastomer in the absence of a peroxide catalyst.Type: GrantFiled: September 21, 2011Date of Patent: March 31, 2015Assignee: Dow Global Technologies LLCInventors: Mohamed Esseghir, Jeffrey M. Cogen, Saurav S. Sengupta
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Patent number: 8991043Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.Type: GrantFiled: July 19, 2012Date of Patent: March 31, 2015Assignee: Subtron Technology Co., Ltd.Inventor: Chao-Min Wang
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Publication number: 20150085461Abstract: A method for manufacturing a combined wiring board includes preparing multiple wiring boards, preparing a metal frame having opening portions which accommodate the boards, respectively, positioning the boards in the opening portions of the frame, respectively, and forming multiple crimped portions in the frame by plastic deformation such that the sidewalls of the boards bond to sidewalls of the opening portions in the frame. The preparing of the boards includes forming the sidewalls of the boards such that when the boards are positioned in the opening portions of the frame, the sidewalls of the boards form wide-space portions and narrow-space portions with respect to the sidewalls of the opening portions in the frame, and the forming of the crimped portions includes generating the deformation such that the sidewalls of the opening portions in the frame abut the narrow-space portions of the boards before the wide-space portions of the boards.Type: ApplicationFiled: September 22, 2014Publication date: March 26, 2015Applicant: IBIDEN CO., LTD.Inventors: Teruyuki ISHIHARA, Michimasa TAKAHASHI
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Publication number: 20150083471Abstract: A combined wiring board includes a metal frame having multiple opening portions, and multiple wiring boards accommodated in the opening portions in the metal frame, respectively. The opening portions in the metal frame have side walls having holding portions such that the holding portions hold the wiring boards in the opening portions in the metal frame, and the metal frame has slit portions adjacent to the holding portions and connecting portions connecting the slit portions to the opening portions.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Applicant: IBIDEN CO., LTD.Inventors: Teruyuki Ishihara, Michimasa Takahashi
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Patent number: 8984746Abstract: A method for the manufacture of a circuit board containing a component and circuit board containing a component. The invention is based on first manufacturing an intermediate product, which contains the insulator layer of the circuit board and the components, which are set in place inside the insulator layer in such a way that the contact elements of the components face the surface of the intermediate product. After this, the intermediate product is transferred to the circuit-board manufacturing line, on which a suitable number of conductor-pattern layers and, if necessary, insulator layers are manufactured on one or both sides of the intermediate product, in such a way that, when manufacturing the first conductor-pattern layer, the conductor material forms an electrical contact with the contact elements of the components. Alternatively, stages can also be performed on a single manufacturing line.Type: GrantFiled: March 15, 2007Date of Patent: March 24, 2015Assignee: GE Embedded Electronics OyInventors: Risto Tuominen, Petteri Palm, Antti Lihola
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Patent number: 8984748Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer.Type: GrantFiled: June 28, 2010Date of Patent: March 24, 2015Assignee: Hsio Technologies, LLCInventor: James Rathburn
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Publication number: 20150077963Abstract: A printed wiring board includes a wiring board, and multiple posts formed on the wiring board and positioned to mount a second printed wiring board onto the wiring board. Each of the metal posts has a first surface connected to the wiring board, a second surface formed to connect the second printed wiring board, and a side surface between the first surface and the second surface, and the side surface of each of the metal posts forms a curved surface.Type: ApplicationFiled: September 19, 2014Publication date: March 19, 2015Applicant: IBIDEN CO., LTD.Inventors: Takema ADACHI, Yuzo KAIDA
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Patent number: 8978247Abstract: A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.Type: GrantFiled: May 22, 2012Date of Patent: March 17, 2015Assignee: Invensas CorporationInventors: Se Young Yang, Cyprian Emeka Uzoh, Michael Huynh, Rajesh Katkar
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Patent number: 8978217Abstract: A package manufacturing method where a base substrate and a lid substrate, at least one having a through-hole, are anodically bonded to each other using a jig having a communication-hole and arranged in a vacuum chamber to laminate the lid substrate to the base substrate and thereby form a bonded body having a plurality of cavities, each of which includes an electronic part sealed therein. The through-hole and the communication-hole are aligned with each other inside the vacuum chamber, such that gas within the cavities can escape through the through-hole and the communication-hole during bonding. A plurality of packages are formed by cutting the bonded body for every one of the plurality of cavities.Type: GrantFiled: March 26, 2012Date of Patent: March 17, 2015Assignee: Seiko Instruments Inc.Inventor: Takeshi Sugiyama
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Patent number: 8981232Abstract: A multi-layer substrate includes a ground structure, a plurality of dielectric layers on the ground structure and a plurality of conductive layers separating the plurality of dielectric layers. The conductive layers include a first conductive layer and a second conductive layer and a connection electrically coupling the first conductive layer and the second conductive layer. The first conductive layer and the ground structure are configured to define a first parasitic capacitance there between and the first conductive layer and the second conductive layer are configured to define a second, negating parasitic capacitance there between.Type: GrantFiled: June 1, 2012Date of Patent: March 17, 2015Assignee: Aerojet Rocketdyne of DE, Inc.Inventors: Thomas A. Hertel, Erich H. Soendker, Horacio Saldivar
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Patent number: 8974626Abstract: A method of manufacturing a micro structure, includes the steps of: preparing separate first and second substrates, the first substrate having a first surface on which a first structural body having a first height and a second structural body having a second height greater than the first height of the first structural body are arranged, the second substrate having a second surface; then placing the first and second substrates to cause the first and second surfaces to face each other across the first and second structural bodies; and then bonding the first and second substrates to each other while compressing the second structural body in a height direction thereof between the first and second surfaces to cause the second structural body to have a height defined by the first structural body.Type: GrantFiled: March 22, 2011Date of Patent: March 10, 2015Assignee: FUJIFILM CorporationInventors: Takamichi Fujii, Akihiro Mukaiyama
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Patent number: 8973259Abstract: A method for manufacturing a multilayered printed circuit board including forming a first insulating resin substrate having a metal layer substantially corresponding to dimensions of a semiconductor device, forming a second insulating resin substrate, forming a recess extending to the metal layer of the first insulating resin substrate such that a surface of the metal layer is exposed, accommodating the semiconductor device in the recess such that the semiconductor device is mounted on the surface of the metal layer, and forming a resin insulating layer on the first insulating resin substrate such that the semiconductor device accommodated in the recess is covered.Type: GrantFiled: September 9, 2011Date of Patent: March 10, 2015Assignee: Ibiden Co., Ltd.Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
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Patent number: 8973257Abstract: Methods for building a neutron detector are disclosed, in which the neutron detector comprises at least two conductive cathode sheets lying parallel to one another and coated with neutron reactive material on at least one side thereof; dielectric material separating the cathode sheets and covering less than about 80% of their surface area; and a plurality of anode wires lying generally parallel to the cathode sheets and separated from them by the dielectric, with the distance between adjacent anode wires being no more than twenty times the distance between said cathode sheets. The cathode sheets may be flat or curved; they may be separate plates or they may be successive folds or windings of a single folded or spiral-shaped metal sheet.Type: GrantFiled: September 15, 2011Date of Patent: March 10, 2015Assignee: Material Innovations, Inc.Inventors: Andrew C. Stephan, Vincent D. Jardret
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Publication number: 20150062802Abstract: Heat pipe assemblies for Information Handling Systems (IHSs). In some embodiments, an IHS may comprise a motherboard including a Central Processing Unit (CPU); a cooling system coupled to the motherboard, the cooling system including a heat pipe, the CPU coupled to a first side of the heat pipe; and a daughterboard coupled to the motherboard and including a Graphics Processing Unit (GPU) coupled to a second side of the heat pipe. In other embodiments, a method may include providing a motherboard including a CPU; coupling a cooling system to the motherboard, the cooling system including a heat pipe, the CPU coupled to a first side of the heat pipe; and coupling a daughterboard to the motherboard, the daughterboard including a GPU coupled to a second side of the heat pipe.Type: ApplicationFiled: September 5, 2013Publication date: March 5, 2015Applicant: Dell Products, L.P.Inventors: David William Grunow, Daniel William Kehoe, Matthew B. Mendelow
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Publication number: 20150062855Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: RAYTHEON COMPANYInventors: Peter D. Morico, John D. Walker
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Publication number: 20150060655Abstract: A method of constructing an ion guide is disclosed comprising providing an elongated spine member and a plurality of plates. Each plate comprises an aperture therethrough for receiving the spine member and at least one electrode for use in guiding ions. The apertures of the plates are arranged around the spine member and the plates are arranged along the spine member. The plates are then locked in position on the spine member such that the plates are fixed axially with respect to the spine member and so that the electrodes of the plates are arranged so as to form an array of electrodes for use in guiding ions.Type: ApplicationFiled: March 15, 2013Publication date: March 5, 2015Inventors: John Richard Garside, Martin Raymond Green, Daniel James Kenny, Jeffrey Ellis Lockett, Richard Barrington Moulds
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Publication number: 20150062900Abstract: A lighting module including an electronic board adapted to accommodate a plurality of light emitting diodes (LEDs) is provided. The lighting module includes a metallic base having cavities adapted to receive adapters. The adapters include a connector body provided with: a) means adapted to accommodate electrical contacts for interconnection to the electronic board; b) means adapted to accommodate gaskets for shielding the contacts; and c) means for the mechanical locking of the adapters on the module.Type: ApplicationFiled: September 2, 2014Publication date: March 5, 2015Inventor: Stefano FERRO
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Publication number: 20150062933Abstract: Disclosed is a substrate for mounting light emitting element with a high positional accuracy and a method of fixing the substrate. A substrate for mounting light emitting element defines a first recess and a second recess in first side in a plan view. The first recess is defined by two corner portions and a straight portion which connects the two corner portions, and the second recess further includes at least two straight portions each narrowing toward the inner end portion.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Inventors: Toshiyuki YAGI, Toshihiko AIZAWA
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Patent number: 8966747Abstract: A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation with the mold forming part of the finished product, e.g. providing heat sink fins or a surface mount solderable surface. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features such as registration features accurately locating the circuit board within the mold cavity, interlocking contours for structural integrity of the singulated module, contours to match component shapes and sizes enhancing heat removal from internal components and reducing the required volume of encapsulant, clearance channels providing safety agency spacing and setbacks for the interconnects.Type: GrantFiled: May 11, 2011Date of Patent: March 3, 2015Assignee: VLT, Inc.Inventors: Patrizio Vinciarelli, Michael B. Lafleur, Sean Timothy Fleming, Rudolph Mutter, Andrew T. D'Amico
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Patent number: 8966750Abstract: A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.Type: GrantFiled: June 23, 2011Date of Patent: March 3, 2015Assignee: Ibiden Co., Ltd.Inventors: Tomoyuki Ikeda, Naoaki Fujii, Seiji Izawa
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Patent number: 8966746Abstract: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.Type: GrantFiled: April 20, 2011Date of Patent: March 3, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu