Assembling Bases Patents (Class 29/830)
  • Publication number: 20150089804
    Abstract: Electrified access-control technology devices for a door, particularly electrified locks for a door, having embedded circuitry therein, and methods of making the same. One or more printed circuit boards (PCBs) having various electronic circuitry are secured inside a housing that encases an access-control device, particularly a lock, for a door. The one or more PCB(s) may be embedded on an internal surface of the housing such that the embedded PCB resides inside the housing along with the lock itself. The embedded PCB(s) avoid interference of both any working components of the lock inside the housing and any openings residing in the housing.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventors: Daniel J. Picard, Robert C. Hunt, Scott B. Lowder
  • Patent number: 8991039
    Abstract: A process for manufacturing a multilayer article, the article comprising two crosslinked semiconductive layers separated by and bonded to an insulation layer, the semiconductive layers formed from a peroxide-crosslinkable olefin elastomer and the insulation layer comprising composition comprising a silane-grafted olefinic elastomer, the process comprises the steps of: (A) injecting the silane-grafted olefinic elastomer between the two crosslinked semiconductive layers so as to have direct contact with each semiconductive layer, and (B) crosslinking the silane-grafted olefinic elastomer in the absence of a peroxide catalyst.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 31, 2015
    Assignee: Dow Global Technologies LLC
    Inventors: Mohamed Esseghir, Jeffrey M. Cogen, Saurav S. Sengupta
  • Patent number: 8991043
    Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Chao-Min Wang
  • Publication number: 20150083471
    Abstract: A combined wiring board includes a metal frame having multiple opening portions, and multiple wiring boards accommodated in the opening portions in the metal frame, respectively. The opening portions in the metal frame have side walls having holding portions such that the holding portions hold the wiring boards in the opening portions in the metal frame, and the metal frame has slit portions adjacent to the holding portions and connecting portions connecting the slit portions to the opening portions.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Michimasa Takahashi
  • Publication number: 20150085461
    Abstract: A method for manufacturing a combined wiring board includes preparing multiple wiring boards, preparing a metal frame having opening portions which accommodate the boards, respectively, positioning the boards in the opening portions of the frame, respectively, and forming multiple crimped portions in the frame by plastic deformation such that the sidewalls of the boards bond to sidewalls of the opening portions in the frame. The preparing of the boards includes forming the sidewalls of the boards such that when the boards are positioned in the opening portions of the frame, the sidewalls of the boards form wide-space portions and narrow-space portions with respect to the sidewalls of the opening portions in the frame, and the forming of the crimped portions includes generating the deformation such that the sidewalls of the opening portions in the frame abut the narrow-space portions of the boards before the wide-space portions of the boards.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Teruyuki ISHIHARA, Michimasa TAKAHASHI
  • Patent number: 8984746
    Abstract: A method for the manufacture of a circuit board containing a component and circuit board containing a component. The invention is based on first manufacturing an intermediate product, which contains the insulator layer of the circuit board and the components, which are set in place inside the insulator layer in such a way that the contact elements of the components face the surface of the intermediate product. After this, the intermediate product is transferred to the circuit-board manufacturing line, on which a suitable number of conductor-pattern layers and, if necessary, insulator layers are manufactured on one or both sides of the intermediate product, in such a way that, when manufacturing the first conductor-pattern layer, the conductor material forms an electrical contact with the contact elements of the components. Alternatively, stages can also be performed on a single manufacturing line.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: March 24, 2015
    Assignee: GE Embedded Electronics Oy
    Inventors: Risto Tuominen, Petteri Palm, Antti Lihola
  • Patent number: 8984748
    Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 24, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Publication number: 20150077963
    Abstract: A printed wiring board includes a wiring board, and multiple posts formed on the wiring board and positioned to mount a second printed wiring board onto the wiring board. Each of the metal posts has a first surface connected to the wiring board, a second surface formed to connect the second printed wiring board, and a side surface between the first surface and the second surface, and the side surface of each of the metal posts forms a curved surface.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 19, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Takema ADACHI, Yuzo KAIDA
  • Patent number: 8978247
    Abstract: A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 17, 2015
    Assignee: Invensas Corporation
    Inventors: Se Young Yang, Cyprian Emeka Uzoh, Michael Huynh, Rajesh Katkar
  • Patent number: 8978217
    Abstract: A package manufacturing method where a base substrate and a lid substrate, at least one having a through-hole, are anodically bonded to each other using a jig having a communication-hole and arranged in a vacuum chamber to laminate the lid substrate to the base substrate and thereby form a bonded body having a plurality of cavities, each of which includes an electronic part sealed therein. The through-hole and the communication-hole are aligned with each other inside the vacuum chamber, such that gas within the cavities can escape through the through-hole and the communication-hole during bonding. A plurality of packages are formed by cutting the bonded body for every one of the plurality of cavities.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 17, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Takeshi Sugiyama
  • Patent number: 8981232
    Abstract: A multi-layer substrate includes a ground structure, a plurality of dielectric layers on the ground structure and a plurality of conductive layers separating the plurality of dielectric layers. The conductive layers include a first conductive layer and a second conductive layer and a connection electrically coupling the first conductive layer and the second conductive layer. The first conductive layer and the ground structure are configured to define a first parasitic capacitance there between and the first conductive layer and the second conductive layer are configured to define a second, negating parasitic capacitance there between.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 17, 2015
    Assignee: Aerojet Rocketdyne of DE, Inc.
    Inventors: Thomas A. Hertel, Erich H. Soendker, Horacio Saldivar
  • Patent number: 8974626
    Abstract: A method of manufacturing a micro structure, includes the steps of: preparing separate first and second substrates, the first substrate having a first surface on which a first structural body having a first height and a second structural body having a second height greater than the first height of the first structural body are arranged, the second substrate having a second surface; then placing the first and second substrates to cause the first and second surfaces to face each other across the first and second structural bodies; and then bonding the first and second substrates to each other while compressing the second structural body in a height direction thereof between the first and second surfaces to cause the second structural body to have a height defined by the first structural body.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 10, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Takamichi Fujii, Akihiro Mukaiyama
  • Patent number: 8973257
    Abstract: Methods for building a neutron detector are disclosed, in which the neutron detector comprises at least two conductive cathode sheets lying parallel to one another and coated with neutron reactive material on at least one side thereof; dielectric material separating the cathode sheets and covering less than about 80% of their surface area; and a plurality of anode wires lying generally parallel to the cathode sheets and separated from them by the dielectric, with the distance between adjacent anode wires being no more than twenty times the distance between said cathode sheets. The cathode sheets may be flat or curved; they may be separate plates or they may be successive folds or windings of a single folded or spiral-shaped metal sheet.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: March 10, 2015
    Assignee: Material Innovations, Inc.
    Inventors: Andrew C. Stephan, Vincent D. Jardret
  • Patent number: 8973259
    Abstract: A method for manufacturing a multilayered printed circuit board including forming a first insulating resin substrate having a metal layer substantially corresponding to dimensions of a semiconductor device, forming a second insulating resin substrate, forming a recess extending to the metal layer of the first insulating resin substrate such that a surface of the metal layer is exposed, accommodating the semiconductor device in the recess such that the semiconductor device is mounted on the surface of the metal layer, and forming a resin insulating layer on the first insulating resin substrate such that the semiconductor device accommodated in the recess is covered.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: March 10, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Publication number: 20150062900
    Abstract: A lighting module including an electronic board adapted to accommodate a plurality of light emitting diodes (LEDs) is provided. The lighting module includes a metallic base having cavities adapted to receive adapters. The adapters include a connector body provided with: a) means adapted to accommodate electrical contacts for interconnection to the electronic board; b) means adapted to accommodate gaskets for shielding the contacts; and c) means for the mechanical locking of the adapters on the module.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 5, 2015
    Inventor: Stefano FERRO
  • Publication number: 20150062855
    Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: RAYTHEON COMPANY
    Inventors: Peter D. Morico, John D. Walker
  • Publication number: 20150060655
    Abstract: A method of constructing an ion guide is disclosed comprising providing an elongated spine member and a plurality of plates. Each plate comprises an aperture therethrough for receiving the spine member and at least one electrode for use in guiding ions. The apertures of the plates are arranged around the spine member and the plates are arranged along the spine member. The plates are then locked in position on the spine member such that the plates are fixed axially with respect to the spine member and so that the electrodes of the plates are arranged so as to form an array of electrodes for use in guiding ions.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 5, 2015
    Inventors: John Richard Garside, Martin Raymond Green, Daniel James Kenny, Jeffrey Ellis Lockett, Richard Barrington Moulds
  • Publication number: 20150062933
    Abstract: Disclosed is a substrate for mounting light emitting element with a high positional accuracy and a method of fixing the substrate. A substrate for mounting light emitting element defines a first recess and a second recess in first side in a plan view. The first recess is defined by two corner portions and a straight portion which connects the two corner portions, and the second recess further includes at least two straight portions each narrowing toward the inner end portion.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Inventors: Toshiyuki YAGI, Toshihiko AIZAWA
  • Publication number: 20150062802
    Abstract: Heat pipe assemblies for Information Handling Systems (IHSs). In some embodiments, an IHS may comprise a motherboard including a Central Processing Unit (CPU); a cooling system coupled to the motherboard, the cooling system including a heat pipe, the CPU coupled to a first side of the heat pipe; and a daughterboard coupled to the motherboard and including a Graphics Processing Unit (GPU) coupled to a second side of the heat pipe. In other embodiments, a method may include providing a motherboard including a CPU; coupling a cooling system to the motherboard, the cooling system including a heat pipe, the CPU coupled to a first side of the heat pipe; and coupling a daughterboard to the motherboard, the daughterboard including a GPU coupled to a second side of the heat pipe.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 5, 2015
    Applicant: Dell Products, L.P.
    Inventors: David William Grunow, Daniel William Kehoe, Matthew B. Mendelow
  • Patent number: 8966731
    Abstract: A method for manufacturing a switching element which has enough resistance to repeat switching operations and which can be miniaturized and have low power consumption, and a display device including the switching element are provided. The switching element includes a first electrode to which a constant potential is applied, a second electrode adjacent to the first electrode, and a third electrode over the first electrode with a spacer layer formed of a piezoelectric material interposed therebetween and provided across the second electrode such that there is a gap between the second electrode and the third electrode. A potential which is different from or approximately the same as a potential of the first electrode is applied to the third electrode to expand and contract the spacer layer, so that a contact state or a noncontact state between the second electrode and the third electrode can be selected.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Honda
  • Patent number: 8966750
    Abstract: A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 3, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Tomoyuki Ikeda, Naoaki Fujii, Seiji Izawa
  • Patent number: 8969736
    Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 3, 2015
    Assignee: Nitto Denko Corporation
    Inventor: Daisuke Yamauchi
  • Patent number: 8971049
    Abstract: A portable electronic device, a peripheral expansion module and methods for assembling a peripheral expansion module onto a portable electronic device are provided herein. The portable electronic device may comprise a main housing unit having a front cover and a back cover which, when coupled together, enclose internal components of the portable electronic device. The peripheral expansion module, comprising one or more peripheral devices coupled within or on a peripheral module housing, may be securely integrated with the portable electronic device. A majority of the peripheral expansion module may be positioned outside of the main housing unit along one side of the portable electronic device. In some embodiments, the peripheral expansion module includes a pair of rails, which extend out from within an interior of the module housing for attachment via one or more mechanical fasteners to an interior surface of the main housing unit of the portable electronic device.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 3, 2015
    Assignee: Motion Computing, Inc.
    Inventors: Bradford Edward Vier, Christopher Lorenzo Dunn
  • Patent number: 8966747
    Abstract: A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation with the mold forming part of the finished product, e.g. providing heat sink fins or a surface mount solderable surface. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features such as registration features accurately locating the circuit board within the mold cavity, interlocking contours for structural integrity of the singulated module, contours to match component shapes and sizes enhancing heat removal from internal components and reducing the required volume of encapsulant, clearance channels providing safety agency spacing and setbacks for the interconnects.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: March 3, 2015
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Michael B. Lafleur, Sean Timothy Fleming, Rudolph Mutter, Andrew T. D'Amico
  • Patent number: 8966746
    Abstract: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu
  • Publication number: 20150055313
    Abstract: A method for manufacturing a combined wiring board includes preparing wiring boards, preparing a metal frame having opening portions formed to accommodate the wiring boards, respectively, positioning the wiring boards in the opening portions in the metal frame, and forming crimped portions in the metal frame by plastic deformation such that sidewalls of the metal frame in the opening portions bond sidewalls of each of the wiring boards. The crimped portions are formed such that the crimped portions in the metal frame have amounts of the plastic deformation which are set different for positions of the crimped portions in the metal frame.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 26, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Teruyuki ISHIHARA, Michimasa Takahashi
  • Patent number: 8959756
    Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: February 24, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 8959764
    Abstract: A structure and method for manufacturing the same for manufacturing a contact structure for microelectronics manufacturing including the steps of forming first and second metal sheets to form a plurality of outwardly extending bump each defining a cavity. Symmetrically mating the first and second metal sheets in opposing relation to each other to form upper and lower bumps each defining an enclosure therebetween wherein the mated first and second sheets form a contact structure. Coating the contact structure with an insulating material, and fabricating helix shaped contacts from upper and lower bumps. The helix shaped contacts having first and second portions being in mirror image relationship to each other.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gareth Hougham, Gerard McVicker, Xiaoxiong Gu
  • Patent number: 8959759
    Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Gibbons, Tracy V. Reynolds, David J. Corisis
  • Patent number: 8959760
    Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 24, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Ayao Niki, Kazuhisa Kitajima
  • Publication number: 20150047185
    Abstract: Disclosed is a system for mounting a flexible first substrate having a first connection region provided with a first electrode group, on a second substrate having a second connection region provided with a second electrode group. The system includes: a stage configured to support the second substrate; a unit for supplying a bonding material including conductive particles and a thermosetting resin, to at least one of the first and second electrode groups; a unit for placing the first substrate on the second substrate via the bonding material and a unit for successively performing a joining process by pressing a first electrode toward a second electrode and curing the thermosetting resin, using a heating tool, while moving the tool to a processing position of another first electrode not yet subjected to the joining process.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 19, 2015
    Applicant: PANASONIC CORPORATION
    Inventors: Koji Motomura, Hideki Eifuku, Hiroki Maruo, Tadahiko Sakai
  • Patent number: 8955218
    Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: February 17, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Shih-Lian Cheng
  • Patent number: 8957321
    Abstract: A printed circuit board of the present invention includes a base body, a through-hole that penetrates through the base body in the thickness direction, and a through-hole conductor that covers an inner wall of the through-hole. The base body has a fiber layer including a plurality of glass fibers and a resin that covers the plurality of glass fibers. The glass fibers have a groove-shaped concavity on a surface exposed to the inner wall of the through-hole. The concavity is filled with a part of the through-hole conductor.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 17, 2015
    Assignee: KYOCERA SLC Technologies Corporation
    Inventors: Masaaki Harazono, Yoshihiro Hosoi
  • Publication number: 20150043188
    Abstract: The invention relates to a method for manufacturing a printed circuit board (10) having a substrate (2) and an electric circuit (8), in particular for a rear view device of a motor vehicle, the method comprising the following steps: manufacturing a plurality of substrate parts (2a, 2b); and selecting at least two of the substrate parts (2a, 2b), and connecting the selected substrate parts (2a, 2b) and providing the connected substrate parts (2a, 2b) with the circuit (8).
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Applicant: SMR PATENTS S.A.R.L.
    Inventor: Andreas Herrmann
  • Patent number: 8950063
    Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: February 10, 2015
    Assignee: Viasystems Technologies Corp., L.L.C.
    Inventors: Raj Kumar, Monte Dreyer, Michael J. Taylor
  • Publication number: 20150033552
    Abstract: Methods and systems for manufacturing a swallowable sensor device are disclosed. Such a method includes mechanically coupling a plurality of internal components, wherein the plurality of internal components includes a printed circuit board having a plurality of projections extending radially outward. A cavity is filled with a potting material, and the mechanically coupled components are inserted into the cavity. The cavity may be pre-filled with the potting material, or may be filled after the mechanically coupled components have been inserted therein. A distal end of each projection abuts against a wall of the cavity thereby preventing the potting material from covering each distal end. The cavity is sealed with a cap causing the potting material to harden within the sealed cavity to form a housing of the swallowable sensor device, wherein the distal end of each projection is exposed to an external environment of the swallowable sensor device.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Applicant: Innurvation, Inc.
    Inventors: Michael R. Arneson, William R. Bandy, Roger A. Davenport, Kevin J. Powell, Michael C. Sloan
  • Publication number: 20150036305
    Abstract: An electronic component built-in multi-layer wiring board that comprises collectively stacked therein a plurality of first printed wiring boards by thermal compression bonding, and that comprises an electronic component package built in thereto, wherein the electronic component package comprises a first electronic component built in thereto and a plurality of second printed wiring boards stacked to have electrodes on an outermost surface of the package at a pitch that is wider than the electrode pitch of the first electronic component and that is matched to the wiring pitch of the first printed wiring boards, the electronic component built-in multi-layer wiring board includes a second electronic component having a thickness which is greater than that of the first electronic component, and the electronic component package having a thickness which is 80% to 125% of the thickness of the second electronic component.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 5, 2015
    Applicant: FUJIKURA LTD.
    Inventor: Hirokazu Nanjo
  • Patent number: 8946561
    Abstract: A flexible printed circuit may be provided with an integrated heat and pressure spreading layer. The heat and pressure spreading layer may be configured to uniformly spread heat and pressure from a bonding tool across a portion of the flexible printed circuit during bonding of the flexible printed circuit to additional circuitry. During manufacturing of the flexible printed circuit, a sheet of heat and pressure spreading material may be attached to a sheet of flexible printed circuitry and the heat and pressure spreading material and the sheet of flexible printed circuitry may be die cut to form multiple flexible printed circuits each with a heat and pressure spreading layer. An electronic device may be provided with a flexible printed circuit with a heat and pressure spreading layer coupled to a component such as a display.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Joshua G. Wurzel, Casey J. Feinstein
  • Patent number: 8943682
    Abstract: A method of making a transparent touch-responsive capacitor apparatus includes providing a transparent conductor precursor structure including a transparent substrate, a first precursor material layer formed over the transparent substrate and a second precursor material layer formed on the first precursor material layer; forming a electrically connected first micro-wires in the first and second precursor material layers; forming electrically connected second micro-wires in a precursor material layer electrically connected to the first micro-wires; and wherein the height of at least a portion of the first micro-wires is greater than the height of at least a portion of the second micro-wires, and wherein the total area occupied by the first micro-wires is less than 15% of the first transparent conductor area and the total area occupied by the second micro-wires is less than 15% of the second transparent conductor area.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Eastman Kodak Company
    Inventors: Ronald Steven Cok, Terrence Robert O'Toole
  • Publication number: 20150028747
    Abstract: An LED-based lighting system having an upgradeable control system and a method thereof are provided. The system includes an LED source having a plurality of LED lights, a control system which comprises a motherboard, a control panel, and a control module. The control module is replaceable with a new control module to provide upgrades of operational modes and features of the lighting system without requiring the entire lighting system be replaced.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Christopher Michael Bourget, Ronald J. Anderson, Barry Arneson
  • Publication number: 20150028912
    Abstract: A board for a probe card includes a ceramic board including a first insulating layer, and second insulating layers disposed on one surface of the first insulating layer and including cavities for receiving electronic components, conductive patterns disposed on the first and second insulating layers, conductive vias electrically connecting the conductive patterns, and a capacitor disposed in the cavities. The cavities have a depth greater than a thickness of the capacitor to secure a space in a lower portion of the cavity after receiving the capacitor.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 29, 2015
    Inventors: Beom Joon CHO, Jung Goo CHOI, Ji Sung NA, Yun Hwi PARK, Kwang Jae OH, Ho Sung CHOO, Ji Hwan SHIN
  • Patent number: 8938876
    Abstract: Various circuit board sockets and methods of manufacturing and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a socket that is operable to receive a circuit board. The socket includes a surface for seating a first portion of a circuit board, a floor and a first support structure projecting away from the floor to support a second portion of the circuit board. The support structure includes a plurality of nested frames. In another aspect, a socket with a with socket cover coupled to a socket housing is disclosed. The socket housing includes a support structure to support a portion of the socket cover.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: January 27, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen F. Heng, Mahesh S. Hardikar
  • Publication number: 20150016067
    Abstract: A high frequency (HF) module and a manufacturing method thereof. The HF module has a single airtight box-like structure formed by a first PCB, a second PCB, and a third PCB. On a lower surface of the third PCB facing the first PCB, a second electronic component is mounted at a position corresponding to a first electronic component relatively low in height, among first electronic components mounted on the first PCB. Upper and lower ends of a plurality of vias formed within the second PCB are connected to a copper layer existing within a body of the third PCB and a copper layer existing within a body of the first PCB to constitute a single electromagnetic wave shielding unit overall.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 15, 2015
    Inventors: Chang Sup SONG, Jong Pil Park
  • Publication number: 20150016048
    Abstract: In various embodiments, a printed circuit arrangement may be provided. The printed circuit arrangement may include a processor circuit. The printed circuit arrangement may further include a printed main circuit arrangement in electrical connection with a first input node of the processor circuit. The printed main circuit arrangement may be configured to receive at least one input signal and generate a main circuit signal based on the at least one input signal after a first delay from receiving the at least one input signal. The printed circuit arrangement may further include a printed reference circuit arrangement in electrical connection with a second input node of the processor circuit. The printed reference circuit arrangement may be configured to receive a further input signal, may have a second delay and may be configured such that the second delay adapts to the first delay.
    Type: Application
    Filed: July 12, 2014
    Publication date: January 15, 2015
    Inventors: Kok Leong Chang, Jie Zhang, Weng Yew Lee
  • Publication number: 20150015287
    Abstract: The test system provides an array of test probes having a cross beam. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. The probes are biased upwardly through the retainer by an elastomeric block having a similar array of slots. The elastomer is then capped at its bottom by a second or lower retainer with like slots to form a sandwich with the elastomer therebetween. The bottom ends of the probes are group by probe height. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and take continue the circuits to a probe card where test signals originate.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Patent number: 8931168
    Abstract: A method for manufacturing a printed wiring board includes preparing a core substrate having a first surface and a second surface on the opposite side of the first surface, forming on the first-surface side of the substrate a first opening portion tapering from the first toward second surface, forming on the second-surface side of the substrate a second opening portion tapering from the second toward first surface, forming a third opening portion such that a penetrating hole formed of the first opening portion, the second opening portion and the third opening portion connecting the first and second opening portions is formed in the substrate, forming a first conductor on the first surface of the substrate, forming a second conductor on the second surface of the substrate, and filling a conductive material in the penetrating hole such that a through-hole conductor connecting the first and second conductors is formed.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: January 13, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshiaki Hibino, Takema Adachi
  • Patent number: 8926785
    Abstract: A method for manufacturing a multi-piece board having a frame section and a multiple piece sections connected to the frame section includes forming a frame section from a manufacturing panel for the frame section, sorting out multiple acceptable piece sections by inspecting quality of piece sections, forming notch portions in the frame section and the acceptable piece sections such that the notch portions allow the acceptable piece sections to be arranged with respect to the frame section, provisionally fixing the piece sections and the frame section in respective positions, injecting an adhesive agent into cavities formed by the notch portions when the frame section and the piece sections are provisionally fixed to each other, and joining the acceptable piece sections with the frame section by curing the adhesive agent injected into the cavities.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: January 6, 2015
    Assignee: Ibiden Co., Ltd.
    Inventor: Takahiro Yada
  • Patent number: 8925189
    Abstract: A method is provided for assembling a connector assembly to a case. The case includes an inside surface defining an inside of the case, an outside surface defining an outside of the case, and an aperture therethrough providing communication from the inside surface to the outside surface. The connector assembly includes an outer connector having a body with a passage therethrough, an electromagnetic shield, and an inner connector with a terminal therein with a conductor extending from the inner connector in electrical communication with the terminal. The method includes positioning the outer connector on the outside of the case to align the passage of the outer connector with the aperture of the case. The method also includes positioning the inner connector on the inside of the case. The method also includes inserting the inner connector into the passage of the outer connector from the inside of the case.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Christopher Adrian Margrave, William T. Madden, Terry A. George, Don E. Bizon
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai
  • Publication number: 20150000959
    Abstract: A multilayer printed circuit board (PCB) includes a first and second PCB component, and an anisotropic conductive film (ACF). The first PCB component includes a first base isolative layer, additional circuited layers and isolative layers alternately stacked on the first base isolative layer, and a number of conductive posts protruding out of the first base isolative layer away from the additional circuited layers and the isolative layers. The second PCB component includes a second base isolative layer, additional circuited layers and isolative layers alternately stacked on the second base isolative layer, and a number of pads are formed on the second base isolative layer opposite to the additional layers and the isolative layers. Each conductive post is aligned with one of the pads. The ACF is sandwiched between and bonds the first base isolative layer and the second base isolative layer together.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Inventor: WEI-SHUO SU