Assembling Bases Patents (Class 29/830)
  • Patent number: 9268366
    Abstract: In one general aspect, an apparatus can include a display portion, a base frame coupled to the display portion where the base frame includes a channel defined by a top wall opposite a bottom wall and a side wall coupled to the top wall and to the bottom wall. The side wall can have an outer surface defining at least a portion of an outer perimeter of the base frame. The channel can have a first portion on a first side of the base frame and a second portion on a second side of the base frame opposite the first side of the base frame. The apparatus can include a midplane having a first edge disposed in the first portion of the channel and having a second edge disposed in the second portion of the channel.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: February 23, 2016
    Assignee: Google Inc.
    Inventors: Michelle Yu, Ji Heun Lee, Jeffrey Hayashida
  • Patent number: 9258899
    Abstract: A method of fabricating a wiring board includes forming a surface plating layer on a support member, and forming an external connecting pad on the surface plating layer formed on the support member such that an area of the external connecting pad formed on the surface plating layer is smaller than an area of the surface plating layer. The method also includes forming an insulating layer and a wiring layer on a surface of the support member where the external connecting pad is formed, and removing the support member.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 9, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kentaro Kaneko
  • Patent number: 9210816
    Abstract: A method of manufacture of a support system includes: forming a carrier having a detachable core and a carrier foil directly on the detachable core; forming a mask directly on the carrier foil, the mask having a mask hole through the mask; forming a bottom conductive layer within the mask hole and directly on the carrier foil; forming an interior insulation layer directly on the bottom conductive layer and the mask after the bottom conductive layer is formed within the mask hole; partially removing the interior insulation layer leaving an insulation hole through the interior insulation layer; forming a conductive connector completely within the insulation hole; and forming a bottom exterior insulation layer over the bottom conductive layer and the mask.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: December 8, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: YoungDal Roh, KyoungHee Park, Dong Ju Jeon, HyungSang Park
  • Patent number: 9199346
    Abstract: A manufacturing apparatus that manufactures flattened tube fins, in which cutaway portions for inserting flattened tubes for heat exchanging are formed, includes: a press apparatus provided with a mold apparatus that forms the cutaway portions in an unmachined metal thin plate to produce a metal strip; an inter-row slit apparatus cutting the metal strip into predetermined widths to form a plurality of metal strips of a product width; a cutoff apparatus cutting each metal strip of the product width into predetermined lengths; a holding apparatus that holds a plurality of metal strips of the product width that protrude from a downstream side in the conveying direction of the cutoff apparatus; and a stacker apparatus for stacking the flattened tube fins that have been cut into predetermined lengths by the cutoff apparatus.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 1, 2015
    Assignee: HIDAKA SEIKI KABUSHIKI KAISHA
    Inventors: Masanao Karasawa, Toshiyuki Nanaarashi, Akio Ueda, Yasuyuki Morimoto, Takatoshi Mori
  • Patent number: 9192050
    Abstract: Disclosed herein is a method of manufacturing a printed circuit board, including; forming an electronic component including an electrode that is formed on at least one side of a body; forming terminals on an upper portion of the electrode and an upper portion of the body; providing a substrate in which a cavity is formed; mounting the electronic component formed with the terminals in the cavity of the substrate; and forming a buildup layer on an upper portion of the substrate and an upper portion of the electronic component.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: November 17, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Yeol Park, Suk Jin Ham, Jung Tae Park, Seung Heon Han, Jung Eun Noh
  • Patent number: 9178009
    Abstract: Methods of forming a capacitor and contact structures are provided. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ki Young Lee, Sanggil Bae, Jae Ho Joung
  • Patent number: 9177726
    Abstract: With a multilayer ceramic capacitor whose average grain size of the dielectric grains present at the outermost layer position P1 in the laminate is given by D1, average grain size of the dielectric grains present at the center position P2 in the laminate is given by D2, and average grain size of the dielectric grains present at the 25%-penetrated position P3 which is a position penetrated into the laminate by 25% is given by D3, growth of the dielectric grains occurring as a result of sintering is partially suppressed in such a way that the relationships of average grain sizes D1, D2, and D3 satisfy the conditions of 1.5×D1<D3 and 1.2×D2<D3. This way, a sufficient CR product can be obtained even with a dielectric thickness of 1 ?m or less.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: November 3, 2015
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Koichiro Morita, Katsuya Taniguchi
  • Patent number: 9176167
    Abstract: A conductive probe for semiconductor material characterization includes a distal metallic layer of micrometer-size particles, an intermediate layer of conformable conductive elastomer material, and a pin attached to the elastomer layer. The probe is preferably manufactured by filling a recess in a bottom plate with the metallic particles, coupling a top plate thereto with a perforation aligned with the recess, and filling the perforation with uncured conductive elastomer. The pin, preferably spring-loaded, is pressed into the perforation to compress the silicone to its intended probe size. The silicone is then allowed to cure at room temperature or in a heated environment, or both.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 3, 2015
    Assignee: BRUKER NANO INC.
    Inventors: Dong Chen, Mark Munch
  • Patent number: 9159673
    Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Cheng Ko, Chi-Chun Hsieh, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 9131635
    Abstract: A manufacturing method of substrate structure is provided. The base material having a core layer and a first and second copper foil layers located at a first and second surfaces of the core layer is provided. A surface treatment is performed on the first and second copper foil layers so as to form a first and second roughened surfaces. A laser beam is irradiated on the first roughened surface so as to form at least one first blind hole extending from the first copper foil layer to the second surface. An etching process is performed on the second copper foil layer so as to form at least one second blind hole extending from the second copper foil layer to the second surface. A conductive layer fills up a through hole defined by the first and second blind holes and covers the first and second copper foil layers.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 8, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Wei Huang
  • Patent number: 9125334
    Abstract: In a method for manufacturing multilayer PCBs having n circuit layers, a double-sided flexible substrate strip is provided. The strip comprises a number of PCB units, each comprising m segments, wherein m=n/2 if n represents an even integer, and m=(n+1)/2 if n represents an odd integer. Each segment includes two foil portions. In a reel to reel process, the strip is treated to form n?2 foil portions of each PCB unit into traces, further remove one foil portion if n represents an odd integer. The other two foil portions are left untreated. Then the strip is cut to separate the PCB units from each other. The PCB unit is folded in such a manner that the traces are arranged between the other two foil portions. The folded PCB unit is laminated to form a multilayer substrate and traces are formed in the two foil portions.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 1, 2015
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Hui Zeng
  • Patent number: 9113562
    Abstract: A manufacturing method for a printed wiring board includes forming an electroless plated film on an interlayer resin insulation layer, forming on the electroless plated film a plating resist with an opening to expose a portion of the electroless plated film, forming an electrolytic plated film on the portion of the electroless plated film exposed through the opening, removing the plating resist using a resist-removing solution containing an amine, reducing a thickness of a portion of the electroless plated film existing between adjacent portions of the electrolytic plated film by using the resist-removing solution, and forming a conductive pattern by removing the portion of the electroless plated film existing between the adjacent portions of the electrolytic plated film by using an etchant.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 18, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Hideo Mizutani, Toshiyuki Matsui, Atsushi Deguchi
  • Patent number: 9082871
    Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi-Jun Park, Won-Keun Kim, Teak-Hoon Lee, Chang-Seong Jeon, Young-Kun Jee
  • Patent number: 9076822
    Abstract: Some embodiments can include a method of manufacturing first electronic device(s) and second electronic device(s), the method including: providing a carrier substrate having a first side and a second side, a first substrate bonded to the first side of the carrier substrate, and a second substrate bonded to the second side of the carrier substrate; depositing at least one layer of a first material over the first substrate while the first substrate is bonded to the first side of the carrier substrate to create a portion of the first electronic device(s); and depositing at least one layer of a second material over the second substrate while the second substrate is bonded to the second side of the carrier substrate to create a portion of the second electronic device(s). In many embodiments, the first substrate and/or the second substrate includes a flexible substrate. Other related systems and methods are also disclosed.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 7, 2015
    Assignee: Arizona Board of Regents, a Body Corporate of the State of Arizona Acting for and on behalf of Arizona State University
    Inventors: Douglas E Loy, David Morton, Emmett Howard
  • Patent number: 9078384
    Abstract: A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 7, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Jun Furuichi, Akihiko Tateiwa, Naoyuki Koizumi
  • Patent number: 9040837
    Abstract: A wiring board includes a first multilayer wiring board having first conductive layers and having a surface, a second multilayer wiring board having second conductive layers and positioned such that the second multilayer wiring board has a surface facing the surface of the first multilayer wiring board, and an adhesive layer including an adhesive sheet and interposed between the first multilayer wiring board and the second multilayer wiring board such that the adhesive layer is adhering the first multilayer wiring board and the second multilayer wiring board. The first multilayer wiring board has a first pad on the surface of the first multilayer wiring board, the second multilayer wiring board has a second pad on the surface of the second multilayer wiring board, and the first pad and the second pad are positioned such that the first pad and the second pad face each other across the adhesive layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: May 26, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Michimasa Takahashi, Teruyuki Ishihara
  • Publication number: 20150141084
    Abstract: A mobile terminal according to the present disclosure includes a terminal main body, a case covering the terminal main body, and forming at least part of appearance of the terminal, wherein the case comprises a penetration line formed through the case along a predetermined path, and forming a connecting portion between ends of the penetration line, and wherein the connecting portion extends from the case, and an input part is formed on a region formed by the penetration line and the connecting portion, the input part being rotatable based on the connecting portion.
    Type: Application
    Filed: May 5, 2014
    Publication date: May 21, 2015
    Applicant: LG Electronics Inc.
    Inventors: Sunghan KIM, Inseok Yoo, Taehyun Kim
  • Publication number: 20150136454
    Abstract: A combined wiring board includes multiple wiring boards, and a connected metal frame having multiple metal frames and one or more connecting portions such that the metal frames are connected each other by the connecting portion or connecting portions and have accommodation opening portions formed to accommodate the wiring boards, respectively.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 21, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Teruyuki ISHIHARA, Michimasa TAKAHASHI
  • Publication number: 20150136453
    Abstract: A combined wiring board includes a wiring board set having multiple wiring boards and one or more adhesive agent portions such that the wiring boards are connected each other by the adhesive agent portion or adhesive agent portions, and a metal frame having an accommodation opening portion formed to accommodate the wiring board set such that the wiring board set is positioned in the accommodation opening portion of the metal frame.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 21, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Teruyuki ISHIHARA, Michimasa TAKAHASHI
  • Patent number: 9032613
    Abstract: A method for making a circuit board includes separating a plurality of versatile circuit boards from a collective board by cutting a connecting portion of the collective board, the plurality of versatile circuit boards being connected each other via the connecting portion, and cutting a part of a wiring formed on each of the plurality of versatile circuit boards to produce the circuit board. The cutting of the part of the wiring is conducted within the separating of the plurality of versatile circuit boards.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventor: Naohiro Fukaya
  • Publication number: 20150131248
    Abstract: An electronic module (20, 39, 60, 80, 132, 140, 144) includes a substrate (21), which includes a dielectric material having a cavity (40, 42, 134, 142) formed therein. First conductive contacts (44) within the cavity are configured for contact with at least one first electronic component (32) that is mounted in the cavity. Second conductive contacts (44) on a surface of the substrate that surrounds the cavity are configured for contact with at least a second electronic component (28, 30) that is mounted over the cavity. Conductive traces (36, 48) within the substrate are in electrical communication with the first and second conductive contacts.
    Type: Application
    Filed: May 9, 2013
    Publication date: May 14, 2015
    Inventors: Michael Dakhiya, Eran Shaked
  • Publication number: 20150131256
    Abstract: The present invention is a backplane board including a first circuit board, a second circuit board, a first slot in which a first connector is connected with the first circuit board, and a second slot in which a second connector is connected with the second circuit board. The first connector and the second connector are arranged so that pin arrangement of the first connector may be shifted by at least one column in a longitudinal direction against pin arrangement of the second connector.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 14, 2015
    Inventor: Kazuhiro Kashiwakura
  • Patent number: 9027247
    Abstract: A method and structure for forming an ink jet printhead can include the use of a transfer pad to transfer an adhesive solution to an ink jet printhead substrate. The adhesive solution can be placed within a patterned recess of a cliché and then an upper surface of the adhesive solution can be gelled. A surface of the transfer pad contacts the gelled upper surface and transfers the adhesive solution to the ink jet printhead substrate. During the transfer, a lower surface of the adhesive solution gels. During contact with the ink jet printhead substrate, the gelled lower surface adheres to the ink jet printhead substrate while the gelled upper surface releases from the transfer pad.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 12, 2015
    Assignee: Xerox Corporation
    Inventors: Xuejin Wen, Mark A. Cellura
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Publication number: 20150124415
    Abstract: Embodiments of the present application relate generally to personal electronics, portable electronics, wearable electronics, and more specifically to a structure and method for a protective covering for a wearable device. Interior and exterior structures of the wearable device are configured to be flexed into a configuration and to retain the configuration after the flexing. Interior structure may include a first flexible substrate having a first relaxation structure and a second flexible substrate having a second relaxation structure. Components or other structures may be connected with the first and/or second flexible substrates. The first and second relaxation structures may be positioned relative to each other to define a flexure point. At least one flexible and electrically non-conductive cover, that may undergo shirking, may conformally cover at least a portion of the interior structure. A flexible overmolding may be formed over the cover and may comprise the exterior structure.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: AliphCom
    Inventors: Dileep Goyal, Andrew Dawn, William Maginn, Hari Chakravarthula
  • Publication number: 20150124420
    Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Inventors: Alexander Heinrich, Peter Scherl, Magdalena Hoier, Hans-Joerg Timme
  • Patent number: 9021692
    Abstract: A printed wiring board includes a resin insulation layer having a first surface and a second surface on an opposite side of the first surface, the resin insulation layer having an opening for a first via conductor, a pad formed on the first surface of the resin insulation layer and provided to mount an electronic component, a first conductive circuit formed on the second surface of the resin insulation layer, and a first via conductor formed in the opening and connecting the pad and the first conductive circuit. The pad has an embedded portion embedded in the resin insulation layer and a protruding portion protruding from the resin insulation layer, and the embedded portion has an external shape which is greater than an external shape the protruding portion.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: May 5, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Satoru Kawai, Kenji Sakai, Liyi Chen
  • Patent number: 9021693
    Abstract: A method of manufacturing a printed circuit board, including: applying a dry film on a carrier and then patterning the dry film to form holes for forming metal bumps; forming an upper circuit layer including metal bumps charged in the holes and connection pads on the dry film; forming an insulation layer on the dry film; forming a build-up layer including a lower circuit layer on the insulation layer; removing the carrier; and removing the dry film.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Yong An, Jae Joon Lee
  • Patent number: 9022602
    Abstract: Modular multichannel light sources connector systems and methods are provided. A lighting assembly includes substrates, each with a respective plurality of ports and conductive path configurations. Each path configuration includes a plurality of conductive paths between the respective plurality of ports. At least two conductive path configurations are the same. A connector couples one of a plurality of first ports on a first substrate to one of a plurality of second ports on a second substrate. A multichannel power supply's outputs are each coupled to an associated conductive path on the first substrate. A first light source is coupled to two conductive paths on the first substrate, and to a first output. A second light source is coupled to two conductive paths on the second substrate, corresponding to the conductive paths on the first substrate, and to a second output, different from the first output.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 5, 2015
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Nicholas Lekatsas, Biju Antony, David Lidrbauch
  • Patent number: 9021690
    Abstract: A method of manufacturing a printed circuit board having a buried solder bump, including: preparing a carrier on which a circuit layer, a solder bump, and a circuit pattern formed on the solder bump are formed; pressing the carrier into an insulating layer so that the circuit layer, the solder bump and the circuit pattern are buried in the insulating layer; and removing the carrier.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 5, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Myung Sam Kang
  • Patent number: 9021691
    Abstract: A method for introducing electrical insulations in a printed circuit board includes selectively introducing groove-shaped recesses between different regions of an electrically conductive layer on a substrate along a machining path using a thermal energy input such that end portions of each of the recesses or different ones of the recesses are joined to one another. The end portions are introduced parallel to one another without overlap such that a strip-shaped region of the conductive layer is initially retained between the end portions so as to insulate the different regions.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 5, 2015
    Assignee: LPKF Laser & Electronics AG
    Inventor: Jan van Aalst
  • Publication number: 20150116629
    Abstract: A method for manufacturing an electronic device is provided, including the following steps. First, an outer frame is provided, wherein the outer frame comprises the first frame member and the second frame member. Next, the first frame member is connected to the second frame member by welding to form a connected structure, wherein a welded portion is formed between the first frame member and the second frame member. Then, a punch pin and a punch base are provided. Next, the connected structure is placed on the punch base. Finally, the connected structure is punched by the punch pin.
    Type: Application
    Filed: March 14, 2014
    Publication date: April 30, 2015
    Applicant: Wistron Corp.
    Inventor: Shu-hua DAI
  • Publication number: 20150117022
    Abstract: The present invention is directed to the use of light emitting diode (LED) lighting in flexible strips, where the color of the lighting emitted from the flexible strip is consequential to the encapsulation process and heat from the lights is adequately dissipated.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Inventor: Ariel Meir
  • Patent number: 9018539
    Abstract: The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 28, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Han Ul Lee
  • Patent number: 9015930
    Abstract: Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 28, 2015
    Assignee: Nikon Corporation
    Inventors: Hidehiro Maeda, Satoshi Katagiri
  • Patent number: 9015932
    Abstract: It is to provide an electronic component connecting method capable of performing dehumidification within a short time without giving a thermal influence to an electronic component which has already been mounted on a wiring board. When a first connection terminal group 5 formed on a connection area 3 of a rigid board 1 is connected to a flexible board 2 where a second connection terminal group 6 has been formed by employing a thermosetting resin in an electrically conductive manner, since a connection area 3 which is heated in a step for thermally hardening the thermosetting resin is locally preheated, moisture, and oils and fats contained in the connection area 3 among such moisture, and oils and fats, which have been absorbed in the rigid board 1 are dehumidified. Thereafter, the thermosetting resin interposed between the first connection terminal group 5 and the second connection terminal group 6 is thermally hardened.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: April 28, 2015
    Assignee: Panasonic Corporation
    Inventors: Tadahiko Sakai, Hideki Eifuku
  • Publication number: 20150109083
    Abstract: A base is a platform that supports a component off the ground in a solar energy installation. The specific configuration of a base can vary based on the intended component, for example whether it holds a transformer or power component. Multiple bases are mechanically and/or electrically connected to form a system of bases in the field. Proper placement of bases and engagement of those bases is facilitated by mating alignment mechanisms such that one base can be lowered “fit” with another. A method of positioning components includes positioning a base and aligning and lowering a second base alongside the first such that the bases engage.
    Type: Application
    Filed: October 13, 2014
    Publication date: April 23, 2015
    Inventor: Dean Solon
  • Publication number: 20150107101
    Abstract: Fabricating preassembled optoelectronic interconnect structures is provided, which have an optical waveguide link with first and second optoelectronic circuits attached to first and second ends of the waveguide link. The optoelectronic circuits include active optical componentry which facilitates optical signal communication across the optical waveguide link. Further, first and second pluralities of electrical contacts are associated with the first and second optoelectronic circuits, respectively, to facilitate electrically, operatively connecting the interconnect structure between first and second components of an electronic assembly as, for instance, a single, field-replaceable unit. The first and second components of the electronic assembly may be, for instance, stacked electronic components of the electronic assembly, or laterally offset components of a substantially planar electronic assembly.
    Type: Application
    Filed: November 11, 2014
    Publication date: April 23, 2015
    Inventors: Casimer M. DeCUSATIS, Rajaram B. KRISHNAMURTHY, Michael ONGHENA, Anuradha RAO
  • Patent number: 9009954
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes forming the Z-directed component in a cavity formed by a constraining material that defines the outer shape of the Z-directed component. The constraining material is dissipated to release the Z-directed component from the constraining material and the Z-directed component is fired.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 21, 2015
    Assignee: Lexmark International, Inc.
    Inventors: Keith Bryan Hardin, Paul Kevin Hall, Zachary Charles Nathan Kratzer, Qing Zhang
  • Patent number: 9013882
    Abstract: A high-frequency module has a multilayer board formed by laminating a plurality of sheets made of a thermoplastic resin material and subjecting the laminated sheets to thermocompression bonding, and an IC chip placed in a cavity provided in the multilayer board. A gap is provided between a side of the IC chip and an inner wall of the cavity. The multilayer board includes a via-hole conductor provided near the inner wall of the cavity for preventing the resin sheets from being softened and flowing into the cavity upon thermocompression bonding.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: April 21, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Naoki Gouchi, Takahiro Baba
  • Publication number: 20150103525
    Abstract: A method of making a light emitting diode (LED) lamp is disclosed. Included are steps of: providing a metal heat sink having a cylindrical portion formed with flat planar surfaces extending longitudinally around the outer surface; providing flat LED boards that are attached to the flat planar surfaces; providing a circular LED board mounted to the top end of the cylindrical portion; providing a turret connector board with electrical connection ports to electrically join the LED boards; providing a driver circuit board and electrically connecting it to the turret connector board; connecting the flat LED boards to the driver circuit board; securing the circular LED board to the top open-end; and securing the flat LED boards to the flat planar surfaces. Optional steps include: providing a mounting plate of heat conducting metal; applying thermal compound; providing and installing a transparent cover; providing and attaching a mount to the incandescent lamp.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: LED Waves, Inc.
    Inventors: Larry W. Rowley, Joel Slavis
  • Publication number: 20150103541
    Abstract: This invention relates to an optical device, more particularly, to a method for manufacturing an optical device substrate in which an optical device can be arranged in a various manner.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Inventors: Bum Mo Ahn, Seung Ho Park
  • Patent number: 9003653
    Abstract: A method for producing a ceramic multilayer circuit system, and a corresponding multilayer circuit system are provided. An embodiment of the method includes sequential deposition of a plurality of circuit layers of the multilayer circuit system on a substrate using a powder spray method; pressing of the deposited plurality of circuit layers; and thermal sintering of the pressed plurality of circuit layers. The individual circuit layers have electrically conductive areas made of at least one conductive material and electrically insulating areas made of at least one ceramic material.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: April 14, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Juergen Egerter, Walter Roethlingshoefer, Markus Werner
  • Patent number: 9003648
    Abstract: The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 14, 2015
    Assignee: Ormet Circuits, Inc.
    Inventor: Ken Holcomb
  • Patent number: 9003649
    Abstract: A fluid cooled electrical assembly that includes a metal box, having a bottom wall, side walls and a top wall. A set of straight-edged pins, each smaller than 3 mm across in widest dimension, extend down from the top wall and up from the bottom wall. Also, electrical components are mounted on top of the top wall and on bottom of the bottom wall.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: April 14, 2015
    Assignee: Maxq Technology, LLC
    Inventors: Guillermo L. Romero, Joe L Martinez, Jr.
  • Publication number: 20150099948
    Abstract: A flexible embedded sensor array includes a first substrate, an electrically conductive pad disposed on at least a portion of the first substrate, and a plurality of sensors disposed on at least a portion of electrically conductive pads. Further, the flexible embedded sensor array includes an electrically non-conductive adhesive material disposed in proximity to one or more of the plurality of sensors, a second substrate, and an electrical contact disposed between at least a portion of the sensor and at least a portion of the second substrate.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: General Electric Company
    Inventors: Christopher James Kapusta, Eric Patrick Davis, Jason Harris Karp
  • Patent number: 8997340
    Abstract: A method of manufacturing an insulating sheet, the method including providing a reinforcement material having a thermoplastic resin layer stacked thereon; stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate; and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
  • Patent number: 8997344
    Abstract: A method for manufacturing an interposer including forming a first insulating layer comprising an inorganic material on a supporting substrate, forming a first wire in the first insulating layer, forming a second insulating layer on a first side of the first insulating layer, forming a second wire with a longer wire length and a greater thickness than the first wire on the second insulating layer, and removing the supporting substrate.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: April 7, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Shuichi Kawano, Daiki Komatsu, Hiroshi Segawa
  • Patent number: 8997342
    Abstract: A method of fabricating a multilayer electronic support structure comprising electroplating copper substructures, laying a dielectric pre-preg comprising a polymer resin over the copper substructures, and pressing to pressures of 200 to 600 PSI against a release film having a higher hardness than the resin of the prepreg but a lower hardness than the cured resin, and heating through a curing cycle while maintaining pressure.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Patent number: 8997343
    Abstract: A method for manufacturing multilayer printed circuit board includes step below. A metal substrate is provide, the metal substrate includes a number of substrate unit. A first insulating layer is formed on one surface of the metal substrate. The first insulating layer has a number of first through holes. An electrically conductive circuit is formed in each substrate unit. A second insulating layer is formed on the other surface of the metal substrate. The second insulating layer has a number of second through holes. A first metal cylinder is formed in a first through hole and a second metal cylinder is formed in a second through hole. The number of substrate units are folded and laminated, the connected and aligned first metal cylinder and the second metal cylinder communicates the electrically conductive circuits.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: April 7, 2015
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Chien-Pang Cheng