Assembling Bases Patents (Class 29/830)
  • Patent number: 8351216
    Abstract: The present invention relates to a layered structure assembly (1) for a DC to AC inverter comprising: a first layered structure (10) with first (12) and second (13) conductive layers, a second layered structure (14) with third (16) and fourth (17) conductive layers, and at least one connector (21) providing a low resistance/inductance interconnection between layered structures (10, 14), the connecter (21) comprising a rod (23) inside a sleeve (26).
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: January 8, 2013
    Assignee: Power Concepts NZ Limited
    Inventor: Christopher William Fotherby
  • Publication number: 20130000113
    Abstract: A method for producing a joined structure involving pressure-bonding a first circuit member and a second circuit member together via a connecting film while the circuit members are being heated, to thereby join the circuit members with each other, wherein the connecting film is defined and includes first and second layers wherein one of the first layer and the second layer is a conductive particle-containing organic resin layer, and the other layer is an insulating organic resin layer containing no conductive particles, and wherein the minimum melt viscosity of the conductive particle-containing organic resin layer is ten times or more greater than the minimum melt viscosity of the insulating organic resin layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: Sony Chemical & Information Device Corporation
    Inventors: Yasushi AKUTSU, Tomoyuki ISHIMATSU, Koichi MIYAUCHI
  • Publication number: 20130003325
    Abstract: In a method for processing or treating a plurality of printed circuit boards, comprising the following steps: providing a plurality of printed circuit boards (4, 5, 6, 7). providing at least one frame or carrier element (2, 3), for coupling to a plurality of printed circuit boards (4, 5, 6, 7), coupling or connecting the printed circuit boards (4, 5, 6, 7) to the at least one frame or carrier element (2, 3), processing or treating the printed circuit boards (4, 5, 6, 7) in the state coupled to the frame or carrier element (2, 3), it is provided that printed circuit boards (4, 5, 6, 7) of different sizes and/or thicknesses and/or of different constructions are coupled to the at least one frame or carrier element (2, 3) to form a composite assembly (1) and are subjected to further processing in the composite assembly (1) formed by the printed circuit boards (4, 5, 6, 7) and the at least one frame or carrier element (2, 3).
    Type: Application
    Filed: March 10, 2011
    Publication date: January 3, 2013
    Inventors: Gerhard Freydl, Christian Vockenberger
  • Patent number: 8341815
    Abstract: A laminate is prepared in which adjacent internal electrodes are electrically insulated from each other at an end surface at which the internal electrodes are exposed, a space between the adjacent internal electrodes, which is measured in the thickness direction of insulating layers, is about 10 ?m or less when a withdrawn distance of the adjacent internal electrodes from the end surface is about 1 ?m or less, and is about 20 ?m or less when a protruding length of the adjacent internal electrodes from the end surface is at least about 0.1 ?m. In an electroplating step, electroplating deposits deposited on the ends of the adjacent internal electrodes are grown so as to be connected to each other.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: January 1, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuo Kunishi, Yoshihiko Takano, Shigeyuki Kuroda, Akihiro Motoki, Hideyuki Kashio, Takashi Noji
  • Patent number: 8344261
    Abstract: Disclosed are a carrier substrate including an insulating base material with a copper foil layer formed on at least one surface thereof, a metal layer formed on the copper layer and having a length shorter than that of the copper foil layer, and an insulating layer formed on the metal layer, a fabrication method thereof, a printed circuit board (PCB) using the same, and a fabrication method thereof. Because there is no land at the via and core in the substrate, because a circuit pattern connected with the via can be formed to be finer, so the circuit pattern can be highly integrated and the substrate can become thinner. Thus, a printed circuit board (PCB) having a smaller size and reduced number of layers can be fabricated.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: January 1, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Won Lee, Keung Jin Sohn, Chang Gun Oh
  • Patent number: 8341834
    Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. A plurality of slots are formed in the sidewall of said interposer for the venting of gases and pressure therethrough.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 8341833
    Abstract: A method for manufacturing a printed circuit board having a substrate composed of an insulation material, a via hole formed in the substrate, and a via land formed around the opening of the via hole on a surface of the substrate includes processes of measuring deformation of the substrate having the via hole formed therein, calculating a position where the via land is to be patterned on the basis of the deformation of the substrate measured in the measurement process, and patterning the via land at a position corrected on the basis of the value calculated in the calculation process.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: January 1, 2013
    Assignee: Alps Electric Co., Ltd.
    Inventor: Hiroshi Kubota
  • Publication number: 20120325524
    Abstract: A flex-rigid wiring board has a first rigid wiring board having a first inner layer and a first terminal on the first inner layer, a second rigid wiring board having a second inner layer and a second terminal on the second inner layer, and a flexible wiring board connecting the boards and having third and fourth terminals on the flexible board. The first and second boards have openings and are positioned such that the boards are spaced apart and form a recess portion formed of the openings facing each other, the flexible board is in the recessed portion such that the first terminal is connected to the third terminal and the second terminal is connected to the fourth terminal, and the first board has an interlayer conductor through an insulation layer in the first board such that the conductor is not directly under the first terminal.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 27, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Nobuyuki NAGANUMA, Hidetoshi Noguchi
  • Publication number: 20120320556
    Abstract: Provided are a frame member having a reduced height, a frame unit, a mounting board unit, and a manufacturing method. The frame unit is to be attached to a board (200) on which an electronic component (210) is mounted and includes a frame member (120) having a side wall (123) to be connected to the board (200) and a first protruding portion (121) protruding inward or outward from the side wall, and a first member (110) detachably attached to the frame member and having a second protruding portion protruding toward the frame member to fit with the first protruding portion (121).
    Type: Application
    Filed: January 26, 2011
    Publication date: December 20, 2012
    Applicant: NEC CORPORATION
    Inventor: Toshinobu Ogatsu
  • Publication number: 20120320085
    Abstract: Example embodiments disclosed herein relate to display outputting a user interface.
    Type: Application
    Filed: April 29, 2011
    Publication date: December 20, 2012
    Inventors: Ping Mei, Warren Jackson
  • Patent number: 8333011
    Abstract: In an embodiment of the present invention a method for making an electronic assembly is provided. The method comprises positioning a substrate having a plurality of segmented portions. A first segmented portion has a first plurality of conductive traces terminating to form a first plurality of conductive pads. A second segmented portion has a second plurality of conductive traces terminating to form a second plurality of conductive pads. A flex circuit is placed onto the conductive pads. The flex circuit includes a third plurality of conductive traces terminating at a first end to form a first plurality of connecting pads and terminating at a second end to form a second plurality of connecting pads. Electronic components are electrically coupled to the first and second plurality of conductive traces to form a primary PCB and a daughter PCB. The connecting pads are electrically coupled to the conductive pads for electrically coupling the daughter PCB to the primary PCB.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: December 18, 2012
    Assignee: Autoliv ASP, Inc.
    Inventors: Charles Still, David R. Stoscup
  • Patent number: 8330052
    Abstract: A method for producing a joined structure, containing: after placing an anisotropic conductive film in the predetermined manner, placing a wiring member containing a wiring plate formed thereon, where the wiring plate has a resist region in which the wiring plate is covered with a resist layer, and a second electrode region in which the wiring plate is not covered with the resist layer, so that the edge of the resist region at a boundary with the second electrode region comes above the chamfer part of the substrate; and heating and compressing the anisotropic conductive film from the side of the wiring member to melt and make the anisotropic conductive film flow into the side of the resist region to thereby cover the second electrode region with the anisotropic conductive film, so as to electrically connect the first electrode region and the second electrode region.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 11, 2012
    Assignee: Sony Chemical & Information Device Corporation
    Inventors: Tomoyuki Ishimatsu, Yukio Yamada
  • Patent number: 8327534
    Abstract: Disclosed herein is a method for fabricating a printed circuit board assembly by adhering an element to a printed circuit board without using any solder. The printed circuit board may be fabricated by sequentially applying a conductor-containing first ink and an insulator-containing second ink onto a base substrate by ink-jet printing to form a printed circuit board, mounting an element on the printed circuit board such that an electrode of the element contacts a conductive layer and curing the conductive layer at a high temperature.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Young Park, Young Jun Moon, Hyun Joo Han, Gyun Heo, Kyung Woon Jang, Sang il Hong, Dong Seok Baek
  • Patent number: 8327533
    Abstract: A multilayer printed wiring board is manufactured by a method in which a core substrate is provided, an insulation layer including a thermosetting resin material is formed over the core substrate, an uncured resin layer including a thermoplastic resin material is placed on the insulation layer, the uncured resin layer is cured to form a resin complex layer including a resin complex comprising the thermosetting resin material and the thermoplastic resin material, and a conductive circuit is formed over the resin complex layer.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: December 11, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Kiyotaka Tsukada, Takamichi Sugiura
  • Publication number: 20120305293
    Abstract: According to an aspect of the invention, there is provided a circuit board assembly including a first circuit board including a first circuit pattern formed on a surface of the first circuit board, and an opening that is adjacent to the first circuit pattern; and a second circuit board including a second circuit pattern corresponding to the first circuit pattern and a protection film that is applied to a surface of the second circuit board so as to form a hollow place located corresponding to the opening, wherein the first circuit board and the second circuit board are combined with each other.
    Type: Application
    Filed: October 28, 2011
    Publication date: December 6, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-seok Kim, Inh-seok Suh, Tak-kyoum Kim
  • Patent number: 8322030
    Abstract: A method of making a substrate for a semiconductor package includes providing a laminated layer structure including a backing layer and a metal layer attached to the backing layer. A circuit layer is plated atop a first surface of the metal layer to form a circuit-on-metal structure. The circuit-on-metal structure is coupled to a dielectric layer by causing the dielectric layer to flow around the circuit layer to the first surface of the metal layer so that the circuit layer is embedded within the dielectric layer and the first surface of the metal layer is in direct contact with a first surface of the dielectric layer. The backing layer is then removed completely. The metal layer is then removed completely.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 4, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli
  • Publication number: 20120302074
    Abstract: A method and system for connecting a vertical printed circuit board with a horizontal printed circuit board where a contact device is biased in a first position when not contacting a vertical printed circuit board and is biased in a second position when the vertical printed circuit is coupled to the horizontal printed circuit board.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: Xirrus, Inc.
    Inventor: Abraham Hartenstein
  • Patent number: 8316532
    Abstract: A producing method of a wired circuit board includes the steps of preparing the wired circuit board, placing the wired circuit board on a support table, and applying light from above the wired circuit board toward the wired circuit board, and sensing pattern reflected light, table reflected light and foreign-matter reflected light to inspect the conductive pattern and the foreign matter based on a contrast therebetween. In the step of inspecting the conductive pattern and the foreign matter, a reflectance of the table reflected light is in a range of 25 to 55%, and a reflectance of the foreign-matter reflected light is in a range of not more than 10%.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 27, 2012
    Assignee: Nitto Denko Corporation
    Inventors: Yoshihiro Toyoda, Terukazu Ihara
  • Patent number: 8316533
    Abstract: A method for manufacturing a Micro-Electro-Mechanical System pressure sensor. The method includes forming a gauge wafer including a diaphragm and a pedestal region. The method includes forming an electrical insulation layer disposed on a second surface of the diaphragm region and forming a plurality of sensing elements patterned on the electrical insulation layer disposed on the second surface in the diaphragm region. The method includes forming a cap wafer with a central recess in an inner surface and a plurality of through-wafer embedded vias made of an electrically conductive material in the cap wafer. The method includes creating a sealed cavity by coupling the inner recessed surface of the cap wafer to the gauge wafer, such that electrical connections from the sensing elements come out to an outer surface of the cap wafer through the vias. The method includes attaching a spacer wafer with a central aperture to the pedestal region with the central aperture aligned to the diaphragm region.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: November 27, 2012
    Assignee: S3C, Inc.
    Inventors: James Tjanmeng Suminto, Mohammad Yunus
  • Patent number: 8316536
    Abstract: A method of making a semiconductor package substrate includes laser-ablating channels in the substrate. After the channels are ablated in the substrate, conductive material is added to fill the channels and cover the surface of the substrate. Then a photomask etching process simultaneously forms a circuit pattern above the surface of the substrate and removes excess metal above the channels, by removing metal above the surface only in patterned regions. The result is a two-level circuit pattern having conductors within and above the substrate.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: November 27, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, David Jon Hiner, Russ Lie
  • Patent number: 8312623
    Abstract: A device including a heat sensitive substrate and an electrical conductor disposed thereon is provided. In certain examples, the heat sensitive substrate may be configured to degrade at or above a sintering temperature. In other examples, the electrical conductor may be processed, prior to disposal on the heat sensitive substrate, at the sintering temperature on a second substrate that can withstand the sintering temperature. Methods and kits are also disclosed.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: November 20, 2012
    Assignee: Fry's Metals, Inc.
    Inventors: Oscar Khaselev, Nitin Desai, Michael T. Marczi, Bawa Singh
  • Patent number: 8314343
    Abstract: In a multi-layer substrate including a core formed with a plurality of holes capable of containing an electronic part, a bottom insulating resin layer formed on a bottom surface of the core, a top insulating resin layer formed on a top surface of the core, a wiring layer selectively formed on an outer layer of the bottom insulating resin layer or top insulating resin layer, and an electronic part contained in the holes, both of the bottom and top insulating resin layers have a structure that is a combination of a resin which is changed to cohesiveness when heated and which undergoes smaller plastic deformation when heated to a higher temperature and an insulating resin layer which has a thickness sufficient to maintain insulation between the electronic part or a conductor of the core and the wiring layer and which inherently undergoes small plastic deformation, so that the electronic part can be securely and sealed in the holes without using a particular adhesive.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: November 20, 2012
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yusuke Inoue, Eiji Mugiya, Masashi Miyazaki, Tatsuro Sawatari, Yuichi Sugiyama
  • Patent number: 8307546
    Abstract: A method for manufacturing a ceramic elements module. The method includes providing a ceramic elements that has a plurality of lower inserting grooves; mounting an electronic component on a lower surface of the ceramic elements; providing a heat sink that has a first penetrating hole corresponding to the lower inserting groove and a second penetrating hole into which the electronic component is inserted to a lower part of the ceramic elements; coupling the ceramic elements with the heat sink; engaging a fixing member with the lower inserting groove of the ceramic elements by passing through the first penetrating hole of the heat sink; and removing the fixing member.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: November 13, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Gyu Man Hwang, Dae Hyeong Lee
  • Patent number: 8309854
    Abstract: A rigid-flex printed circuit board module includes a non-working zone and a working zone. The non-working zone defines a receiving space. The working zone is disposed in the receiving space, and is connected to the non-working zone through a plurality of interconnecting zones. The interconnecting zones are flexible regions having greater flexibility than the non-working zone, and are of the same thickness and material. The interconnecting zones are defined by flexible circuit board member such that the interconnecting zones can be quickly cut off using a single machine during processing of the rigid-flex printed circuit board module. Thus, the speed of separating the working zone from the non-working zone can be increased, and costs and time associated with processing and manufacturing can be reduced. Additionally, the processing flow can be simplified, and the product quality of the working zone after cutting can be ensured.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: November 13, 2012
    Assignee: Wistron Corporation
    Inventors: Chien-Yi Huang, Chen-Liang Ku, Ko-Chin Lee
  • Patent number: 8310835
    Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive and/or active elements of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: November 13, 2012
    Assignee: Apple Inc.
    Inventors: Gloria Lin, Bryson Gardner, Jr., Joseph Fisher, Jr., Dennis Pyper, Amir Salehi
  • Publication number: 20120279771
    Abstract: A package structure comprising a first substrate, a second substrate, an encapsulation layer sandwiched between the first and second substrates, and at least one electronic component mounted on the first substrate and isolated from the second substrate by the encapsulation layer. At least one conducting hole is defined in the encapsulation layer to communicate the at least one electronic component with the second substrate. An inner wall of each of the at least one conducting hole is coated with a first metal layer to electrically connect the at least one electronic component to the second substrate.
    Type: Application
    Filed: June 15, 2011
    Publication date: November 8, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., AMBIT MICROSYSTEMS (ZHONGSHAN) LTD.
    Inventor: JUN-YI XIAO
  • Patent number: 8303752
    Abstract: Provided is a method of manufacturing a wiring board, in which: a composite adhesive sheet 20 is attached to one of the surfaces of a support substrate 10, and a double-sided CCL 30 is attached to the other surface. Then, in an integrated state of the above components, a multilayer wiring structure including a conductive layer and a resin insulating layer is formed on a metal layer 33 of the double-sided CCL 30 by a known build-up method. A thermally foamable adhesive layer 22 of the composite adhesive sheet 20 is then heated, thereby thermally decomposing a thermal foaming agent to generate gas, and the support substrate 10 is separated from the remaining bonded body. Thereafter, a carrier foil layer 32b and a copper foil layer 32a of a carrier-foil coated copper foil 32 are mechanically peeled from each other at a boundary between both the layers, thereby obtaining a wiring board 1.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: November 6, 2012
    Assignee: TDK Corporation
    Inventors: Kenichi Kawabata, Hiroshige Ohkawa
  • Patent number: 8302277
    Abstract: A method of manufacturing a module is provided that can alleviate a decrease in cutting yield. This method includes: a step of mounting, on a wiring board having a plurality of mounting regions enclosed by cutting lines on its upper surface, an electronic component in each of the mounting regions; a step of cutting the wiring board along the cutting lines; a step of forming a sealing resin layer so as to seal the electronic component to cover at least part of upper and side surfaces of the cut wiring board; and a step of cutting the sealing resin layer along cut portions (cutting lines) of the cut wiring board.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 6, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Koga, Shigenori Makino
  • Patent number: 8302299
    Abstract: A method of manufacturing a multilayer printed circuit board of a built-in electronic device provides a substrate having a copper clad laminate and a first dielectric layer. The first dielectric layer is laminated onto the copper clad laminate and has a cavity for accommodating the electronic device. A second dielectric layer is laminated onto the substrate and electronic device to produce a base circuit board with an embedded electronic device. A build-up circuit layer is formed on the base circuit board. The first and second dielectric layers are made of a plastic material.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 6, 2012
    Assignee: Unitech Printed Circuit Board Corp.
    Inventors: Cheng-Hsien Chou, Shun-Yueh Hsu, Kun-Chi Chen, Hung-Min Chen
  • Patent number: 8302300
    Abstract: A method for manufacturing multilayer printed circuit board includes steps below. A first copper clad laminate includes a central portion and a peripheral portion is provided. A group of concentric copper annular collars is formed by etching the peripheral portion. A second copper clad laminate and an adhesive layer is laminated on to the first copper clad laminate in a manner that the adhesive is sandwiched between the first copper clad laminate and the second copper clad laminate to form a multilayer substrate. A detection hole is formed run through the multilayer substrate. An offset distance is determined and plated through holes in the central portion of the multilayer substrate is formed based on the offset distance.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: November 6, 2012
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Ye-Ning Chen
  • Patent number: 8296944
    Abstract: A method for manufacturing a printed circuit board includes the steps of: providing a base board having a first surface layer; performing a first patterning process to the base board to form a bottom circuit on the first surface layer; forming a metal protection layer on the bottom circuit; performing a second patterning process to the metal protection layer to form a patterned metal protection layer; performing a build-up process to the base board to form a first built-up layer on the bottom circuit and the patterned metal protection layer; performing a third patterning process to the first built-up layer to form a first built-up layer circuit; performing a laser manufacturing process to the first built-up layer to form a cavity structure; and clearing the patterned metal protection layer.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: October 30, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Hung-Lin Chang, Chen-Chuan Chang
  • Patent number: 8296938
    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: October 30, 2012
    Assignee: RF Micro Devices, Inc.
    Inventors: Dan Carey, Jeffrey Scott Walker, Gary D. Messner
  • Patent number: 8296942
    Abstract: The invention provides a process for preparing a heatsink system for a heat generating electronic device, comprising the steps of: (a) providing a heat conducting substrate; (b) applying an insulating layer on the heat conducting substrate; and (c) applying a printed circuit on the isolating layer by means of a hot embossing system. The invention further provides a heatsink system obtainable by said process, comprising a heat conducting substrate, an insulating layer that is applied on the heat conducting substrate, and a printed circuit that is applied on the insulating layer, wherein the thickness of the part of the insulating layer which is arranged between the heat conducting substrate and the printed circuit is between 1 and 100 micron.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: October 30, 2012
    Assignee: Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek TNO
    Inventors: Frits Kornelis Feenstra, Jürgen Hackert
  • Publication number: 20120268899
    Abstract: A microelectronic package includes a microelectronic element including a first surface having contacts thereon, a second surface remote therefrom, and edge surfaces extending between the first and second surfaces. A reinforcing layer adheres to the at least one edge surface and extends in a direction away therefrom, the reinforcing layer not extending along the first surface of the microelectronic element. A conductive redistribution layer including a plurality of conductive elements extends from the contacts along the first surface and along a surface of the reinforcing layer beyond the at least one edge surface. An encapsulant overlies at least the reinforcing layer. The microelectronic element has a first coefficient of thermal expansion, the encapsulant has a second coefficient of thermal expansion, and the reinforcing layer has a third coefficient of thermal expansion that is between the first and second coefficients of thermal expansion.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Belgacem Haba, Teck-Gyu Kang
  • Patent number: 8291583
    Abstract: A packaging method for assembling a captive screw to a printed circuit board (PCB) includes the steps of providing a captive screw having a screw head, a threaded shank and a sleeve; pressing a fixture toward the screw head for a part of the threaded shank to exposed from a distal end of the sleeve, and then clamping the fixture on the sleeve; providing a PCB having through holes and a layer of solder provided thereon; using a tool to pick up the fixture and the captive screw and align the threaded shank with one through hole on the PCB; releasing the fixture and the captive screw from the tool for a flange at the distal end of the sleeve to extend into the through hole; heating, melting and then cooling to harden the solder layer, so that the sleeve is fixedly held to the PCB; and removing the fixture.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: October 23, 2012
    Inventor: Ting-Jui Wang
  • Patent number: 8294031
    Abstract: A solder resist coating for a rigid-flex circuit board contains one or more conductor tracks and at least one flex area. The solder resist coating has one or more movement gaps in the flex area of the circuit board. In addition, an electronic module is formed having at least one rigid-flex circuit board with a solder resist coating.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: October 23, 2012
    Assignee: Continental Automotive GmbH
    Inventors: Detlev Bagung, Michael Decker, Gregory Drew, Thomas Riepl, Bernd Roller
  • Patent number: 8294039
    Abstract: A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: October 23, 2012
    Assignee: Princo Middle East FZE
    Inventors: Chih-kuang Yang, Chieh-lin Hsing
  • Patent number: 8291585
    Abstract: A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the chip element (step of application electrically conductive paste). A chip element is formed in which the electrically conductive green sheet is attached to the end surface via the electrically conductive paste applied to the end surface of the chip element (step of attaching electrically conductive sheet). In the step of attaching, the end surface of the electrically conductive green sheet on the side of the side surfaces is positioned on the outside of the side surfaces, and the electrically conductive paste applied to the end surface is pressed out into a space between the electrically conductive green sheet and ridge portions.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: October 23, 2012
    Assignee: TDK Corporation
    Inventors: Ko Onodera, Satoshi Kurimoto, Hisayuki Abe, Taketo Sasaki, Yoji Tozawa, Osamu Hirose
  • Patent number: 8291581
    Abstract: A plurality of reference holes are formed in the surface of a first substrate made of a first material, and a plurality of columnar members are each fitted in the reference holes in such a manner that at least a part of each of the columnar members projects from the surface of the first substrate. Subsequently, an electrode surface layer made of a second material is formed on the surface of the first substrate in such a manner that an end portion of each of the columnar members are exposed at the surface and then the columnar members are removed. Thus obtained is a substrate-like electrode including at least an electrode surface layer provided with through holes having a cross section matching a sectional shape of the projecting portion of the columnar members.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 23, 2012
    Assignees: Mitsui Engineering & Shipbuilding Co., Ltd., ADMAP, Inc.
    Inventor: Fimitomo Kawahara
  • Patent number: 8294034
    Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 23, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
  • Patent number: 8286343
    Abstract: A method of manufacturing a wiring substrate includes forming a conducting layer on a first insulating layer including a first glass cloth; forming a photosensitive resist layer on the conducting layer; recognizing a first origin position on the first insulating layer; forming a mask on the resist layer by positioning the mask with respect to the first origin position, the mask being formed so as to position wiring patterns only on positions overlapping the first glass cloth in a planar view; and exposing the resist layer via the mask and forming the wiring patterns only on the positions overlapping the first glass cloth in the planar view.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 16, 2012
    Assignee: Fujitsu Limited
    Inventor: Makoto Suwada
  • Patent number: 8286345
    Abstract: Techniques for producing a flexible structure attached to a device. One embodiment includes the steps of providing a first substrate, providing a second substrate with a releasably attached flexible structure, providing a bonding layer on at least one of the first substrate and the flexible structure, adjoining the first and second substrate such that the flexible structure is attached at the first substrate by means of the bonding layer, and detaching the second substrate in such a way that the flexible structure remains on the first substrate.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roger Dangel, Laurent Dellmann, Michel Despont, Bert Jan Offrein, Stefano Sergio Oggioni
  • Publication number: 20120258634
    Abstract: An interface system may be used for connecting a mother board with a peripheral device board. The interface system may include a mother interface and a daughter interface. The mother interface may establish a connection portal for the mother board, and the daughter interface may establish a connection portal for the peripheral device board. The interface system may be equipped with a socket with multi-contact surface for providing high speed, high performance, and low noise data transmission. The interface system may be ruggedized with various stabilizing mechanisms, such that it may deliver consistent and reliable performance under harsh military and/or aerospace conditions.
    Type: Application
    Filed: March 19, 2012
    Publication date: October 11, 2012
    Inventors: FRANK MORANA, Mark Avzenberg
  • Patent number: 8281485
    Abstract: A method for producing a circuit board layer, in particular for a multilayer circuit board, a ceramic foil upon which a carrier foil is disposed being used, the carrier foil being perforated by laser to form at least one circuit trace, and/or the carrier foil and the ceramic foil being perforated together by laser to form at least one feedthrough, the circuit trace and/or the feedthrough subsequently being created by printing, the carrier foil constituting a printing screen, and the carrier foil subsequently being removed from the ceramic foil.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: October 9, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Peter Tauber, Tuncay Sentuerk, Ulrich Speh
  • Publication number: 20120246925
    Abstract: A method for manufacturing a printed wiring board includes preparing a core substrate having a first surface and a second surface on the opposite side of the first surface, forming on the first-surface side of the substrate a first opening portion tapering from the first toward second surface, forming on the second-surface side of the substrate a second opening portion tapering from the second toward first surface, forming a third opening portion such that a penetrating hole formed of the first opening portion, the second opening portion and the third opening portion connecting the first and second opening portions is formed in the substrate, forming a first conductor on the first surface of the substrate, forming a second conductor on the second surface of the substrate, and filling a conductive material in the penetrating hole such that a through-hole conductor connecting the first and second conductors is formed.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 4, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiaki Hibino, Takema Adachi
  • Publication number: 20120251055
    Abstract: Provided are an opto-electric hybrid board and a manufacturing method. The opto-electric hybrid board includes an optical waveguide unit and an electric circuit unit having an optical element mounted thereon. The optical waveguide unit includes socket portions for locating the electric circuit unit, which are formed on a surface of an undercladding layer and formed of the same material as a core. The socket portions are located at predetermined locations with respect to one end surface of a core. The electric circuit unit includes bent portions which are formed by bending a part of an electric circuit board so as to stand, for fitting into the socket portions. The bent portions are located at predetermined locations with respect to the optical element. The optical waveguide unit and the electric circuit unit are coupled in a state in which the bent portions fit into the socket portions.
    Type: Application
    Filed: March 1, 2012
    Publication date: October 4, 2012
    Applicant: NITTO DENKO CORPORATION
    Inventors: Akiko Nagafuji, Yuichi Tsujita, Masayuki Hodono, Masami Inoue
  • Patent number: 8276270
    Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 2, 2012
    Assignee: C. Uyemura & Co., Ltd.
    Inventors: Teruyuki Hotta, Shushi Morimoto, Takahiro Ishizaki, Hisamitsu Yamamoto
  • Patent number: 8278559
    Abstract: An assembly comprising a first printed circuit board, PCB, with a ball grid array, BGA, on its underside, a second PCB facing the first PCB and having at least one through-hole between its top and bottom surfaces, its top surface printed with a circuit pattern bonded to the BGA, a heat sink layer facing the bottom surface of the second PCB and having at least one thermally-conductive pin projecting normally into the through-hole or a respective one of the through-holes in the second PCB, and, for each pin, a thermally-conductive stud of the same cross-section as the pin, bonded to the BGA and disposed within the through-hole between the pin and the first PCB in thermal contact with the pin.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: October 2, 2012
    Assignee: Thales Holdings UK PLC
    Inventors: Emmanuel Loiselet, Phil Wills
  • Publication number: 20120244753
    Abstract: The invention relates to a multipole relief plug-in connector (10a, 10b) and to a multilayer circuit board (12a, 12b), the relief plug-in connector (10a, 10b) comprising a plurality of contact elements (14a, 14b), the contacting sections (16a, 16b) of which are arranged in height-offset contact area surfaces (18a, 18b), and the multilayer circuit board (12a, 12b) comprising several height-offset contact area surfaces (20, 20b) accordingly, and to a combination of a multipole relief plug-in connector (10a, 10b) for contacting with a multilayer circuit board (12a, 12b) and a multilayer circuit board (12a, 12b) for populating with the multipole relief plug-in connector (10a, 10b).
    Type: Application
    Filed: December 3, 2010
    Publication date: September 27, 2012
    Applicant: ERNI ELECTRONICS GMBH
    Inventor: Roland Moedinger
  • Publication number: 20120236464
    Abstract: A multi-layer substrate includes a ground structure, a plurality of dielectric layers on the ground structure and a plurality of conductive layers separating the plurality of dielectric layers. The conductive layers include a first conductive layer and a second conductive layer and a connection electrically coupling the first conductive layer and the second conductive layer. The first conductive layer and the ground structure are configured to define a first parasitic capacitance there between and the first conductive layer and the second conductive layer are configured to define a second, negating parasitic capacitance there between.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 20, 2012
    Inventors: Thomas A. Hertel, Erich H. Soendker, Horacio Saldivar