Assembling Bases Patents (Class 29/830)
  • Patent number: 8502086
    Abstract: Wiring board bases 2 to 4 are provided with: insulating substrates 1a to 4a having conductive layers 1b to 4b provided on one surfaces thereof, respectively; through-holes 2e to 4e which are arranged on the insulating substrates and reach the conductive layers from the other surfaces; and conductive vias 2d to 4d connected to the conductive layers by filling the through-holes with a conductive paste. In a method for manufacturing a laminated wiring board, at least one of the wiring board bases is stacked. Before the through-hole is filled with the conductive paste, a surface portion, in the through-hole, of the conductive layer is smoothed and a smooth surface portion 2g is formed.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: August 6, 2013
    Assignee: Fujikura Ltd.
    Inventor: Takaharu Hondo
  • Patent number: 8495815
    Abstract: An electromagnetic shielding method includes the steps of disposing a flexible electromagnetic shielding film including a laminate of at least an insulating layer and a conductive metal layer to cover a portion to be electromagnetically shielded on a printed wiring board so that the insulating layer faces the printed wiring board, the conductive metal layer having a higher melting temperature than that of the insulating resin layer; and heating the electromagnetic shielding film to a temperature to melt and contract the insulating layer, thereby bonding the conductive metal layer to a grounding conductor of the printed wiring board and electrically connecting the conductive metal layer to the grounding conductor. The heating temperature is higher than the melting temperature of the insulating layer and lower than the melting temperature of the conductive metal layer.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: July 30, 2013
    Assignee: Sony Mobile Communications, Inc.
    Inventors: Koichi Izawa, Yumi Ogura
  • Patent number: 8497431
    Abstract: The circuit-connecting material for connection between circuit members each having a board and a circuit electrode formed on the primary surface of the board, comprising an adhesive composition that cures in response to light or heat and an organic compound containing a urethane group and an ester group.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: July 30, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Motohiro Arifuku, Nichiomi Mochizuki, Takashi Nakazawa, Kouji Kobayashi, Tohru Fujinawa, Takashi Tatsuzawa
  • Publication number: 20130188350
    Abstract: Electrical connectors for attachment to electrical contacts of light emitting devices as well as light emitting device packages and lamp assemblies that use such connectors are provided. Further, methods for assembling light emitting device packages that use such connectors are provided. The electrical connector, for example, can have a plug housing with an electrically conductive socket engaging connection for engaging a socket. The electrical connector can also have an electrically conductive member extending from the plug housing and connected to the socket engaging connection. The electrically conductive member can have an end distal from the plug housing that forms a contact base configured to attach to an electrical contact on a light emitting device.
    Type: Application
    Filed: December 21, 2012
    Publication date: July 25, 2013
    Applicant: Cree, Inc.
    Inventor: CREE, Inc.
  • Publication number: 20130186678
    Abstract: Provided is a highly accurately alignable substrate set, the cost of which is kept low. In the substrate set, a light source FPC substrate (11) has a notch (16), and an anode pad (13) and a cathode pad (14) that are disposed so as to sandwich the notch (16) therebetween, and a panel FPC substrate (21) has a plus terminal (23) and a minus terminal (24) that are disposed so as to be in contact with the anode pad (13) and the cathode pad (14), and an opening (26) that is sandwiched between the plus terminal (23) and the minus terminal (24).
    Type: Application
    Filed: January 6, 2011
    Publication date: July 25, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Eiji Koike, Yukihiro Sumida, Toshiteru Nakawaki
  • Patent number: 8490282
    Abstract: According to one feature of the present invention, a method of manufacturing a porous catcher includes providing a catcher face material layer; forming pores in the catcher face material layer using a first etching process that is controlled by a first photolithographic mask; providing a reinforcing structure material layer that is in mechanical contact with the porous catcher face; forming openings in the reinforcing structure material layer using a second etching process that is controlled by a second photolithographic mask; and fluidically connecting the openings in the reinforcing structure and the pores of the catcher face using a material removal process.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: July 23, 2013
    Assignee: Eastman Kodak Company
    Inventors: Shan Guan, Yonglin Xie, Chang-Fang Hsu
  • Publication number: 20130180764
    Abstract: A flexible printed circuit may be provided with an integrated heat and pressure spreading layer. The heat and pressure spreading layer may be configured to uniformly spread heat and pressure from a bonding tool across a portion of the flexible printed circuit during bonding of the flexible printed circuit to additional circuitry. During manufacturing of the flexible printed circuit, a sheet of heat and pressure spreading material may be attached to a sheet of flexible printed circuitry and the heat and pressure spreading material and the sheet of flexible printed circuitry may be die cut to form multiple flexible printed circuits each with a heat and pressure spreading layer. An electronic device may be provided with a flexible printed circuit with a heat and pressure spreading layer coupled to a component such as a display.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Inventors: Joshua G. Wurzel, Casey J. Feinstein
  • Patent number: 8488326
    Abstract: A memory support structure includes a base for physically and electrically connecting to a substrate. When so connected, the memory support structure extends orthogonal to the substrate to a height of at least 2.5 cm. The memory support structure provides at least three sockets for receiving and engaging memory modules so that they extend parallel to the substrate. The memory support structure also includes electrical pathways for electrically connecting the sockets and the base so that a memory module inserted into one of said sockets is electrically connected to the substrate.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: July 16, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Vincent Nguyen
  • Patent number: 8484829
    Abstract: Methods of manufacturing low profile magnetic components configured as a power management devices for an electrical system of an electronic device involve prefabricated coil windings assembled with a plurality of flexible dielectric sheet layers, and laminating the plurality of flexible dielectric sheets around the prefabricated coil windings to form a dielectric body having a low profile chip configuration attachable to the electronic device.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: July 16, 2013
    Assignee: Cooper Technologies Company
    Inventors: Daniel Minas Manoukian, Robert James Bogert
  • Patent number: 8484839
    Abstract: Provided are processes for making multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 16, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Pui-Yan Lin, Govindasamy Paramasivam Rajendran, George Elias Zahr
  • Patent number: 8484832
    Abstract: There is provided a method of producing a printed circuit board incorporating a resistance element capable of adjusting resistance after the resistance element has been formed and assuring a high accurate resistance. A method of producing a printed circuit board incorporating a resistance element using carbon paste includes the steps of: forming through holes 5, 6, 25 and 26 or a bottomed hole in a double-sided copper clad laminate; applying noble metal plating into the through hole or the bottomed hole; filling the through hole or the bottomed hole with carbon paste; subjecting the carbon paste with which the thorough hole or the bottomed hole is filled to noble metal plating, conducting treatment and plating to form a conductive layer; forming an opening 18 in the conductive layer on the end of the through hole filled with the carbon paste; and performing trimming through the opening to adjust the resistance of the resistor formed by the carbon paste.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: July 16, 2013
    Assignee: Nippon Mektron, Ltd.
    Inventor: Garo Miyamoto
  • Publication number: 20130176692
    Abstract: For a method for producing a circuit board consisting of a plurality of circuit board areas, wherein the individual circuit board areas comprise at least one layer made of an in insulating base material and a conducting pattern located on or in the base material, the following is provided: a substrate material, at least one registration mark formed in the substrate material, a first circuit board area arranged on the substrate material, at least one additional circuit board area, which substantially adjoins the first circuit board area or at least partially overlaps the first circuit board, the additional circuit board areas being oriented relative to the registration mark, and a plurality of connections of the conducting patterns of the first circuit board area and of the at least one additional circuit board area. Thus improved registration and orientation can be achieved when circuit board areas are coupled.
    Type: Application
    Filed: September 14, 2011
    Publication date: July 11, 2013
    Applicant: AT & S Austria Technologie & Systemtechnik Aktieng
    Inventors: Nikolai Haslebner, Markus Leitgeb, Michael Gossler, Mike Morianz
  • Patent number: 8479388
    Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 8481858
    Abstract: The invention relates to a method for producing a non-developable surface printed circuit and to the thus obtained printed circuit. According to the invention, each electrically conductive pattern of a printed circuit includes at least one base, which is arranged on the non-developable surface and obtained by projecting an electrically conductive varnish, and a coating, which is arranged on the base and made of an electrically well conductive material by buffer electrolysis.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: July 9, 2013
    Assignee: Astrium SAS
    Inventor: Christian Desagulier
  • Patent number: 8479385
    Abstract: A method of producing a wiring substrate includes producing a substrate body including a first primary surface on which a semiconductor chip mounting area is provided and a second primary surface opposed to the first primary surface; attaching a stiffener member on the first primary surface, the stiffener member including an opening which the semiconductor chip mounting area is exposed from; and connecting lead pins to corresponding connection pads provided on the second primary surface by way of electrically conductive members.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 9, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Hiroyuki Miyazawa
  • Patent number: 8479389
    Abstract: A method of manufacturing a flex-rigid wiring board including disposing a flexible board comprising a flexible substrate and a conductor pattern formed over the flexible substrate and a non-flexible substrate adjacent to each other, covering a boundary between the flexible board and the non-flexible substrate with an insulating layer comprising an inorganic material, providing a conductor pattern on the insulating layer, forming a via hole opening which passes through the insulating layer and reaches the conductor pattern of the flexible board, and plating the via hole opening to form a via connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 9, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Michimasa Takahashi, Masakazu Aoyama
  • Patent number: 8481861
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 9, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Publication number: 20130161073
    Abstract: A method of manufacturing a multi-layer circuit board includes: forming a first circuit layer on a first surface of a first prepreg; stacking a second prepreg on a first surface of the first circuit layer; and forming at least one of a second or a third circuit layer on at least one of a first surface of the second prepreg and a second surface opposite of the first surface of the first prepreg, wherein, in the stacking of the first prepreg, the first prepreg and the second prepreg are semi-cured.
    Type: Application
    Filed: October 24, 2012
    Publication date: June 27, 2013
    Applicant: SAMSUNG TECHWIN CO., LTD.
    Inventor: SAMSUNG TECHWIN CO., LTD.
  • Publication number: 20130162276
    Abstract: Provided is a probe card including a plurality of unit plates including pad areas and contact probe areas, a plurality of electrode pads formed in the pad areas, a plurality of contact probes formed in the contact probe areas, and a plurality of interconnecting layers electrically connecting the electrode pads and the contact probes. The plurality of unit plates has different sizes and are arranged and laminated so as to expose all the pad areas of each unit plate.
    Type: Application
    Filed: September 7, 2011
    Publication date: June 27, 2013
    Applicant: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Hak Joo Lee, Jung Yup Kim, Jun-Hyub Park
  • Patent number: 8468693
    Abstract: A dielectric device has a first conductor and a dielectric disposed thereon. An intermediate region is formed between the first conductor and dielectric. In the intermediate region, an additive different from the first conductor and dielectric and the dielectric are mixed with each other. The additive contains at least one element of Si, Al, P, Mg, Mn, Y, V, Mo, Co, Nb, Fe, and Cr.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: June 25, 2013
    Assignee: TDK Corporation
    Inventors: Tomohiko Katoh, Kenji Horino, Yuko Saya
  • Publication number: 20130155150
    Abstract: A process for producing a liquid ejection head including a recording element substrate, an electrical wiring substrate provided with plural lead terminals, a support member provided with a concavity and a joining surface, and a sealant control wall arranged between a side surface of the recording element substrate and a side surface of the support member, the process including preparing a liquid ejection head in which the concavity and recording element substrate are mutually fixed, the joining surface and electrical wiring substrate are mutually fixed, and the lead terminals and connection terminal are mutually connected, and filling the sealant between the side surface of the recording element substrate and the side surface of the sealant control wall on the side of the recording element substrate followed by filling the sealant between a side surface of the sealant control wall on the side of the lead terminals and the lead terminals.
    Type: Application
    Filed: November 29, 2012
    Publication date: June 20, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Canon Kabushiki Kaisha
  • Publication number: 20130148311
    Abstract: The invention discloses a double-layer PCB of a low power wireless sensing system and a manufacturing method thereof. The low power wireless sensing system includes a first layer and a second layer. The first layer comprises a wireless communication module, a power amplifying module, a USB module, a balun module, an antenna module, a low-frequency oscillator and a high-frequency oscillator. According to the double-layer PCB of the low power wireless sensing system and the manufacturing method thereof, a circuit layout can be performed on the double-layer PCB to reduce volume of the PCB.
    Type: Application
    Filed: June 14, 2012
    Publication date: June 13, 2013
    Inventors: Chia-Chi CHANG, Jang Ping Sheu
  • Publication number: 20130146349
    Abstract: The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.
    Type: Application
    Filed: June 4, 2012
    Publication date: June 13, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventor: Han Ul Lee
  • Patent number: 8462510
    Abstract: A board-level package includes a printed circuit board, a semiconductor die package mounted on the printed circuit board, a tuned mass structure, and a support structure mounted to the printed circuit board and supporting the tuned mass structure.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Po-Yao Lin
  • Patent number: 8458888
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is movable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony K. Stamper, John G. Twombly
  • Patent number: 8453323
    Abstract: A method for manufacturing a printed circuit board, including providing a core substrate having an electronic component accommodated in the core substrate; forming a positioning mark on the core substrate; forming an interlayer insulating layer over the core substrate, the positioning mark and the electronic component; forming a via hole opening connecting to the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate; and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the electronic component.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: June 4, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Patent number: 8453314
    Abstract: A process for fabricating an origami formed antenna radiating structure is provided. In one embodiment, the invention relates to a process for precisely fabricating a radio frequency (RF) antenna structure, the process including providing a flexible circuit substrate, forming a plurality of parallel channels in the flexible circuit substrate in a first direction, mounting the flexible substrate to a precision die, pressing the flexible substrate into the precision die using an elastomeric material thereby sandwiching the flexible substrate between the elastomeric material and the precision die, and applying heat to the flexible substrate sandwiched between the elastomeric material and the precision die.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 4, 2013
    Assignee: Raytheon Company
    Inventors: Alberto F. Viscarra, Ethan S. Heinrich, Melvin S. Campbell, David T. Winslow, Kevin C. Rolston, Rosalio S. Vidaurri
  • Patent number: 8453321
    Abstract: A method for manufacturing a multilayer FPCB which includes providing a first substrate, a second substrate and a binder layer; defining an opening on the binder layer; defining a first slit in the dielectric layer of the first substrate; laminating the first substrate, the binder layer and the second substrate; forming a second slit in the conductive layer of the first substrate, the second slit being created so as to align with the first slit, cutting the first substrate, the binder layer and the second substrate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: June 4, 2013
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Jun-Qing Zhang, Chih-Yi Tu, Szu-Min Huang
  • Publication number: 20130135836
    Abstract: A first printed circuit board (PCB) assembly can include an embedded electrical connector configured to be mechanically coupled to a corresponding tab-shaped portion of a second PCB assembly, such as to permit insertion of the tab-shaped portion of the second PCB assembly into the embedded electrical connector when the second PCB assembly is aligned in a specified orientation. In an example, the second PCB assembly can include an approximately planar conductive antenna.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 30, 2013
    Inventors: John Clark Roberts, Robert Wayne Ridgeway
  • Publication number: 20130128472
    Abstract: The present invention discloses a printed circuit board and a manufacturing method thereof. The manufacturing method of the printed circuit board includes: forming a first circuit pattern on a metal layer formed on one surface of a base substrate; forming a second circuit pattern after laminating a first insulating layer in which the first circuit pattern is embedded; sequentially laminating a second insulating layer and a preliminary third circuit pattern on the second circuit pattern; separating the base substrate and forming a hole in the separated substrate; and forming a third circuit pattern, a landless first fill-plating layer, and a second fill-plating layer by performing fill-plating on the entire surface of the substrate in which the hole is formed, forming an insulating film layer on the other surface of the substrate, and performing an etching process on one surface and the other surface of the substrate.
    Type: Application
    Filed: May 31, 2012
    Publication date: May 23, 2013
    Applicant: Samsung Electro-Mechanics
    Inventors: Kyung Don MUN, Kil Yong Yun
  • Patent number: 8447566
    Abstract: A mounting condition determining method including: obtaining mounting information including information related to component mounting operations scheduled to be performed by a mounter (S1); judging, using the mounting information obtained in the obtaining: which production mode between a synchronous mode and an asynchronous mode is suitable for the scheduled component mounting operations; or which production mode between an alternating mode and an independent mode is suitable for the scheduled component mounting operations (S2, S3); and selecting the production mode indicated by a result of the judgment in the judging, as the production mode to be executed by the mounter (S5, S6).
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventor: Yasuhiro Maenishi
  • Patent number: 8446736
    Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Takayuki Kita, Masaaki Katsumata, Tadashi Nakamura, Kota Fukasawa, Kazuhiro Furugoori
  • Publication number: 20130122833
    Abstract: A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 16, 2013
    Applicant: QUALCOMM Incorporated
    Inventor: QUALCOMM Incorporated
  • Patent number: 8440916
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Publication number: 20130112012
    Abstract: A device forming a pressure sensor is provided. The device includes: a substrate made of electrical insulation material including a first reservoir, a second reservoir in communication with the first reservoir and of which two internal walls are each equipped with an electrode, and a flexible membrane made of an electrical insulation material, including a protuberance and secured to the substrate so as to enable movement of the protuberance between a position in which it is at a distance from a liquid filling the first reservoir and at least one second position in which it exerts a pressure on the liquid, thus discharging it at least partially from the first reservoir toward the second reservoir with mechanical contact with the two electrodes, the mechanical contact of the liquid with the electrodes establishing a resistance or capacitance between the electrodes. Application in the production of a touch screen is also provided.
    Type: Application
    Filed: April 7, 2011
    Publication date: May 9, 2013
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Mohamed Benwadih
  • Publication number: 20130114251
    Abstract: An illuminant device includes at least an illuminant element and a lamp holder including a housing, a metal core printed circuit board (MCPCB) and a power-driving unit. The housing includes a first side and a second side opposite to the first side. The MCPCB is disposed on the first side of the housing and includes a base and a plurality of extending parts extended from the circumference of base in a bending forming manner and spaced from each other. The base has a plurality of holes, the extending parts are embedded within the housing, and the illuminant element is mounted on the base. The power-driving unit includes a circuit board, and a first end of the circuit board has a plurality of posts. The posts are respectively penetrated the holes and electrically connected to the MCPCB. In addition, a manufacturing method of the lamp holder is disclosed.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 9, 2013
    Inventor: Qiang-Fei DUAN
  • Patent number: 8436254
    Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 7, 2013
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Po Yu, Han-Pei Huang
  • Patent number: 8434222
    Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Doyle, Joseph Kuczynski, Kevin A. Splittstoesser, Timothy J. Tofil
  • Publication number: 20130105212
    Abstract: A multilayer insulating substrate with excellent electrical characteristics and a method for manufacturing the multilayer insulating substrate.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 2, 2013
    Applicant: Japan Electronic Materials Corp.
    Inventor: Japan Electronic Materials Corp.
  • Publication number: 20130107486
    Abstract: An apparatus comprising: first and second circuit boards with respective electrodes thereon, the first and second circuit boards in a bonded configuration; One or more first layers positioned to be proximal to the one or more of the electrodes; electrolyte proximal to the respective electrodes; one or more second layers configured to provide for the bonded configuration in which the first and second circuit boards are bonded together, under curing, such that the respective one or more first layers are positioned between the one or more second layers and the electrodes, the bonding defining a chamber therebetween with the electrodes therein and facing one another, the chamber comprising the electrolyte; and wherein the one or more first layers are configured to inhibit interaction of the electrolyte with the one or more second layers during curing.
    Type: Application
    Filed: August 21, 2012
    Publication date: May 2, 2013
    Inventor: Pritesh HIRALAL
  • Patent number: 8429800
    Abstract: In an exemplary method a piezoelectric wafer is prepared on which multiple piezoelectric frames are formed. Each frame has a piezoelectric vibrating piece including excitation electrodes, and a frame portion surrounds the vibrating piece. A lid wafer is prepared on which multiple respective lids are formed, each sized substantially similarly to the respective frames. A base wafer is prepared on which multiple of bases are formed, each sized substantially similarly to the respective frames. Each base has through-holes. Stripes of a first bonding film are formed on both major surfaces of the piezoelectric wafer around the periphery of each frame. Stripes of a second bonding film are formed on the inner major surface of the lid wafer, corresponding to respective stripes of the first bonding film. Stripes of a third bonding film are formed on the inner major surface of the base wafer, corresponding to respective stripes of the first bonding film.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: April 30, 2013
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Hiroshi Kawahara, Ryoichi Ichikawa
  • Patent number: 8429809
    Abstract: A method for manufacturing a mirror device is presented. The method includes forming a mirror from a first substrate and forming a hinge/support structure from a second substrate. The hinge/support structure is formed with a recessed region and a torsional hinge region. The mirror is attached to the hinge/support structure at the recessed region. Further, a driver system is employed to cause the mirror to pivot about the torsional hinge region.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 30, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: John W. Orcutt
  • Patent number: 8431835
    Abstract: A method for making a packaging device for an electronic element includes: preparing a ceramic frame body defined with a hollow space for receiving the electronic element therein; preparing a ceramic substrate having a copper layer formed thereon; etching the copper layer to form a predetermined copper pattern on an upper surface of the ceramic substrate; placing the ceramic frame body onto the upper surface of the ceramic substrate and in contact with the copper pattern; and heating the ceramic frame body and the ceramic substrate such that the copper pattern bonds the ceramic frame body to the ceramic substrate. A packaging device for an electronic element is also disclosed.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: April 30, 2013
    Assignee: High Conduction Scientific Co. Ltd.
    Inventors: Wen-Chung Chiang, Keng-Chung Wu, Ying-Chi Hsieh, Cheng-Kang Lu, Ming-Huang Fu
  • Patent number: 8429813
    Abstract: A method of manufacturing an electrical device that is electrically and mechanically connectable to another electrical device is presented. The electrical device includes a face equipped with contact pads. The method includes applying an adhesive layer on the face equipped with contact pads. The adhesive layer is composed of a substance with adhesive properties. The method further includes creating a plurality of openings through the adhesive layer over each contact pad, and growing, electrolessly or electrochemically, small metal sticks in the areas where the openings have been created to form a plurality of conductive paths over each contact pad, the volume of which is defined by the openings.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: April 30, 2013
    Assignee: Gemalto SA
    Inventor: Beatrice Bonvalot
  • Publication number: 20130099802
    Abstract: Devices and methods are provided that facilitate improved input device performance. The devices and methods utilize a first substrate with proximity sensor electrodes and at least a first force sensor electrode disposed on the first substrate. A second substrate is physically coupled to the first substrate, where the second substrate comprises a spring feature and an electrode component. The electrode component at least partially overlaps the first force sensor electrode to define a variable capacitance between the first force sensor electrode and the electrode component. The spring feature is configured to facilitate deflection of the electrode component relative to the first force sensor electrode to change the variable capacitance. A measure of the variable capacitance may be calculated and used to determine force information regarding the force biasing the input device.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 25, 2013
    Applicant: SYNAPTICS INCORPORATED
    Inventors: Lin-Hsiang Hsieh, Richard R. Schediwy
  • Patent number: 8426740
    Abstract: A metal base circuit board, having an insulating layer with a linear expansion coefficient of 60 ppm per degree C. or higher and 120 ppm per degree C. or lower, a metal foil provided on one side of the insulating layer, comprising a metal material with a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C. or lower, a circuit portion and a non-circuit potion having a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: April 23, 2013
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Taiki Nishi, Takeshi Miyakawa, Kiyokazu Yamazaki, Takashi Saiki
  • Patent number: 8424202
    Abstract: A process for fabricating a circuit board is provided. A circuit substrate having a first surface and a first circuit layer is provided. A first dielectric layer having a second surface is formed on the circuit substrate and covers the first surface and the first circuit layer. An antagonistic activation layer is formed on the second surface. The antagonistic activation layer is irradiated by a laser beam to form at least a blind via extended from the antagonistic activation layer to the first circuit layer and an intaglio pattern. A first conductive layer is formed inside the blind via. A second conductive layer is formed in the intaglio pattern and the blind via. The second conductive layer covers the first conductive layer and is electrically connected with the first circuit layer through the first conductive layer. The antagonistic activation layer is removed to expose the second surface.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: April 23, 2013
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
  • Publication number: 20130093296
    Abstract: An electric motor that includes an electronic motor controller is described. The electronic motor controller includes a motor management circuit and a power supply circuit physically separate from the motor management circuit. The motor management circuit includes an insulated metal substrate, driver components operably attached to the insulated metal substrate and operable to provide output signals for application to windings of the electric motor, at least one current sensor operable for sensing an amount of current applied to the windings of and electric motor, and at least one control device operably attached to the insulated metal substrate for controlling operation of the driver components. The power supply circuit includes a composite circuit card and power processing components operably attached to the circuit card and operable to convert an input voltage into at least one output voltage to be supplied to the motor management circuit.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Inventors: Steven Peter Camilleri, Lyell Douglas Embery, Byron John Kennedy
  • Patent number: 8418361
    Abstract: Method of manufacturing printed circuit board, including: providing a substrate including a first circuit layer having a lower land of a via; forming an insulating layer on the first circuit layer; forming a via hole in the insulating layer; filling the via hole with a first metal, thus forming a via; forming a seed layer with a second metal on the insulating layer and an exposed surface of the via; applying a resist film on the seed layer, and forming a resist pattern having an opening for a second circuit layer with a width formed on the via being smaller than a width of the via; plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and removing the resist film, and selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 16, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Won Lee, Chang Gun Oh, Mi Sun Hwang
  • Patent number: 8418331
    Abstract: Provided is a method for fabricating a duplexer. The method includes fabricating an embedded PCB having an isolation part built therein and forming pads on certain areas of an upper side of the embedded PCB to connect with an external terminal. Further, a first filter and a second filter are separately fabricated, each having at least one film bulk acoustic resonator which is fabricated by depositing a lower electrode, a piezoelectric layer, and an upper electrode in this respective order. Thereafter, the first and second filters are bonded onto the pads formed on the embedded PCB. The entire surface of the embedded PCD is packaged at a predetermined distance from the first and second filters.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-sik Hwang, Yun-kwon Park, Il-jong Song, Byeoung-ju Ha