Assembling Formed Circuit To Base Patents (Class 29/831)
  • Patent number: 8178959
    Abstract: An electrical connection support for receiving a semiconductor component includes an electrical connection plate having electrical connection pads. A stand-off structure is provided over the electrical connection pads. The stand-off structure may include a supplementary layer provided on a zone of the electrical connection plate which includes the electrical connection pads of the plate and is outside of a place configured to receive a semiconductor component. The stand-off structure further includes electrical connection vias passing through the supplementary layer. These vias are electrically connected to the electrical connection pads of the plate and have outer faces for making external electrical connection (for example, to another electrical connection support in a stacked structure).
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: May 15, 2012
    Assignee: STMicroelectronics (Grenoble) SAS
    Inventors: Jerome Lopez, Richard Remert
  • Patent number: 8171623
    Abstract: A methodology for connecting device components with circuitry located at different levels and orientations relative to one another is described. First circuitry can be located on a multi-plane rigid circuit board where the multi-plane rigid circuit board can include at least one flexible member sharing a common substrate with the multi-plane rigid circuit board that extends from a body portion of the multi-plane rigid circuit board. The flexible member can include traces used to convey power and/or data and an interface coupled to the power and/or data traces. The flexible member can be deflected or twisted to connect first circuitry on the body portion of the multi-plane rigid circuit board to second circuitry associated with another device component.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 8, 2012
    Assignee: Apple Inc.
    Inventors: Stephen R. McClure, Joshua D. Banko, John P. Ternus
  • Patent number: 8171622
    Abstract: Disclosed is a flexible printed circuit, comprising a substrate, and a silver foil and a reinforcement plate attached on said substrate in order, wherein there is an ink layer between said silver foil and said reinforcement plate. According to the invention, by printing the ink onto the silver foil and then attaching the reinforcement plate, especially printing the ink in the form of a dot, strip or mesh, the total thickness of the flexible printed circuit will not increase while the surface roughness of the silver foil increases, resulting in increase of adhesion of the reinforcement plate. This strengthens the attachment between the reinforcement plate and the silver foil, meeting the requirement of peeling-resistant strength between the reinforcement plate and the silver foil.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: May 8, 2012
    Assignee: BYD Company Limited
    Inventor: Hua Zhang
  • Publication number: 20120103085
    Abstract: A thermal flow sensor integrated circuit for sensing flow in a channel based on temperature measurements, the integrated circuit having a temperature sensing element (30) on a front side of the integrated circuit arranged to face the channel, and a bond pad (60, 200) coupled electrically to the temperature sensing element, for making electrical contact off the integrated circuit, the bond pad being arranged to face away from the channel. By having the bond pad facing away from the channel, the space needed for the bond pad and any connections to it need not extend beyond the temperature sensing element and get in the way of the channel. Hence the temperature sensing element can be located closer to the channel or in the channel to enable measurements with better response time and sensitivity.
    Type: Application
    Filed: July 16, 2010
    Publication date: May 3, 2012
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jaap Roger Haartsen, Ronald Dekker, Pascal De Graaf, Nicolaas Johannes Anthonius Van Veen, Alphonsus Tarcisius Jozef Maria Schipper
  • Publication number: 20120104103
    Abstract: A matching network is integrated into a multilayer printed circuit board containing an RFID integrated circuit to provide both an antenna and a matching network for the RFID integrated circuit in the ultra high frequency regime.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: NXP B.V.
    Inventor: Giuliano MANZI
  • Patent number: 8166647
    Abstract: A printed circuit board and a method for manufacturing the printed circuit board are disclosed. The method can include; providing an insulated layer, in which a first metal layer is formed on one side of the insulated layer; forming a groove on the insulated layer; forming a metallic substance on an inner side of the groove and on another side of the insulated layer; and forming a first circuit pattern on at least one of one side of the insulated layer and the metallic substance formed on the groove by removing a portion of the first metal layer. The present invention provides the printed circuit board having a high efficiency of heat emission by disposing a heat sink in direct contact with a board and the method of manufacturing the printed circuit board.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 1, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun-Oh Hwang, Jee-Soo Mok, Jun-Heyoung Park, Kyung-Ah Lee, Eung-Suek Lee
  • Patent number: 8166653
    Abstract: A method of manufacturing a printed circuit board (PCB) having embedded resistors, including providing a PCB on which internal layer circuit patterns, including electrode pads, are formed; layering insulating layers on the PCB; forming first via holes on the electrode pads and simultaneously forming second via holes at predetermined locations on the internal layer circuit patterns; forming contact pads for connecting the electrode pads with resistors by filling the first via holes with oxidation-resistant conductive material and flattening the oxidation-resistant conductive material; forming the resistors so that ends of each resistor are connected to two respective contact pads, which are spaced apart from each other; forming circuit patterns on the PCB, in which the second via holes are formed; and layering insulting layers on the PCB having the formed circuit patterns, and forming external layer circuit patterns.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: May 1, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hwa Sun Park, Tae Eui Kim
  • Patent number: 8166649
    Abstract: A sheet in an electronic display is composed of a substrate containing an array of wire electrodes. The wire electrodes are preferably electrically connected to patterned transparent conductive electrode lines. The wire electrodes are used to carry the bulk of the current. The wire electrodes are capable of being extended away from the substrate and connected directly to the printed circuit board. The transparent conductive electrode (TCE) is used to spread the charge or voltage from the wire electrode across the pixel. The TCE is a patterned film and must be at least 50% transparent, and, for most applications, is preferably over 90% transparent. In most applications, the electroded surface of the electroded sheet has to be flattened. Use of a thin polymer substrate yields a light, flexible, rugged sheet that may be curved, bent or rolled.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 1, 2012
    Assignee: Nupix, LLC
    Inventor: Chad B. Moore
  • Patent number: 8163329
    Abstract: A method includes steps of (1a) preparing a hydrophilic first liquid, (1b) preparing a component-dispersing liquid where the component is dispersed in a second liquid, (1c) preparing a substrate having a hydrophilic region and a water-repellant region, (2) disposing the first liquid to the hydrophilic region, (3) bringing the component-dispersing liquid in contact with the first liquid disposed on the hydrophilic region, and (4) removing the first liquid and the second liquid from the substrate to dispose the component on the hydrophilic region. The hydrophilic region includes a component-mounting region and a liquid-capturing region surrounding the component-mounting region. The surface of the liquid-capturing region has a material represented by X—(CH2)n—Si-(substrate), where X represents N+R3Q? (Q represents Cl, Br, or I), OR, or halogen atom, R represents lower alkyl group with a carbon number of 1-4, and n represents a natural number of 1, 2, or 3.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventor: Hidekazu Arase
  • Patent number: 8161636
    Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as the thermal expansion coefficient of the circuit board. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs which include first fibers that conduct electricity and second fibers that do not conduct electricity, which have the second fibers disposed at positions where plated through holes will pass through, and which are impregnated with resin; a step of forming through holes at positions in the core portion where the second fibers are disposed; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the first fibers and thereby produce a core substrate.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: April 24, 2012
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Kishio Yokouchi, Hideaki Yoshimura, Katsuya Fukase
  • Patent number: 8161635
    Abstract: Novel methods are provided that results in the formation of single-cap VIPs in a substrate are described herein. As a result, fine pitch trace patterns may be formed on the substrate. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Chien Te Chen
  • Patent number: 8156645
    Abstract: Printed circuit boards have circuit layers with one or more via filled holes with copper wraps and methods of manufacturing the same. An embodiment of the present invention provides a method to enhance the consistency of the wraparound plating of through-hole vias of printed circuit boards with (requiring) via filling to provide extra reliability to the printed circuit boards and enables the designers and/or manufacturers of printed circuit boards to design and manufacture boards with relatively fine features and/or tight geometries.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 17, 2012
    Assignee: DDi Global Corp.
    Inventor: Rajwant Singh Sidhu
  • Patent number: 8156647
    Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: April 17, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshinori Takenaka, Takeshi Nakamura
  • Patent number: 8156640
    Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.
    Type: Grant
    Filed: October 4, 2008
    Date of Patent: April 17, 2012
    Assignee: Sanmina-SCI Corporation
    Inventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
  • Patent number: 8156646
    Abstract: A composite layer composed of an Ni layer and a Pd layer is formed on a solder pad, and a solder on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by thermal stress.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: April 17, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Tsutomu Iwai, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Patent number: 8151446
    Abstract: An apparatus for manufacturing a printed circuit board that uses conductive bumps to interconnect layers includes: a conveyor unit, which is configured to transport a board that has the conductive bumps formed on one side; an upper roller and a lower roller, which press the board and an insulator together; an elastic coating layer, formed on a surface of the upper roller; and a cleaning device, which removes impurities from a surface of the elastic coating layer. The apparatus does not require a separate device for performing a cushioning function and a detaching function between the bumps and the rollers, and the rollers can be kept clean using a cleaning device.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: April 10, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee-Soo Mok, Je-Gwang Yoo, Yoong Oh, Jong-Seok Bae, Chang-Sup Ryu
  • Patent number: 8146243
    Abstract: A method of manufacturing a device-incorporated substrate as well as a printed circuit board. A transfer sheet is formed having a structure that includes two layers, a metal base material and a dissolvee metal layer and a conductor pattern is formed on the dissolvee metal layer by electroplating. After the transfer sheet on which the conductor pattern is formed is adhered onto an insulating base material, the transfer sheet is removed by separating the metal base material from the dissolvee metal layer and thereafter selectively dissolving and removing the dissolvee metal layer with respect to the conductor pattern.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: April 3, 2012
    Assignee: Sony Corporation
    Inventors: Hiroshi Asami, Ken Orui, Hidetoshi Kusano, Fumito Hiwatashi
  • Publication number: 20120075821
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventor: Reza Argenty Pagaila
  • Patent number: 8141216
    Abstract: An ultrasound probe comprising a transmitting piezoelectric layer, an electrode layer and a receiving piezoelectric layer laminated in that order, the ultrasound probe transmitting and receiving an ultrasound, wherein a polarization treatment on the receiving piezoelectric layer is carried out by providing a peelable dielectric layer on the receiving piezoelectric layer.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 27, 2012
    Assignee: Konica Minolta Medical & Graphic, Inc.
    Inventors: Takeshi Habu, Takayuki Sasaki
  • Patent number: 8141250
    Abstract: A droplet discharging head comprises a pressure chamber in which fluid is filled through a channel, and a nozzle that is connected to the pressure chamber and which discharges the fluid as a droplet. After the droplet discharging head is assembled, at least the wall surfaces contacting the fluid are coated with a carbonized silicon film.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: March 27, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Kumiko Tanaka, Michiaki Murata
  • Patent number: 8141247
    Abstract: A method of manufacture of an integrated circuit package-on-package system includes providing a base package and providing solder caps on the top of the base package configured to protrude above subsequent resin bleed, the resin bleed extending to an edge of the base package, and configured for merging with solder balls of a top package to form larger solder balls between such a top package and the base package.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8141244
    Abstract: An insulating material, a printed circuit board that utilizes the insulating material, and a method of manufacturing the printed circuit board. The method includes perforating at least one through-hole corresponding with the at least one, which is in correspondence with the via, in a first insulator; applying a surface treatment on the first insulator by irradiating an ion beam; forming a first seed layer over an inner wall of the through-hole and over one or either side of the first insulator; forming a first plating resist over one or either side of the first insulator on which the first seed layer is formed; performing electroplating in correspondence with the circuit pattern and the via; removing the first plating resist; and removing a portion of the first seed layer by flash etching. This method can improve adhesion between the insulator and the circuit patterns to allow fine-line circuit patterns.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 27, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jong-Seok Song
  • Patent number: 8136240
    Abstract: A mechanism is disclosed for providing horizontally split vias in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first/second ones and third/fourth ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first/second conductive vias are plated onto the first through-hole and before third/fourth conductive vias are plated onto the second through-hole. The depth of these PTH plugs is controlled (e.g.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Kevin Albert Splittstoesser, Timothy Jerome Tofil, Paul Alan Vermilyea
  • Patent number: 8136213
    Abstract: The method comprises fabricating a layer stack on a substrate, the layer stack comprising at least two electrically conducting layers and at least one electrically insulating layer arranged between the two electrically conducting layers, and displacing a first portion of the layer stack away from its original position, the first portion comprising an edge portion of the layer stack, and bending the first portion back towards a second portion of the layer stack. The bending may comprise a rolling-up of the first portion of the layer stack.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: March 20, 2012
    Assignee: Max-Planck-Gesellschaft zur Forderung der Wissenschaften e.V.
    Inventor: Oliver G. Schmidt
  • Patent number: 8136220
    Abstract: A process for the manufacture of small sensors with reproducible surfaces, including electrochemical sensors. One process includes forming channels in the surface of a substrate and disposing a conductive material in the channels to form an electrode. The conductive material can also be formed on the substrate by other impact and non-impact methods. In a preferred embodiment, the method includes cutting the substrate to form a sensor having a connector portion and a transcutaneous portion, the two portions having edges that define one continuous straight line.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 20, 2012
    Assignee: Abbott Diabetes Care Inc.
    Inventors: James Say, Michael F. Tomasco, Adam Heller, Yoram Gal, Behrad Aria, Ephraim Heller, Phillip John Plante, Mark S. Vreeke
  • Publication number: 20120063094
    Abstract: Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Applicant: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Dong G. Kam, Duixian Liu, Scott K. Reynolds
  • Patent number: 8127433
    Abstract: In a manufacturing method of a glass substrate for a magnetic disk including a cleaning process of the glass substrate, the cleaning process includes a process of contacting the glass substrate with a cleaning solution containing a compound, such as thioglycolic acid or a thioglycolic acid derivative, having a thiol group as a functional group.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 6, 2012
    Assignee: Hoya Corporation
    Inventor: Yoshinori Marumo
  • Patent number: 8127441
    Abstract: A method of manufacturing a ceramic/metal composite structure includes the steps of: providing a ceramic substrate; forming a metal interface layer on the ceramic substrate; placing a copper sheet on the metal interface layer; heating the ceramic substrate, the metal interface layer and the copper sheet so that the metal interface layer forms strong bonds with the ceramic substrate and the copper sheet. Multiple stages of pre-oxidizing processes are performed on the copper sheet at different temperatures and in different atmospheres with different oxygen partial pressures before the copper sheet is placed on the metal interface layer. The metal interface layer provides a wetting effect for the copper sheet to the ceramic substrate at a high temperature so that the copper sheet wets a surface of the aluminum oxide.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: March 6, 2012
    Assignee: National Taiwan University
    Inventors: Wei-Hsing Tuan, Tsong-Jen Yang
  • Patent number: 8127437
    Abstract: Electroactive polymer transducers for sensory feedback applications are disclosed.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: March 6, 2012
    Assignee: Bayer MaterialScience AG
    Inventors: Michael G. Lipton, Ilya Polyakov, Alireza Zarrabi, Otto Hui, Silmon James Biggs, Thomas A. Kridl, Gordon Russell, Jonathan R. Heim, Roger Hitchcock, Chris A. Weaber
  • Patent number: 8127438
    Abstract: A method of manufacturing a wiring substrate includes the steps of bonding a first substrate, which includes a pixel area and a drive area located around the pixel area, and is provided with a protruding section formed in the pixel area, to a second substrate on which a peripheral circuit is disposed, so that the peripheral circuit faces the drive area, and separating the second substrate from the first substrate while leaving the peripheral circuit on the first substrate. In the step of bonding the first and the second substrates, the peripheral circuit is pressure-bonded to the first substrate, and the protruding section is made abut on the second substrate in the pixel area.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: March 6, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Toshiki Hara
  • Patent number: 8127445
    Abstract: Disclosed is a method for integrating at least two heat transfer members to provide an integrated composite member, the method comprising: a) disposing the at least two heat transfer members in a mold cavity, such that said heat transfer members each have at least one exposed surface forming a surface of a resin injection cavity; and b) injecting a thermally conductive resin into the resin injection cavity to contact the exposed surfaces of the at least two heat transfer members, to form the integrated composite member; wherein the thermally conductive resin has a thermal conductivity of at least 0.7 W/mK or higher.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: March 6, 2012
    Assignee: E. I. Du Pont de Nemours and Company
    Inventors: Yuji Saga, Narumi Une, Yoshinobu Uchida
  • Patent number: 8127424
    Abstract: An electrode assembly includes an electrode electrically connected to a capacitor with a wire. An assembly carrier may be used to hold and secure at least the wire and capacitor during assembly. A method of assembly for attaching a wire to a capacitor and an electrode may include an assembly carrier for housing and securing the wire, capacitor, and electrode during assembly.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: March 6, 2012
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Matthew I. Haller, Tom Xiaohai He, Jay Daulton
  • Patent number: 8129628
    Abstract: The multilayer wiring board is provided with a lower layer wiring (8), and an upper layer wiring (10) formed on the lower layer wiring (8) through an interlayer insulating layer (9). On the interlayer insulating layer (9), a contact hole (11) is provided for interconnecting the upper layer wiring (8) with the lower layer wiring (10). A region surrounded by an inner wall (13) which forms the contact hole (11) is permitted to have a linewidth region wherein a wide line region (13A) and protruding regions (13B, 13C) as regions having different linewidths are connected. Thus, film thickness distribution of an ink baked product (12) formed at the contact hole (11) rises at the protruding regions (13B, 13C), and highly reliable multilayer interconnection can be performed between the lower layer wiring (8) and the upper layer wiring (10).
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: March 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tokuo Yoshida, Akiyoshi Fujii, Tatsuya Fujita
  • Patent number: 8122596
    Abstract: An image is captured or otherwise converted into a signal in an artificial vision system. The signal is transmitted to the retina utilizing an implant. The implant consists of a polymer substrate made of a compliant material such as poly(dimethylsiloxane) or PDMS. The polymer substrate is conformable to the shape of the retina. Electrodes and conductive leads are embedded in the polymer substrate. The conductive leads and the electrodes transmit the signal representing the image to the cells in the retina. The signal representing the image stimulates cells in the retina.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 28, 2012
    Assignees: Lawrence Livermore National Security, LLC, Doheny Eye Institute
    Inventors: Peter Krulevitch, Dennis L. Polla, Mariam N. Maghribi, Julie Hamilton, Mark S. Humayun, James D. Weiland
  • Patent number: 8117743
    Abstract: A method includes providing a voltage switchable dielectric material having a characteristic voltage, exposing the voltage switchable dielectric material to a source of ions associated with an electrically conductive material, and creating a voltage difference between the source and the voltage switchable dielectric material that is greater than the characteristic voltage. Electrical current is allowed to flow from the voltage switchable dielectric material, and the electrically conductive material is deposited on the voltage switchable dielectric material. A body comprises a voltage switchable dielectric material and a conductive material deposited on the voltage switchable dielectric material using an electrochemical process. In some cases, the conductive material is deposited using electroplating.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: February 21, 2012
    Assignee: Shocking Technologies, Inc.
    Inventor: Lex Kosowsky
  • Patent number: 8112882
    Abstract: A method for producing a structure includes bonding two substrates facing one another by crushing a closed peripheral sealing strip located between the two substrates, the closed peripheral sealing strip delineating a closed cavity between the substrates. A microsystem is disposed on one of the substrates within the closed cavity. Before crushing, the sealing strip includes perforated patterns delineating a plurality of voids inside the strip.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 14, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Xavier Baillin, Jean Brun, Thierry Enot, David Henry
  • Patent number: 8112881
    Abstract: A process for manufacturing a multilayer wiring board including the steps of forming an insulating layer on a base provided with a bump for interlayer connection, bonding a copper foil onto the insulating layer by a thermocompression bonding by sandwiching the copper foil between stainless steel plates, and patterning the copper foil, in which a metal foil is interposed at least between each of the stainless plates and the copper foil at the time of the thermocompression bonding. At this time, a mold release layer is formed on a surface of the metal foil to be imposed. Thus, such a multilayer wiring board can be manufactured that prevents sticking of a product after molding (cementing of the copper foil) and excels in dimensional stability without occurrence of wrinkling and ruggedness.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: February 14, 2012
    Assignees: Tessera Interconnect Materials, Inc., Sony Chemical & Information Device Corporation
    Inventors: Kazuhiro Shimizu, Masanobu Yagi, Kenichiro Hanamura, Mitsuyuki Takayasu, Kiyoe Nagai, Tomoo Iijima
  • Patent number: 8110500
    Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bhyrav M. Mutnury, Moises Cases, Tae Hong Kim, Nanju Na
  • Patent number: 8108993
    Abstract: A method of manufacturing a wiring substrate is disclosed. The method includes: (a) preparing a supporting substrate including a main body and a through electrode penetrating the main body, wherein the supporting substrate includes a first surface and a second surface opposite to the first surface, and a trace is formed on the second surface of the supporting substrate; (b) forming a build-up wiring structure by alternately forming a wiring layer and an insulating layer on the first surface of the supporting substrate; and (c) obtaining a wiring substrate by separating the build-up wiring structure from the supporting substrate. Step (b) includes: forming the wiring layer using the through electrode as a power feeding wiring, and step (c) includes: peeling the build-up wiring structure from the supporting substrate to obtain the wiring substrate.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: February 7, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Kei Murayama, Masahiro Sunohara, Hideaki Sakaguchi
  • Patent number: 8108992
    Abstract: A method of making a self-supporting field director structure for use in heating an article in a microwave oven comprises in any operative order, the steps of folding a first and a second elongated vane blank along a central fold line to form at least two V-shaped vane doublets; inserting each of the vane doublets into a slotted annular support member so that each vane in each vane doublet extends through an adjacent slot in the annular support member; and attaching the vane doublets at their vertices to define a vane array.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: February 7, 2012
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: William R. Corcoran, Jr.
  • Patent number: 8108990
    Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: February 7, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Hironori Tanaka
  • Patent number: 8104171
    Abstract: The present invention directs to fabrication methods of single-sided or double-sided multi-layered substrate by providing a lamination structure having at least a core structure and first and second laminate structures stacked over both surfaces of the core structure. The core structure functions as the temporary carrier for carrying the first and second laminate structures through the double-sided processing procedures. By way of the fabrication methods, the production yield can be greatly improved without increasing the production costs.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: January 31, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl Appelt, Yuan-Chang Su, Ming-Chiang Lee, You-Lung Yen
  • Patent number: 8104172
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Publication number: 20120018207
    Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed. In addition, a fabricating process of a circuit substrate is also provided.
    Type: Application
    Filed: September 10, 2010
    Publication date: January 26, 2012
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Chen-Yueh Kung
  • Patent number: 8099852
    Abstract: A method for assembling an image capturing device is provided. The image capturing device includes a light-pervious module, an image sensor and a binding material. The image sensor has a light sensing region for converting an imaging light into an electronic signal. The binding material is used for binding articles together and curable by a curing process. Firstly, the light-pervious module and the image sensor together are releasably bound together via the binding material, thereby defining a close space for accommodating the image sensor. Then, a testing process is performed to detect a clean condition of the close space. If particles present in the close space are detected, the light-pervious module is detached from the image sensor, a cleaning process is done to remove the particle, and the light-pervious module and the image sensor are releasably bound together to define the close space again. Afterwards, the binding material is cured.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: January 24, 2012
    Assignee: Primax Electronics Ltd.
    Inventor: Jui-Hsiang Lo
  • Patent number: 8099866
    Abstract: In a roll-to-roll step, an adhesive solution is applied to a release film 1 including a polyethylene terephthalate film and this film 1 is passed through a drying oven 500 regulated to 60 to 150° C. to thereby form an adhesive layer 2. Subsequently, an insulating film 3 including a polyimide film is laminated on the adhesive layer 2 at room temperature (about 25° C.) to thereby produce a layered product 6 including the release film 1, adhesive layer 2 and insulating film 3. Next, the release film 1 is stripped from the layered product 6 and a conductor film 4 including a copper foil is laminated to the adhesive layer 2 to thereby produce a conductor-clad laminate 8.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: January 24, 2012
    Assignee: Nitto Denko Corporation
    Inventor: Daisuke Yamauchi
  • Patent number: 8091218
    Abstract: Provided is a bending rigid printed wiring board which facilitate the mounting of electric parts (realization of a high producibility and high assemblability substrate circuit) and enables spaces to be saved and which can be easily manufactured. That is, provided is a bending rigid printed wiring board, which is characterized in that a heat resistant resin layer is laminated on a front surface of a hard core material provided so as to contain a gap portion and also on a top surface of the gap portion, in that a heat resistant resin layer is laminated on a rear surface of the core material except the gap portion, in that a conductor layer is laminated and firmly fixed via the heat resistant resin layers and in that the conductor layer is etched, whereby a circuit is formed.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: January 10, 2012
    Assignees: Fujikura Ltd., Kyoei Electric Co., Ltd.
    Inventors: Atsushi Momota, Ichiro Terunuma, Takeshi Hasegawa, Yasuo Takemura, Yoshifumi Hatakeyama, Hiroshi Harada, Makoto Katoh
  • Patent number: 8091220
    Abstract: A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 10, 2012
    Assignee: Abbott Diabetes Care Inc.
    Inventors: Benjamin J. Feldman, Adam Heller, Ephraim Heller, Fei Mao, Joseph A. Vivolo, Jeffery V. Funderburk, Fredric C. Colman, Rajesh Krishnan
  • Patent number: 8091225
    Abstract: The manufacturing method of a probe with printed tip consists of a substrate having a plurality of probe tips connected to its end edge, a plurality of test paths, each connected to one of the probe tips and extending along the substrate, and at least one of the test paths including an electrical component adjacent to the test path's probe tip. The electrical component may be a resistor. The probe tips may have a width equal to the thickness of the substrate. The probe tips may consist of a plurality of probe tip layers. The invention also includes a method of probing signals transmitted over target transmission lines on a target board. The disclosure also includes a method of manufacturing the claimed invention.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: January 10, 2012
    Assignee: Tektronix, Inc.
    Inventors: Leonard A. Roland, Kathleen F. Ullom, Ira G. Pollock, James E. Spinar
  • Patent number: 8091235
    Abstract: A manufacturing method for manufacturing a liquid ejection element including a liquid flow path which is open at an ejection outlet for ejecting liquid, and an energy generating member for generating energy usable for ejecting the liquid from liquid flow path through the ejection outlet, the manufacturing method, includes a step of forming the energy generating member on a front side of a substrate; a step of forming a top plate member on the side having the energy generating member formed by the energy generating member forming step, wherein the top plate member is a member in which the liquid flow path and the ejection outlet are formed; and a step of thinning the substrate, having the top plate member formed thereon by the top plate member forming step, from a back side thereof.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: January 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirokazu Komuro