Assembling Formed Circuit To Base Patents (Class 29/831)
  • Publication number: 20130265073
    Abstract: The present invention provides a ST board 2 that is formed with an lower surface electrode 22; a unit attachment plate 3 that is fastened on the ST board 2 and formed with an opening part 31 exposing the lower surface electrode 22; a probe unit 5 that includes a probe substrate 50 formed with a contact probe 51 and a probe electrode 52 and is fastened on the unit attachment plate 3; and an electrically conductive wire 54 that connects the lower surface electrode 22 and the probe electrode 52 to each other through the opening part 31. The probe unit 5 can be fastened on the ST board 2 with the unit attachment plate 3 intervening, and through the opening part 31 of the unit attachment plate 3, the probe electrode 51 and the lower surface electrode 22 can be electrically connected to each other.
    Type: Application
    Filed: January 16, 2011
    Publication date: October 10, 2013
    Applicant: Japan Electronic Materials Corporation
    Inventors: Hirofumi Nakano, Taishi Uemura, Kazuhiro Matsuda
  • Publication number: 20130265782
    Abstract: An assembly for high-powered LEDs provides a direct attachment of the LED to a ceramic thermal conductor/electrical insulator sealed in a housing with a compression element between a portion of the housing and ceramic heat sink to provide a predetermined range of biasing force locating the ceramic heat sink against the portion of the housing with dimensional changes in the ceramic heat sink caused by thermal expansion of the ceramic heat sink.
    Type: Application
    Filed: December 14, 2011
    Publication date: October 10, 2013
    Applicant: ILLINOIS TOOL WORKS INC.
    Inventors: Juan J. Barrena, Edward J. Claprood, Eric K. Larson
  • Patent number: 8549740
    Abstract: Various folded waveguides and methods of manufacturing waveguides are disclosed herein. For example, some embodiments provide a method of manufacturing a folded waveguide including machining a plate with a number of registration marks and forming at least one slow wave circuit in at least two halves on the plate. A portion of the registration marks are for the plate and another portion are for the at least one slow wave circuit. The method also includes connecting the at least two halves of the at least one slow wave circuit and machining the at least one slow wave circuit.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: October 8, 2013
    Assignee: InnoSys, Inc
    Inventors: Ruey-Jen Hwu, Laurence P. Sadwick, Jehn-Huar Chern
  • Patent number: 8549728
    Abstract: To provide a vibration actuator, a lens barrel, a camera, a manufacturing method for a vibration body and a manufacturing method for a vibration actuator, which have a high driving efficiency and can lead to easy manufacture. A vibration actuator of the present invention is provided with an elastic body and an electromechanical transducer element sintered onto the elastic body in the state that the element is divided into a plurality of areas by a groove-shaped border portion.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: October 8, 2013
    Assignee: Nikon Corporation
    Inventor: Takahiro Sato
  • Patent number: 8549745
    Abstract: A process for fabricating process a circuit substrate having a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: October 8, 2013
    Assignee: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung
  • Patent number: 8549737
    Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 8, 2013
    Assignee: General Dynamics Advanced Information Systems, Inc.
    Inventor: Deepak K. Pai
  • Publication number: 20130258578
    Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 24, 2013
    Publication date: October 3, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Myung Jin Yim, Nanette Quevedo, Richard Strode
  • Publication number: 20130256004
    Abstract: An apparatus and method wherein the apparatus comprises includes a deformable substrate; a conductive portion; and at least one support configured to couple the conductive portion to the deformable substrate so that the conductive portion is spaced from the deformable substrate.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Darryl COTTON, Samiul Md. HAQUE, Piers ANDREW
  • Publication number: 20130256006
    Abstract: A method for forming a circuit on a flexible laminate substrate, wherein when a circuit is formed using an adhesive-free flexible laminate having a polyimide film that serves as a flexible laminate substrate at least one surface of which is plasma-treated, a tie-coat layer A formed on the polyimide film, a metal conductor layer B formed on the tie-coat layer, and a nickel-copper alloy layer as an alloy layer C on the metal conductor layer, a photoresist is applied on the alloy layer C formed on the metal conductor layer, the photoresist is exposed and developed, the sputter layer C, the metal conductor layer B, and the alloy layer C are removed by etching using the same etching solution so as to retain a circuit portion, and the photoresist of the circuit portion is further removed so as to form the circuit.
    Type: Application
    Filed: November 8, 2011
    Publication date: October 3, 2013
    Applicant: JX NIPPON MINING & METALS CORPORATION
    Inventors: Kazuhiko Sakaguchi, Hajime Inazumi
  • Publication number: 20130257420
    Abstract: A sensor includes a body having a sensor surface and an oblique surface. A sensor element is arranged on the sensor surface and configured to pick up a direction component of a directional measurement variable. At least one contact-making surface configured to make contact with the sensor element is arranged on the oblique surface. The oblique surface is at an angle with respect to a lattice structure of carrier material of the sensor and is oriented in a different direction than the sensor surface.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 3, 2013
    Applicant: Robert Bosch GmbH
    Inventors: Hubert Benzel, Christoph Schelling
  • Patent number: 8547703
    Abstract: Disclosed herein is a card-type peripheral apparatus including: a case body configured to accommodate an electronic package including a circuit board between a first surface and a second surface that are opposite to each other; a first electronic package including a memory mounted on the circuit board; a second electronic package including an electronic part for controlling the memory mounted on the circuit board; a first thermal conductive material arranged inside the case body, the first thermal conductive material in contact with a surface of at least one of the first electronic package and the second electronic package; and a second thermal conductive material formed with the first surface and the second surface of the case body, wherein the first thermal conductive material and the second thermal conductive material are in contact with each other inside the case body.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: October 1, 2013
    Assignee: Sony Corporation
    Inventors: Yoshitaka Aoki, Hitoshi Kimura
  • Patent number: 8544167
    Abstract: There is disclosed a collective mounting method of electronic components in which a plurality of electronic components can uniformly be pressed to an insulating layer in a short time in a case where the electronic components and a resin layer are fixed. To manufacture a semiconductor-embedded substrate 200 in which a plurality of semiconductor devices 220 are embedded, after disposing the plurality of semiconductor devices 220 on an unhardened resin layer 212, this is stored in a container 31 of a pressurizing and heating unit 3, the plurality of semiconductor devices 220 are simultaneously, collectively and isotropically pressurized by use of an internal gas in the container 31 as a pressure medium to simultaneously press the plurality of semiconductor devices 220 to the unhardened resin layer 212, and the resin layer 212 is heated and hardened.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 1, 2013
    Assignee: TDK Corporation
    Inventor: Takaaki Morita
  • Patent number: 8544170
    Abstract: In one embodiment, a percutaneous stimulation lead for applying electrically stimulation pulses to tissue of the patient comprises: a plurality of electrode assemblies electrically coupled to a plurality of terminals through a plurality of conductors of the stimulation lead, wherein each electrode assembly is disposed in an annular manner around the lead body and each electrode assembly comprises (i) an electrode adapted to deliver electrical stimulation to tissue of a patient, (ii) an interior conductive layer, and (iii) a dielectric layer disposed between the electrode and the interior conductive layer; the electrode and interior conductive layer being capacitively coupled, the dielectric layer further comprising an inductor, the inductor being electrically connected to one of the plurality of conductors through the interior conductive layer, and the inductor being electrically coupled to the electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 1, 2013
    Assignee: Advanced Neuromodulation Systems, Inc.
    Inventors: Timothy J. Cox, John Erickson, Enri Zhulati, Terry Daglow, John Swanson
  • Patent number: 8540903
    Abstract: Disclosed is an electrically conductive paste which enables to reduce the level of void growth in a conducting pathway formed in a joint part produced after curing the electrically conductive paste in the implementation of an electronic component on a circuit board by using the electrically conductive paste, and which contains a reduced amount of a viscosity-adjusting/thixotropy-imparting additive. Two Sn-containing low-melting-point alloy particles having different melting points and different average particle diameters are selected as electrically conductive filler components to be used in an electrically conductive paste, and the two alloy particles are mixed at a predetermined ratio for use.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: September 24, 2013
    Assignee: Panasonic Corporation
    Inventors: Takayuki Higuchi, Hidenori Miyakawa, Atsushi Yamaguchi, Arata Kishi, Naomichi Ohashi
  • Patent number: 8539655
    Abstract: A piezoelectric mirror device fabrication process, including: dividing a silicon wafer into a multiplicity of segments, wherein on one surface of said silicon wafer per segment, a pair of lower electrodes, a mirror portion positioned between said lower electrodes and a pair of mirror support portions adapted to join said mirror portion to said lower electrodes are formed of an electrically conductive material having a Young's modulus of up to 160 GPa and a melting point higher than that of a piezoelectric element to be formed later; stacking the piezoelectric element and an upper electrode on said lower electrodes; removing the silicon wafer in a desired pattern from another surface of said silicon wafer per segment, and obtaining a multiplicity of piezoelectric mirror devices by dicing said multiplicity of piezoelectric mirror devices into individual ones.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: September 24, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Shinji Maekawa
  • Patent number: 8539667
    Abstract: A method of fabricating a touch panel is provided. A substrate having a touch-sensing region and a peripheral region is provided. A touch-sensing circuit layer including first sensing series, second meshed metal sensing pads, and peripheral circuits is formed on the touch-sensing region of the substrate. An insulating layer having first contact windows and second contact windows is formed on the substrate to cover the touch-sensing circuit layer. The first contact windows expose a portion of the second meshed metal sensing pads. A transparent conductive layer including second transparent bridge lines and transparent contact pads is formed on the insulating layer located in the touch-sensing region of the substrate. Each second transparent bridge line is electrically connected to two adjacent second meshed metal sensing pads through two first contact windows. Each transparent contact pad is electrically connected to the corresponding peripheral circuit through the second contact window.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: September 24, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yu-Feng Chien, Zeng-De Chen, Tun-Chun Yang, Seok-Lyul Lee
  • Publication number: 20130242183
    Abstract: The present invention relates to a camera module, the camera module including: a PCB (Printed Circuit Board), an image sensor mounted on the PCB and formed with an imaging device for converting light to an electrical signal; a housing fixed a bottom end to an upper surface of the PCB, the housing being a case formed with a hole at an upper center and having a bottom-opened inner space: a lens assembly having at least one lens aligned to the lens hole by being positioned at and contacted to an upper surface of the image sensor and accommodated at an inner space of the housing; and an elastic stiffening material inserted between a lens hole periphery at an upper inner side of the housing and an upper edge of the lens assembly.
    Type: Application
    Filed: November 10, 2011
    Publication date: September 19, 2013
    Applicant: LG INNOTEK CO., LTD
    Inventor: Kiho Lee
  • Patent number: 8536457
    Abstract: A wiring board including a main substrate having a base material and a conductive pattern formed on the base material, and a flex-rigid printed wiring board provided to the main substrate and having a rigid substrate and a flexible substrate connected to each other. The flex-rigid printed wiring board has a conductive pattern formed on the rigid substrate and/or the flexible substrate. The conductive pattern of the main substrate is electrically connected to the conductive pattern of the flex-rigid printed wiring board.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: September 17, 2013
    Assignee: Ibiden Co., Ltd.
    Inventor: Michimasa Takahashi
  • Patent number: 8528195
    Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: September 10, 2013
    Assignee: Inventec Corporation
    Inventors: Chung-Yang Wu, Hung-Tao Wong
  • Patent number: 8528197
    Abstract: An electronic part mounting method including introducing electronic parts in a bulk form into a bulk feeder, transferring the introduced electronic parts to at least one inspection unit by use of a rotatably installed positioning wheel, inspecting and aligning the electronic parts, transferring the inspected and aligned electronic parts to a part insertion unit by use of the positioning wheel, inserting the electronic parts, determined as good ones by the inspection unit, into the part insertion unit, and picking up the electronic parts received in the part insertion unit to mount the electronic parts on a board.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 10, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Jun-Kyu Park, Sang-Mun Shin, Gweon-Young Park, Byung-Chul Lee
  • Patent number: 8522426
    Abstract: A vented BGA package is reconfigured by first applying a continuous bead of adhesive around the perimeter of the package to seal the gap between the lid and substrate. The continuous bead defines a channel through the pressure relief vents to a polarity through-hole in the lid. The BGA package is reflow soldered to a PWB at an elevated temperature using solder flux, clean or no-clean. The IC die achieves elevated temperature pressure relief through the pressure relief vents along the channel and out the polarity through-hole. After reflow a seal is applied to plug the polarity through-hole. The PWB is washed in an aqueous cleaner solution to remove flux residue. The continuous bead of adhesive and the seal form a cleaner solution barrier that prevents the solution from contacting conductors inside the package. The seal may be removed or left intact depending on the operating environment.
    Type: Grant
    Filed: June 5, 2010
    Date of Patent: September 3, 2013
    Assignee: Raytheon Company
    Inventors: Robert H. Dennis, Amanda Loehr, Robert E. Morris, Peter D. Patalano, Aaron J. Stein, John Stephens, Harold L. Wieck, Eli Holzman
  • Patent number: 8522425
    Abstract: A method for assembling an electronic device comprises inserting a thermal element into an electrical connector contained within a special volume defined by a constricted enclosure that comprises a housing of the electronic device. The spatial volume contains a printed circuit board and the electrical connector includes internal electrical contacts that are positioned proximate to solder connection pads on the printed circuit board when the electrical connector and the printed circuit board are contained within the constricted enclosure. Insertion of the thermal element heats the internal electrical contacts so that solder on the solder connection pads reflows to form solder connections respectively between the internal electrical contacts and the solder connection pads. Thereafter, the thermal element is removed from the electrical contact.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: September 3, 2013
    Assignee: Apple Inc.
    Inventor: Stephen Brian Lynch
  • Patent number: 8522427
    Abstract: A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film layer exposed by electroplating. Then, the plating resist layer is removed, and the thin metal film layer in the region having the plating resist layer is removed. In this way, a conductive pattern including the thin metal film layer and the metal plating layer is formed. The upper surface of the base insulating layer in the region without the conductive pattern is subjected to roughening treatment. A cover insulating layer is formed on the upper surfaces of the base insulating layer and the conductive pattern. In this way, a printed circuit board is completed.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: September 3, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Tadao Ookawa, Mitsuru Honjo, Takashi Oda
  • Publication number: 20130223031
    Abstract: A sensor comprises a preferably multi-layer ceramic substrate (2) and at least one sensor element (1) arranged in, at, or on the ceramic substrate (2). The sensor element (1) can be contacted via a metallic contact (6), with the metallic contact (6) being produced via a soldering connection, which electrically connects the contact (6) with the sensor element (1) and here generates a fixed mechanic connection of the contact (6) in reference to the ceramic substrate (2). Furthermore, a method is claimed for producing the sensor according to the invention.
    Type: Application
    Filed: October 10, 2011
    Publication date: August 29, 2013
    Applicant: MICRO-EPSILON MESSTECHNIK GMBH & CO. KG
    Inventors: Sabine Schmideder, Torsten Thelemann, Josef Nagl, Heinrich Aschenbrenner, Reinhold Hoenicka
  • Patent number: 8510941
    Abstract: Printed circuit boards have circuit layers with one or more via filled holes with copper wraps and methods of manufacturing the same. An embodiment of the present invention provides a method to enhance the consistency of the wraparound plating of through-hole vias of printed circuit boards with (requiring) via filling to provide extra reliability to the printed circuit boards and enables the designers and/or manufacturers of printed circuit boards to design and manufacture boards with relatively fine features and/or tight geometries.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: August 20, 2013
    Assignee: DDI Global Corp.
    Inventor: Rajwant Singh Sidhu
  • Patent number: 8510936
    Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 20, 2013
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chih-Hong Chuang, Tzu-Wei Huang
  • Publication number: 20130202247
    Abstract: An optical interface module includes a single flexible Printed Circuit Board (PCB) including conductive traces. An electrical connector, one or more opto-electronic transducers and ancillary circuitry are disposed on the flexible PCB. The electrical connector is configured to mate with a corresponding connector on a substrate. The opto-electronic transducers are configured to be coupled to optical fibers carrying optical signals. The ancillary circuitry is coupled by the traces to the opto-electronic transducers and the electrical connector so as to convey electrical signals corresponding to the optical signals between the opto-electronic transducers and the electrical connector.
    Type: Application
    Filed: February 5, 2012
    Publication date: August 8, 2013
    Applicant: MELLANOX TECHNOLOGIES LTD.
    Inventors: Shmuel Levy, Shai Rephaeli, Yonatan Malkiman
  • Patent number: 8499440
    Abstract: A method of making a circuitized substrate including a composite layer having a first dielectric sub-layer including a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papthomas
  • Publication number: 20130196722
    Abstract: A mobile wireless communications device includes a portable housing having a metallic front housing forming a peripheral sidewall as a metallic ring. A circuit board is carried by the portable housing and forms a chassis ground plane. A wireless communications circuit is carried by a circuit board. An antenna circuit is carried by a circuit board and connected to the wireless communications circuit. A frequency selective grounding circuit is positioned at a selected grounding location at the chassis ground plane and metallic front housing and forms a harmonic trap that responds to a specific range of frequencies.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 1, 2013
    Applicant: RESEARCH IN MOTION LIMITED
    Inventor: RESEARCH IN MOTION LIMITED
  • Patent number: 8493747
    Abstract: A flex-rigid wiring board including an insulative substrate, a flexible wiring board positioned beside the insulative substrate, an insulation layer positioned over the insulative substrate and the flexible wiring board and exposing a portion of the flexible wiring board, and a wiring layer made of a conductor and formed on the insulation layer. The insulation layer has a tapered portion which becomes thinner toward an end surface of the insulation layer in the direction of the portion of the flexible wiring board exposed by the insulation layer. The wiring layer has a sloping portion formed on the tapered portion of the insulation layer.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 23, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Nobuyuki Naganuma, Michimasa Takahashi, Masakazu Aoyama
  • Publication number: 20130183862
    Abstract: A dual-personality extended USB (EUSB) system supports both USB and EUSB devices using an extended 9-pin EUSB socket. Each EUSB device includes a PCBA having four standard USB metal contact pads, and several extended purpose contact springs disposed on an upper side of a PCB. A single-shot molding process is used to form a molded housing over passive components and IC dies disposed on the lower PCB surface. The passive components are mounted using SMT methods, and the IC dies are mounted using COB methods. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs. The EUSB device is optionally used as a modular insert that is mounted onto a metal or plastic case to provide a EUSB assembly having a plug shell similar to a standard USB male connector.
    Type: Application
    Filed: March 5, 2013
    Publication date: July 18, 2013
    Applicant: Super Talent Technology, Corp.
    Inventor: Super Talent Technology, Corp.
  • Patent number: 8484836
    Abstract: An integrated circuit connector is extendable for a variety of applications. In connection with various embodiments, an electrical connector has first and second ends connected to respective circuit nodes in an integrated circuit device. The connector is bundled between the circuit nodes (e.g., substantially all of the connector is located between nodes), and is extended from such a bundled state in which the first and second connected ends are separated by a first proximate distance. The connector is applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance by at least two orders of magnitude.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 16, 2013
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Giulia Lanzara, Fu-Kuo Chang
  • Patent number: 8484840
    Abstract: When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Limited
    Inventors: Toshiyasu Sakata, Eiichi Konno
  • Patent number: 8479386
    Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 8479384
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
  • Patent number: 8479389
    Abstract: A method of manufacturing a flex-rigid wiring board including disposing a flexible board comprising a flexible substrate and a conductor pattern formed over the flexible substrate and a non-flexible substrate adjacent to each other, covering a boundary between the flexible board and the non-flexible substrate with an insulating layer comprising an inorganic material, providing a conductor pattern on the insulating layer, forming a via hole opening which passes through the insulating layer and reaches the conductor pattern of the flexible board, and plating the via hole opening to form a via connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 9, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Michimasa Takahashi, Masakazu Aoyama
  • Patent number: 8479376
    Abstract: A method produces a magnetostrictive torque sensor which detects a steering torque applied to a steering shaft by electrically detecting distortion of magnetostrictive films provided on a surface of the steering shaft. A plating step forms the magnetostrictive film on the surface of the steering shaft, and a heat treatment step heat treats the magnetostrictive film on the steering shaft. During the heat treatment step, hydrogen in the magnetostrictive film is decreased so that a hydrogen desorbing peak around 120° C. disappears when the magnetostrictive film is heated after the heat treatment step.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: July 9, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventors: Yasuo Shimizu, Nagatsugu Mukaibou
  • Patent number: 8481858
    Abstract: The invention relates to a method for producing a non-developable surface printed circuit and to the thus obtained printed circuit. According to the invention, each electrically conductive pattern of a printed circuit includes at least one base, which is arranged on the non-developable surface and obtained by projecting an electrically conductive varnish, and a coating, which is arranged on the base and made of an electrically well conductive material by buffer electrolysis.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: July 9, 2013
    Assignee: Astrium SAS
    Inventor: Christian Desagulier
  • Patent number: 8481863
    Abstract: A substrate includes a storage portion which is defined by a base for mounting a light emitting element and a wall portion standing up on and from the base. A package is structured such that the upper end of the wall portion so formed as to surround the periphery of the storage portion is connected to a cover to thereby seal a light emitting element. A seal structure is composed of an uneven portion formed on the lower surface side surface of the base, a close contact layer formed on the surface of the uneven portion, a power supply layer formed on the close contact layer, and an electrode layer formed on the surface of the power supply layer. The uneven portion includes a first recessed portion formed at a position spaced in the radial direction from the outer periphery of a through electrode or from the inner wall of a through hole, and a second recessed portion formed at a position spaced further outwardly from the first recessed portion.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: July 9, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akinori Shiraishi, Kei Murayama, Masahiro Sunohara, Naoyuki Koizumi, Mitsutoshi Higashi
  • Patent number: 8469607
    Abstract: Methods and apparatus are provided related to opto-electronics. An opto-electronic subassembly includes electrical contacts bonded to a base by way of a compliant adhesive. The opto-electronic subassembly is mechanically engaged to a circuit board resulting in contact force loading of the compliant adhesive. Such loading maintains electrical coupling between the electrical contacts and respective circuit pathways of the circuit board. Optical signal communication between the opto-electronic subassembly and another entity is performed by way of an optical connector.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 25, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul Rosenberg, Michael Renne Ty Tan, Sagi Mathai, Wayne Sorin
  • Patent number: 8458899
    Abstract: A circuit assembly (34) resistant to high-temperature and high g centrifugal force is disclosed. A printed circuit board (42) is first fabricated from alumina and has conductive traces of said circuit formed thereon by the use of a thick film gold paste. Active and passive components of the circuit assembly are attached to the printed circuit board by means of gold powder diffused under high temperature. Gold wire is used for bonding between the circuit traces and the active components in order to complete the circuit assembly (34). Also, a method for manufacturing a circuit assembly resistant to elevated temperature is disclosed.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: June 11, 2013
    Assignee: Siemens Energy, Inc.
    Inventors: David J. Mitchell, Anand A. Kulkarni, Ramesh Subramanian, Edward R. Roesch, Rod Waits, Roberto Schupbach, John R. Fraley, Alexander B. Lostetter, Brice McPherson, Bryon Western
  • Patent number: 8453323
    Abstract: A method for manufacturing a printed circuit board, including providing a core substrate having an electronic component accommodated in the core substrate; forming a positioning mark on the core substrate; forming an interlayer insulating layer over the core substrate, the positioning mark and the electronic component; forming a via hole opening connecting to the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate; and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the electronic component.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: June 4, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Patent number: 8453322
    Abstract: Methods of manufacturing at least a portion of a printed circuit board. The circuit board is formed to include a plurality of sub-assemblies, each of the sub-assemblies including a plurality of circuit layers and having at least one countersink and at least one hole, the countersink having a first diameter and a first depth from a first side of at least one of the sub-assemblies and into the at least one sub-assembly, the hole having a second diameter smaller than the first diameter and a second depth longer than the first depth from the first side of the at least one sub-assembly and into the at least one sub-assembly at the countersink; a metal metalized within the hole and the countersink; a lamination adhesive interposed between one and a corresponding one of the sub-assemblies and having at least one via formed therethrough; and a counter paste filled within the via.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: June 4, 2013
    Assignee: DDI Global Corp.
    Inventors: Raj Kumar, Monte Dreyer, Michael J. Taylor, Ruben Zepeda
  • Patent number: 8447566
    Abstract: A mounting condition determining method including: obtaining mounting information including information related to component mounting operations scheduled to be performed by a mounter (S1); judging, using the mounting information obtained in the obtaining: which production mode between a synchronous mode and an asynchronous mode is suitable for the scheduled component mounting operations; or which production mode between an alternating mode and an independent mode is suitable for the scheduled component mounting operations (S2, S3); and selecting the production mode indicated by a result of the judgment in the judging, as the production mode to be executed by the mounter (S5, S6).
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventor: Yasuhiro Maenishi
  • Patent number: 8434220
    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: May 7, 2013
    Assignee: RF Micro Devices, Inc.
    Inventors: Jayanti Jaganatha Rao, Thomas Scott Morris, Milind Shah
  • Patent number: 8436254
    Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 7, 2013
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Po Yu, Han-Pei Huang
  • Patent number: 8425716
    Abstract: A method of providing chiplets over a substrate including providing in sequence a substrate; coating an adhesive in a layer over the substrate; placing a plurality of first chiplets onto the adhesive layer in separated chiplet location(s) to adhere the first chiplets to the adhesive layer, wherein one or more of the first chiplets do not adhere to the adhesive layer, so that first chiplet(s) are adhered to the adhesive layer in adhered chiplet location(s) and first chiplet(s) are not adhered in non-adhered chiplet location(s); locally processing the adhesive layer in the non-adhered chiplet location(s) to condition the adhesive layer in the non-adhered locations to receive second chiplets; placing second chiplet(s) onto the adhesive layer in the conditioned non-adhered chiplet location(s) to adhere the second chiplets in the adhesive layer in the non-adhered locations; and curing the adhesive.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: April 23, 2013
    Assignee: Global OLED Technology LLC
    Inventors: Ronald S. Cok, John W. Hamer
  • Patent number: 8424195
    Abstract: An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a die attach portion attaching a semiconductor chip on the lead frame supplied to the index rail.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: April 23, 2013
    Assignee: STS Semiconductor & Telecommunications Co., Ltd.
    Inventor: Sun Ha Hwang
  • Patent number: 8418361
    Abstract: Method of manufacturing printed circuit board, including: providing a substrate including a first circuit layer having a lower land of a via; forming an insulating layer on the first circuit layer; forming a via hole in the insulating layer; filling the via hole with a first metal, thus forming a via; forming a seed layer with a second metal on the insulating layer and an exposed surface of the via; applying a resist film on the seed layer, and forming a resist pattern having an opening for a second circuit layer with a width formed on the via being smaller than a width of the via; plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and removing the resist film, and selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 16, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Won Lee, Chang Gun Oh, Mi Sun Hwang
  • Patent number: RE44423
    Abstract: In a method for manufacturing a quartz crystal unit, a quartz crystal tuning fork resonator is formed by etching a quartz crystal wafer to form a quartz crystal tuning fork base, quartz crystal tuning fork tines connected to the quartz crystal tuning fork base, and a groove having stepped portions in at least one of opposite main surfaces of each of the quartz crystal tuning fork tines. A first electrode is disposed on at least one of the stepped portions of each of the grooves and a second electrode is disposed on each of side surfaces of each of the quartz crystal tuning fork tines. A frequency of oscillation of the quartz crystal tuning fork resonator is adjusted at least twice and in different steps. The quartz crystal tuning fork resonator is then mounted in a case and an open end of the case is covered with a lid.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: August 13, 2013
    Assignee: Piedek Technical Laboratory
    Inventor: Hirofumi Kawashima