Assembling Formed Circuit To Base Patents (Class 29/831)
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Patent number: 8266792Abstract: A printed circuit board with an electronic component embedded printed circuit board and a manufacturing method thereof are disclosed. According to an embodiment of the present invention, the method of manufacturing a printed circuit board with an embedded electronic component having a groove formed on one surface thereof and an electrode formed inside the groove includes: forming a first circuit pattern on one surface of a first metal layer; pressing the first metal layer against a first insulator; forming a first conductive protrusion by selectively etching the other surface of the first metal layer; and mounting a first electronic component by disposing a conductive adhesive layer such that an electrode of the first electronic component and the first conductive protrusion are electrically connected to each other. Thus, an electronic component without its electrode protruded outward can be mounted easily and reliably and the manufacturing time can be shortened.Type: GrantFiled: January 31, 2012Date of Patent: September 18, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woon-Chun Kim, Soon-Gyu Yim
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Patent number: 8266793Abstract: A module having a stacked magnetic device and semiconductor device, and method of forming the same. In one embodiment, the module includes a printed wiring board including a patterned conductor formed on an upper surface thereof. The module also includes a magnetic core mounted on the upper surface of the printed wiring board proximate the patterned conductor and a semiconductor device mounted on an upper surface of the magnetic core.Type: GrantFiled: February 26, 2009Date of Patent: September 18, 2012Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Douglas Dean Lopata, John David Weld, Mathew A. Wilkowski
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Patent number: 8266796Abstract: Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.Type: GrantFiled: May 21, 2008Date of Patent: September 18, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Yong Park, Kyoung-Sei Choi
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Patent number: 8266797Abstract: Disclosed are a multi-layer substrate and a manufacturing method of the multi-layer substrate. By employing a carrier to alternately form dielectric layers and metal structure layers thereon. Each dielectric layer adheres with the adjacent dielectric layer to embed the metal structure layers in the dielectric layers corresponding thereto. Comparing with prior arts, which have to use prepregs when hot pressing and adhering different layers of different materials, the present invention takes fewer processes, thus, fewer kinds of materials without using prepregs. Therefore, the present invention can promote the entire quality and yield of manufacturing the multi-layer substrate to satisfy mechanical characteristic matching of the multi-layer substrate and to reduce cost of the whole manufacturing process.Type: GrantFiled: April 22, 2011Date of Patent: September 18, 2012Assignee: Princo Middle East FZEInventors: Chih-Kuang Yang, Cheng-Yi Chang
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Publication number: 20120228017Abstract: A wiring board for an electronic parts inspecting device that can be designed and produced relatively quickly, inexpensively, and with a few number of jigs is provided. In certain embodiments the wiring board comprises a board main body having a front surface, a probe pad area having probe pads located in a central portion of the front surface, an outer connecting terminal area having outer connecting terminals located in a peripheral portion of the front surface, and wherein probe pads are connected to outer connecting terminals by front surface wirings formed between the probe pad area and the outer connecting terminal area. While certain embodiments further comprise inner wirings and first via conductors to connect the probe pads and outer connecting terminals, it is preferable to have no or a minimal amount of such inner wirings. Lastly, a method of manufacturing the same is provided.Type: ApplicationFiled: March 7, 2012Publication date: September 13, 2012Applicant: NGK SPARK PLUG CO., LTD.Inventors: Tomoyoshi ONO, Kazushige AKITA, Toshihisa NOMURA
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Patent number: 8261430Abstract: A method for manufacturing anti-EMI shields on computer chassis, the method includes the following steps. The anti-EMI plate is glued to the computer chassis. The anti-EMI plate is pressed onto the plate by a pressing machine, and then the plate is quick dried with the anti-EMI plate by a drying machine. The plate is cut into desired dimension with the anti-EMI plate by a cutting machine, and the plate is stamped into desired shape with the anti-EMI plate by a stamping machine.Type: GrantFiled: June 2, 2009Date of Patent: September 11, 2012Assignees: Hong Fu Jin Precision Industry (ShenZhen)Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Chin-Wen Yeh, Zhi-Jian Peng
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Patent number: 8261436Abstract: A circuit substrate fabricating process includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block. In addition, a fabricating process for the circuit substrate is also provided.Type: GrantFiled: December 23, 2009Date of Patent: September 11, 2012Assignee: VIA Technologies, Inc.Inventor: Chen-Yueh Kung
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Patent number: 8263870Abstract: It is an object to improve a conventional point that mounting an electronic component that requires a high current and heat radiation, such as an LED, together with other general electronic components on the same board has been difficult. To achieve this object, a different thickness lead frame partially having different thicknesses is used. On a thick portion of the different thickness lead frame, a special electronic component, such as an LED, for which a high current and heat radiation are required is mounted. Further, a thin portion of the different thickness lead frame is formed at a fine pitch, and general electronic components are mounted at a high density on the thin portion. Thus, unitization or modularization of electronic components for which a high current and heat radiation are required becomes possible.Type: GrantFiled: September 25, 2006Date of Patent: September 11, 2012Assignee: Panasonic CorporationInventors: Tetsuya Tsumura, Hiroharu Nishiyama, Etsuo Tsujimoto
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Patent number: 8261428Abstract: The present invention discloses a method for assembling a 3D microelectrode structure. Firstly, 2D microelectrode arrays are stacked to form a 3D microelectrode array via an auxiliary tool. Then, the 3D microelectrode array is assembled to a carrier chip to form a 3D microelectrode structure. The present invention uses an identical auxiliary tool to assemble various types of 2D microelectrode arrays having different shapes of probes to the same carrier chip. Therefore, the method of the present invention increases the design flexibility of probes. The present invention also discloses a 3D microelectrode structure, which is fabricated according to the method of the present invention and used to perform 3D measurement of biological tissues.Type: GrantFiled: November 25, 2009Date of Patent: September 11, 2012Assignee: National Tsing Hua UniversityInventors: Weileun Fang, Yu-Tao Lee, Yen-Chung Chang
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Patent number: 8256113Abstract: A method of manufacturing an electrically driven L.E.D. lamp assembly (20) comprises disposing an electrically insulative coating (24) on a thermally conductive substrate (22). A plurality of light emitting diodes (26) is secured to the coating (24). A coupling agent is disposed on a tape portion (48) of a foil tape (46), and the foil tape (46) is secured to the coating (24) with the coupling agent in predetermined spaced lengths (42) along the coating (24) to establish discrete and electrically conductive spaced lengths (42) with the light emitting diodes (26) disposed between the spaced lengths (42). Each light emitting diode (26) includes a pair of electrical leads (32) which are secured to the spaced lengths (42) to electrically interconnect the light emitting diodes (26).Type: GrantFiled: May 18, 2009Date of Patent: September 4, 2012Assignee: Relume Technologies, Inc.Inventor: Peter A. Hochstein
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Patent number: 8256111Abstract: A method for laying out a circuit board includes following steps. A substrate board is formed with a plurality of board sides. A ground plane, including a plurality of tiles, is provided. Each ground trace tile is defined by a plurality of ground traces. A signal plane on the substrate board has a plurality of signal traces that comprise of a plurality of straight line segments. Any one ground trace of each tile is arranged at an angle other than zero degrees relative to one determined board side. The straight line segments is applied to be mapped on the ground plane crossing one ground trace of one tile within an angle range determined by the ground traces of the tile and an adjacent diagonal line of the tile. The one ground trace and the straight line segments are applied at an angle movable in a range from 22.5° to 32.5°.Type: GrantFiled: December 22, 2009Date of Patent: September 4, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yu-Hsu Lin, Jeng-Da Wu, Chih-Hang Chao
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Patent number: 8250745Abstract: A process for manufacturing a single microcircuit into an integrated cochlear electrode array includes securing and supporting a nonconductive film substrate; attaching a metallic ribbon to a surface of the substrate; machining a flat multiconductor microcircuit from the ribbon to produce a flat elongated multiconductor tail portion with spaced outwardly exposed electrode receiving pads, and a flat multiconductor head portion connected to the tail portion and having spaced outwardly exposed attachment pads; laminating the flat microcircuit between the film substrate and an insulating cover; excising the laminated microcircuit from the film substrate with the electrode receiving pads exposed; wrapping the tail portion of the excised laminated microcircuit into a helix with the exposed electrode receiving pads wrapped around the insulating cover; mounting and electrically connecting the ring electrodes on and to the exposed electrode pads; and overmolding the helix tail portion with a polymeric material to readType: GrantFiled: December 18, 2008Date of Patent: August 28, 2012Assignee: Advanced Bionics, LLCInventor: William G. Orinski
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Publication number: 20120210576Abstract: This invention relates to a printed circuit board and a method of manufacturing the same, in which an outermost layer of the printed circuit board includes a fine circuit and the manufacturing cost of the printed circuit board is reduced.Type: ApplicationFiled: May 1, 2012Publication date: August 23, 2012Inventors: Jin Yong AN, Suk Hyeon CHO, Ji Hong JO
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Patent number: 8245390Abstract: The present invention relates to a method of manufacturing a printed wiring board (PWB) of the type depicted in FIG. 1. Such a PWB comprises a first substrate and alternating layers of a second substrate and a metal layer. The layer 2 metallization of the PWB is a thick layer of a composite engineered metal material having a configurable coefficient of thermal expansion (CTE) to provide CTE matching with respect to radio frequency (RF) components mounted on the PWB, and having substantial heat dissipation properties to dissipate heat generated by the RF components. This composite metal layer also provides a ground plane for the RF components.Type: GrantFiled: November 6, 2007Date of Patent: August 21, 2012Assignee: Lockheed Martin CorporationInventors: William S. McKinley, Steve T. Nicholas, Jeffery A. Dean
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Patent number: 8245397Abstract: A process of twinning a pair of polymer-insulated conductors to form a twisted pair, where the polymer-insulated conductors are formed by extruding a uniformly thick coating of polymer onto the conductors. More than one twisted pair is encased in a polymer jacket forming a cable. The twisted pair obtains a desirable average impedance performance using a reduced amount by weight of polymer forming said polymer-insulated conductors by: (i) extruding to form longitudinally running peaks and valleys in the exterior surface of each of the polymer-insulated conductors of the pair of polymer-insulated conductors and (ii) twinning resultant polymer-insulated conductors to nest at least one of the peaks in the exterior surface of one of the polymer-insulated conductors in at least one of said valleys in the exterior surface of the other of the polymer-insulated conductors of the pair of polymer-insulated conductors.Type: GrantFiled: August 6, 2010Date of Patent: August 21, 2012Assignee: E. I. du Pont de Nemours and CompanyInventors: Gary Thuot, Robert Thomas Young, John L. Netta
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Patent number: 8245392Abstract: A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.Type: GrantFiled: December 1, 2009Date of Patent: August 21, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Patent number: 8245389Abstract: The invention aims to provide substrate treatment equipment that can automatically collect a substrate in a normal condition without needing manual operation. The equipment includes a substrate holder for holding substrates in a multistage manner and a substrate transfer unit for transferring the substrates into the substrate holder, wherein a substrate holding condition of the substrate holder is sensed by a sensing section. The sensing section has photo-sensors, and sensing waveforms sensed by the photo-sensors are compared with a normal waveform. A control section is provided, which controls a substrate transfer unit such that substrates other than at least a substrate that was determined to be abnormal are transferred by the unit.Type: GrantFiled: March 31, 2011Date of Patent: August 21, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Makoto Hirano, Akihiro Yoshida
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Patent number: 8240031Abstract: A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.Type: GrantFiled: July 16, 2010Date of Patent: August 14, 2012Assignee: Endicott International Technologies, Inc.Inventors: Voya R. Markovich, Ronald V. Smith, How T. Lin, Frank D. Egitto, Rabindra N. Das, William E. Wilson, Rajinder S. Rai
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Patent number: 8240022Abstract: Method of connecting an antenna wire to a transponder chip. A transponder chip or chip module in a recess in a substrate, and an antenna wire mounted to the surface of the substrate and having end portions spanning the recess. The end portions are spaced wider than the chip, to allow the chip to be inserted (installed) into the recess from the same side as the antenna past the end portions of the antenna wire. The chip may be moved in the recess so that its terminals are under the wires, or the wires may be repositioned to be over the terminals, for subsequently bonding thereto. Prior to installing the chip in the recess, insulation may be removed from the end portions of the antenna wire, which may also be flattened to improve bonding.Type: GrantFiled: August 1, 2007Date of Patent: August 14, 2012Assignee: Feinics Amatech TeorowitaInventor: David Finn
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Patent number: 8240036Abstract: An object of an aspect of the present invention is to provide a method of producing a circuit board that allows highly accurate preservation of the circuit profile and gives a circuit having a desired depth in preparation of a fine circuit by additive process.Type: GrantFiled: December 2, 2008Date of Patent: August 14, 2012Assignee: Panasonic CorporationInventors: Shingo Yoshioka, Hiroaki Fujiwara
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Patent number: 8234787Abstract: A first film adhesive between actuator units and a supply port plate, a second film adhesive between a reservoir plate and the supply port plate, and a third film adhesive between the reservoir plate and a nozzle plate are each provided with round holes having an equal size and formed in correspondence to the locations of nozzle communication ports. Thanks to the round holes having the equal size one another, irregularity in capacities of spaces formed by layers of the first film adhesive, the second adhesive, and the third film adhesive are reduced, thereby reducing a difference of passage resistance caused in the nozzle communication ports. Accordingly, it is possible to realize a printing head capable of reducing irregularity in an amount of ejected ink and a speed of ink drops between nozzles.Type: GrantFiled: March 24, 2011Date of Patent: August 7, 2012Assignee: Seiko Epson CorporationInventor: Satoshi Sugawara
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Patent number: 8234781Abstract: Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.Type: GrantFiled: September 14, 2009Date of Patent: August 7, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Young Gwan Ko
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Patent number: 8231692Abstract: During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.Type: GrantFiled: November 6, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Martin P. Goetz, Gary E. O'Neil
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Publication number: 20120190247Abstract: This disclosure is directed to apparatuses, systems, and methods associated with a connector assembly for use with surface mount technology (SMT). The connector assembly has a connector header configured to be mounted to a circuit board and is constructed of a high-temperature resistant material suitable for use with a reflow soldering process. The connector header includes at least one connector socket and at least one mounting shoulder, and is configured to be coupled to a header attachment assembly. The header attachment assembly comprises at least one connector pin and at least one mounting shoulder, and is configured to be coupled to the connector header. An electronic device, such as a card reader or hard drive, may be connected to the header attachment assembly and thereby to the circuit board. The connector assembly allows for the obstructed view inserting and attaching in a manual or an automated assembly process.Type: ApplicationFiled: November 17, 2011Publication date: July 26, 2012Inventors: Earl Anthony Daughtry, Yi Fei Luo, Chi-Lun Lin
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Patent number: 8225471Abstract: Embodiments of an injection molded energy harvesting device are described. In one embodiment, a piezoelectric cantilever is produced via an injection molding method to harvest vibration energy from an environment being sensed. The cantilever device consists of a piezoelectric material member, a proof mass of high density material coupled to the piezoelectric member, and a leadframe for electrical connection. The piezoelectric member is electrically attached to the leadframe with a standard connecting material. The entire assembly is then injection molded with plastic. The plastic encased piezoelectric member forms a cantilever that generates electricity in response to vibration exerted on the proof mass.Type: GrantFiled: May 27, 2010Date of Patent: July 24, 2012Assignee: Robert Bosch GmbHInventor: Brian Stark
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Patent number: 8225492Abstract: A method of assembling a touch panel including a support structure and a conductive membrane, the support structure having a conductive surface and a peripheral insulating spacer about the conductive surface. The conductive membrane overlies the peripheral insulating spacer separating the conductive membrane and the conductive surface thereby to define an air gap therebetween. The method comprises tensioning the conductive membrane prior to securing to the insulating spacer; and securing the tensioned conductive membrane to the insulating spacer.Type: GrantFiled: March 11, 2010Date of Patent: July 24, 2012Assignee: SMART Technologies ULCInventors: Paul Anthony Auger, Amir Butmir
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Patent number: 8220143Abstract: A plastic lead frame with reflection and conduction metal layer includes a base made of a metal catalyst containing or an organic substance containing plastic material, the base further includes a slanted reflection surface formed downwardly on top of the base; an insert slot continuously and staggeringly formed along the circumferential fringe of the base; a molded carrier made of non-metallic catalyst or organic substance containing plastic material accommodated in the insert slot; an interface layer formed on the surface of the base by chemical deposition; an insulation route formed on the surface of the base by ablating part of the interface layer with the laser beam radiation; and a metallic layer formed on the base by electroplating process thereby forming a plastic lead frame of excellent electrical conductivity and high light reflection property.Type: GrantFiled: May 22, 2009Date of Patent: July 17, 2012Assignee: Kuang Hong Precision Co., LtdInventor: Cheng-Feng Chiang
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Patent number: 8220144Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.Type: GrantFiled: November 18, 2008Date of Patent: July 17, 2012Assignee: ASUSTeK Computer Inc.Inventors: Chia-Hsing Chou, Chih-Wei Tsai
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Patent number: 8215018Abstract: There is provided a method for manufacturing a liquid discharge head that includes a discharge port, a supply path for supplying the liquid to the discharge port, a transparent member, and an absorptive member, wherein the transparent member and the absorptive member include supply path sections that become a part of a wall of the supply path. The method includes bringing the transparent and absorptive member into contact with each other in such a manner that surfaces of both members including the supply path sections are brought into contact with each other in the vicinity of the supply path sections, welding the both members by irradiating the contact portion where the both members are in contact with each other with the laser beam, and exhausting gas from an exhaust path formed on the liquid discharge head in the vicinity of the contact portion at least throughout the welding process.Type: GrantFiled: April 2, 2010Date of Patent: July 10, 2012Assignee: Canon Kabushiki KaishaInventors: Osamu Morita, Kiyomitsu Kudo
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Patent number: 8215012Abstract: A method of manufacturing a thermal contact arrangement. The method including the operations of providing a thermal conductor and forming a first zone having a first roughness on a first portion of a first exterior surface of the thermal conductor. The method further including the operation of forming a second zone having a second roughness on a second portion of the first exterior surface of the thermal conductor. The second portion is unique from the first portion and formed from a part of the thermal contact arrangement other than the first portion and the second roughness is rougher than the first roughness.Type: GrantFiled: October 2, 2008Date of Patent: July 10, 2012Assignee: Apple Inc.Inventor: Richard Lidio Blanco, Jr.
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Publication number: 20120170231Abstract: A folded stacked package and a method of manufacturing the same are provided. The folded stacked package includes a flexible board or substrate comprising first, second and third device packaging units, and first and second folding unit units. The flexible board has wiring patterns formed thereon; one or more active devices disposed in at least one of the first, second, and third device packaging units; and one or more passive devices disposed on a surface of each of the first and second device packaging units. The passive devices include one or more first passive devices disposed on the surface of the first device packaging unit and one or more second passive devices disposed on the surface of the second device packaging unit. The first and second passive devices do not overlap each other when the flexible board is folded at the folding unit.Type: ApplicationFiled: August 4, 2011Publication date: July 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Baik-Woo LEE
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Publication number: 20120165759Abstract: Described herein are flexible and stretchable LED arrays and methods utilizing flexible and stretchable LED arrays. Assembly of flexible LED arrays alongside flexible plasmonic crystals is useful for construction of fluid monitors, permitting sensitive detection of fluid refractive index and composition. Co-integration of flexible LED arrays with flexible photodetector arrays is useful for construction of flexible proximity sensors. Application of stretchable LED arrays onto flexible threads as light emitting sutures provides novel means for performing radiation therapy on wounds.Type: ApplicationFiled: March 11, 2011Publication date: June 28, 2012Inventors: John A. Rogers, Rak-Hwan Kim, Dae-Hyeong Kim, David L. Kaplan, Fiorenzo G. Omenetto
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Patent number: 8205327Abstract: A method for manufacturing a circuit board on which an electronic component is mounted, includes at least the steps of (a) supplying a liquid photo-polymerizable adhesive containing conductive particles dispersed therein to a surface of a printed board, to form an adhesive layer on the board surface; (b) irradiating the photo-polymerizable adhesive with ultraviolet light to turn into a gel, to provide adhesiveness to the adhesive layer; and (c) pressing the electronic component against the component mounting portion of the printed board from an upper surface side of the adhesive layer, to form an electrical connection between the electronic component and the component mounting portion, and in the method, the photo-polymerizable adhesive is a delayed reactive adhesive.Type: GrantFiled: November 13, 2006Date of Patent: June 26, 2012Assignee: Panasonic CorporationInventors: Hidenori Miyakawa, Atsushi Yamaguchi, Kazuhiro Nishikawa, Kunio Hibino
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Patent number: 8205329Abstract: An object is to obtain a dielectric layer constituting material, a capacitor circuit forming piece, etc. in which unnecessary dielectric layer is removed except capacitor circuit parts that improve accuracy of position of an embedded capacitor circuit in a multi-layer printed wiring board. For the purpose of achieving the object, “a method for manufacturing a dielectric layer constituting material characterized in that step a is a step for forming a first electrode circuit by etching a conductor layer on one side of a metal clad dielectric comprising a conductor layer on each side of a dielectric layer; step b is a step for removing the dielectric layer that is exposed between the first electrode circuits to manufacture the dielectric layer constituting material; and the step a is conducted and then the step b is conducted” is adopted.Type: GrantFiled: August 9, 2005Date of Patent: June 26, 2012Assignee: Mitsuimining & Smelting Co., Ltd.Inventors: Kensuke Nakamura, Kazuhiro Yamazaki
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Publication number: 20120155038Abstract: The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board (20), a second insulating layer (24) made of an inorganic material is positioned between a wiring layer (25) and a first insulating layer (23) made of an inorganic material.Type: ApplicationFiled: July 28, 2010Publication date: June 21, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yasumori Fukushima, Masaki Fujiwara, Steven Roy Droes
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Publication number: 20120151760Abstract: A method of manufacturing a touch screen display may include heating a substantially planar glass sheet to a working temperature. The planar glass sheet may be bent into a non-planar configuration to include a curved inside surface and a curved outside surface. The curved inside surface may be ground to form a substantially planar inside surface. A touch screen assembly may be mounted to the substantially planar inside surface.Type: ApplicationFiled: December 15, 2010Publication date: June 21, 2012Applicant: SONY ERICSSON MOBILE COMMUNICATIONS ABInventor: Magnus Steijner
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Patent number: 8196296Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.Type: GrantFiled: October 14, 2008Date of Patent: June 12, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuji Yukiiri, Izumi Tanaka
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Patent number: 8198546Abstract: A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.Type: GrantFiled: November 23, 2007Date of Patent: June 12, 2012Assignee: Ibiden Co., Ltd.Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
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Patent number: 8196298Abstract: Disclosed is a method for manufacturing an electroconductive material-filled throughhole substrate that is free from any void part in the electroconductive material filled into the throughholes. The method comprises forming an electroconductive base layer on one side of a core substrate having throughholes, and precipitating and growing an electroconductive material from one direction within the throughholes by electroplating using the electroconductive base layer as a seed layer to fill the electroconductive material into the throughholes without forming any void part and thus to manufacture an electroconductive material-filled throughhole substrate.Type: GrantFiled: October 13, 2010Date of Patent: June 12, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Shigeki Chujo, Koichi Nakayama
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Patent number: 8191241Abstract: A multi-turn coil device comprising a flexible circuit board and a plurality of serially electrically coupled coils coupled to both sides of the flexible circuit board. The coils are formed such that when the circuit board is folded in an accordion manner, the coils are substantially aligned and have the same direction of current flow. The coils are serially coupled sequentially from front to back and back to front wherein the coupling of the coils is through a plated through hole in the flexible circuit board.Type: GrantFiled: March 28, 2008Date of Patent: June 5, 2012Assignee: Flextronics AP, LLCInventor: Bruce D. Olson
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Patent number: 8186054Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.Type: GrantFiled: March 17, 2010Date of Patent: May 29, 2012Assignee: Kinsus Interconnect Technology Corp.Inventors: Chien-Wei Chang, Ting-Hao Lin, Jen-Fang Chang, Yu-Te Lu, Chia-Chi Lo
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Patent number: 8186045Abstract: A method of manufacturing a multilayer printed circuit board, including providing a substrate, embedding an electronic component having a die pad on a surface of the component into the substrate such that the component has the surface and pad exposed from a surface of the substrate, forming a metallic layer including metallic film layers such that the surface of the substrate and the pad and surface of the component are covered with the metallic layer, providing a resist on the metallic layer such that a portion of the metallic layer on the pad is exposed from the resist, forming a thickening metallic layer on the portion of the metallic layer exposed, removing the resist from the substrate and surface of the component, and etching to remove the metallic layer such that a mediate layer including the portion of the metallic layer is formed between the pad and the thickening layer.Type: GrantFiled: April 15, 2008Date of Patent: May 29, 2012Assignee: Ibiden Co., Ltd.Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
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Patent number: 8186028Abstract: A method for manufacturing a piezoelectric resonator, comprising the step of: producing an arrangement comprising a piezoelectric layer having a resonance frequency temperature coefficient of a first sign, a first and a second electrode. The piezoelectric layer is arranged between the first and second electrodes, and a compensation layer is arranged between the first electrode and the piezoelectric layer. The compensation layer has a compensation material having a second resonance frequency temperature coefficient of a second sign opposite to the first one. The producing comprises providing the compensation material with a modification material to increase a conductivity of the compensation layer in a direction between the first electrode and the piezoelectric layer.Type: GrantFiled: December 29, 2008Date of Patent: May 29, 2012Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.Inventor: Robert Aigner
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Patent number: 8186044Abstract: A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent.Type: GrantFiled: April 13, 2007Date of Patent: May 29, 2012Assignee: Abbott Diabetes Care Inc.Inventors: Benjamin J. Feldman, Adam Heller, Ephraim Heller, Fei Mao, Joseph A. Vivolo, Jeffery V. Funderburk, Fredric C. Colman, Rajesh Krishnan
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Patent number: 8187667Abstract: A method for disposing a component comprises: a step of preparing a substrate and a first liquid; a step of preparing a component-containing liquid containing the components and a second liquid; a step of disposing the first liquid in a hydrophilic region; a step of bringing the component-containing liquid into contact with the first liquid disposed on the hydrophilic region; a step of removing the first liquid and the second liquid to dispose the component on the hydrophilic region. The hydrophilic region is composed of a component-disposing region and a liquid-capturing region formed on the periphery of the component-disposing region.Type: GrantFiled: May 31, 2011Date of Patent: May 29, 2012Assignee: Panasonic CorporationInventor: Hidekazu Arase
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Patent number: 8186053Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as strength and thermal expansion coefficient. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs formed by disposing carbon fibers so as to produce openings at positions where plated through holes will pass through and impregnating the carbon fibers with resin; a step of forming through holes that pass inside the openings at positions of the openings in the core portion; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the carbon fibers and thereby produce a core substrate.Type: GrantFiled: November 14, 2008Date of Patent: May 29, 2012Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Kishio Yokouchi, Hideaki Yoshimura, Katsuya Fukase
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Publication number: 20120124828Abstract: A printed circuit board with an electronic component embedded printed circuit board and a manufacturing method thereof are disclosed. According to an embodiment of the present invention, the method of manufacturing a printed circuit board with an embedded electronic component having a groove formed on one surface thereof and an electrode formed inside the groove includes: forming a first circuit pattern on one surface of a first metal layer; pressing the first metal layer against a first insulator; forming a first conductive protrusion by selectively etching the other surface of the first metal layer; and mounting a first electronic component by disposing a conductive adhesive layer such that an electrode of the first electronic component and the first conductive protrusion are electrically connected to each other. Thus, an electronic component without its electrode protruded outward can be mounted easily and reliably and the manufacturing time can be shortened.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Woon-Chun KIM, Soon-Gyu Yim
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Patent number: 8181341Abstract: A method of forming a circuit board which includes generating laser light with a carbon dioxide laser and making a hole through an insulating substrate by irradiating the insulating substrate with the laser light. The hole includes a top opening in a top surface of the insulating substrate, a bottom opening in a bottom surface of the insulating substrate, and an inner wall extending from the top opening to the bottom opening along a thickness direction of the insulating substrate, the inner wall including a bulge which extends in a direction generally orthogonal to the thickness direction. A via hole is formed in the insulating substrate by providing metal in the hole such that the metal extends from the top opening to the bottom opening along the inner wall, and completely closes each of the top and bottom openings.Type: GrantFiled: June 22, 2009Date of Patent: May 22, 2012Assignee: Ibiden Co., Ltd.Inventors: Michimasa Takahashi, Yukinobu Mikado, Takenobu Nakamura, Masakazu Aoyama
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Patent number: 8181342Abstract: Disclosed are a coreless packaging substrate and a manufacturing method thereof. The substrate includes a built-up structure and a first wiring layer. The built-up structure has a first outside and an opposite second outside, and includes one or more second dielectric layers and second wiring layers, and a plurality of conductive vias. The second dielectric layers have first and second surfaces respectively facing the first and second outsides. The second wiring layers are disposed on the second surface. The conductive vias are disposed in the second dielectric layer. The outermost second wiring layer at the second outside has a plurality of second conductive pads. The first wiring layer is embedded into and exposed from the first surface of the outermost second dielectric layer at the first outside, and has a plurality of first conductive pads. The conductive vias electrically connect the first wiring layer and the second wiring layer.Type: GrantFiled: December 8, 2009Date of Patent: May 22, 2012Assignee: Unimicron Technology Corp.Inventors: Jen-Hung Chiang, Chao-Meng Cheng
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Patent number: 8178154Abstract: A method for disposing a component comprises: a step of preparing a substrate and a first liquid; preparing a component-containing liquid containing the components and a second liquid; a step of disposing the first liquid in a hydrophilic region; a step of bringing the component-containing liquid into contact with the first liquid disposed on the hydrophilic region; a step of removing the first liquid and the second liquid to dispose the component on the hydrophilic region. The hydrophilic region is composed of a component-disposing region and a liquid-capturing region formed on the periphery of the component-disposing region. The liquid-capturing region comprises a surface represented by the following chemical formula I.Type: GrantFiled: May 31, 2011Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventor: Hidekazu Arase