And Shaping, E.g., Cutting Or Bending, Etc. Patents (Class 29/835)
  • Patent number: 6628527
    Abstract: A unit interconnection substrate for mounting leadless type electronic parts on a mount substrate by superposing them on each other in two or more stages, comprising an insulating surface on the top surface of which an interconnection circuit with conductor pads and connection terminals is formed, depressions for holding electronic parts formed in a bottom surface of the insulating substrate, connection terminals provided on the bottom surface of the insulating substrate on the periphery of the depression, and connection terminals electrically connected to the connection terminals of the top surface of the insulating substrate via conductor via holes provided in the insulating substrate. Electronic parts are electrically connected to the conductor pads on the top surface of the insulating substrate, thereby to make it possible to mount the electronic parts on the insulating substrate.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: September 30, 2003
    Assignee: Shinko Electric Industries Company, Ltd.
    Inventors: Shigetsugu Muramatsu, Takuya Kazama
  • Publication number: 20030167631
    Abstract: A method and assembly for terminating premises automation equipment wiring by mounting premises automation components in readily available holders. A mount for premises automation system components is provided using a punchdown block holder. Opposing tabs of the punchdown block holder bias a printed circuit board (PCB) or a mechanical adapter plate against the holder's top surface. The PCB or mechanical adapter are sized and shaped so that the PCB or adapter snaps in between the tabs and is held against the block holder. An additional PCB may be mounted on top of the first PCB or adapter using coaxial holes and fasteners. The planimetric shape of the first PCB or adapter may vary so long as it snuggly fits in the punchdown block holder, and the second PCB may have the same planimetric shape as or vary from that of the first PCB or adapter.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 11, 2003
    Inventor: Peter D. Hallenbeck
  • Patent number: 6581274
    Abstract: Apparatus having a mandrel, and a ring having an aperture therein, the ring being slidable over the mandrel. A multilead electronic component having electric leads extending therefrom is positioned atop the mandrel. The ring is pressed over the mandrel, bending the electric leads downward. When the ring is retracted, springback forces within the bent electric leads forces them against the inside of the ring; and the multilead electronic component is retained therewithin. The ring is then used, either manually or robotically, to position the component proximate a printed-circuit board with the electric leads aligned with connection apertures in the printed-circuit board. The multilead electronic component is pressed toward the printed-circuit board, forcing the leads through the connection apertures; and the ring is withdrawn for subsequent use.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: June 24, 2003
    Assignee: Trans Tron Ltd., Inc.
    Inventors: Michael E. Salmon, Gary L. Dumer, Martin F. Folgmann, William S. Hyde
  • Patent number: 6580031
    Abstract: A low-modulus-of-elasticity flexible adhesive interposer substrate has high aspect ratio via conductors to which an electronic device, such as a semiconductor chip or die or other component, is attached, e.g., for a high density electronic package. A method for making the flexible adhesive interposer substrate includes etching a sheet of metal to form the high aspect ratio via conductors which are held in position by a sheet or layer of a molecularly flexible adhesive. The via conductors may be built up to even greater aspect ratio. Such flexible interposer may include high aspect ratio via conductors for a plurality of similar or different electronic devices.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: June 17, 2003
    Assignee: Amerasia International Technology, Inc.
    Inventor: Kevin Kwong-Tai Chung
  • Patent number: 6574862
    Abstract: In a method for coupling a PCB sheet, if a defective PCB is found after the manufacture of continuously arranged circuit patterns, then the defective PCB sheet portion is removed to replace it with a new PCB sheet portion. That is, a defective circuit pattern sheet is removed from continuously arranged circuit patterns of a first PCB sheet. After removal of the defective circuit pattern sheet, the first PCB sheet is position-located by a position locator. Then, the space which is formed by removing, the defective circuit pattern sheet is filled with a second PCB sheet on which a good quality circuit pattern is printed. Then, the first PCB sheet and the second PCB sheet are coupled together by using an adhesive.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: June 10, 2003
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bong Kyu Choi, Chun Ho Choi
  • Patent number: 6568054
    Abstract: A method of producing a multilayer electronic part having the shape of a substantially rectangular parallelopiped is constituted which has a multilayer body formed by superposing coil conductors and green sheets of a magnetic or nonmagnetic material. Terminal electrodes are formed respectively on both ends of the multilayer body along the direction of the magnetic flux generated when current is caused to flow through the coil conductors in the multilayer body. The terminal electrodes each has a conductive substrate formed within the area of the end of the multilayer body and including a lamination body as a component of the multilayer body.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: May 27, 2003
    Assignee: TKD Corporation
    Inventors: Shuumi Kumagai, Kouzou Sasaki, Makoto Kobayashi, Noriyuki Saito, Hisayuki Abe, Toru Takahashi, Kenji Shibata
  • Patent number: 6516515
    Abstract: A method for stabilizing the form of a letter S of an inner lead after bonding in a method of manufacturing &mgr;BGA·IC in which a chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead is disclosed. The inner lead is bonded to the electrode pad when the chip is supplied in a fixed position for a bonding tool. Next, the respective positions of the inner lead and the electrode pad are recognized using a feature lead and an electrode pad. The center line of the inner lead is recognized, the inner lead is pushed to the chip in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: February 11, 2003
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
  • Publication number: 20020178579
    Abstract: In processing a head unit in which a head relative height Y is Y′ with a grinding amount &Dgr;GD of &Dgr;GD′, the relationship between distances Bo between a vertex of a curved surface as a front face of a head chip and a head gap before and after grinding the front face of the head chip and a gap depth dimension GD, is predetermined with respect to a head unit in which the head relative height is substantially equal to Y′, through which Bo1 as the value of Bo before grinding corresponding to a target value of the value of Bo after grinding is determined and used as Bo1 of the head unit in which the head relative height Y is Y′. Thus, grinding of the front face of the head chip is conducted after Bo1 corresponding to the target value is determined. Hence, a head unit with the value of Bo after grinding falling within the range of standard values can be manufactured efficiently, and accordingly the yield can be improved.
    Type: Application
    Filed: July 31, 2001
    Publication date: December 5, 2002
    Inventors: Tetsuya Okana, Mitsuhisa Fujiki, Satoshi Yamabayashi, Shinya Ogasawara
  • Patent number: 6483037
    Abstract: A flexible circuit (100) includes a first circuit path portion (110) and a second rigid circuit path portion (140) to which electronic components (102) may be coupled. Each circuit path portion (110 and 140) including a resin layer (112 and 142) and an adjacent conductive layer (114 and 144). Each circuit path portion (110 and 140) defining a gap (120 and 150) substantially running along a line corresponding to a desired bend location. A central circuit path portion (130) is disposed between the first circuit path portion (110) and the second rigid circuit path portion (140) and includes a first conductive layer (134) in electrical communication with the first circuit path portion (110) and a second conductive layer (136) in electrical communication with the second rigid circuit path portion (140), so as to provide electrical communication across the gaps (120 and 150). A metal plate (160) is disposed adjacent the second rigid circuit path portion (140).
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: November 19, 2002
    Assignee: Motorola, Inc.
    Inventors: Kevin D. Moore, Thomas P. Gall
  • Patent number: 6449829
    Abstract: method for making a high current, low profile inductor includes taking an elongated plate, cutting a plurality of slots in the sides of the plate so as to form a plurality of cross segments extending transversely with respect to the length of the plate and a plurality of connecting segments extending approximately axially with respect to the longitudinal axis of the plate. The method further requires bending the segments transversely with respect to the plate axis so as to place the opposite flat surfaces of the cross segments in planes parallel to one another and facing in an axial direction with respect to the longitudinal plate axis.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: September 17, 2002
    Assignee: Vishay Dale Electronics, Inc.
    Inventor: Timothy M. Shafer
  • Patent number: 6438827
    Abstract: A ceramic electronic part includes at least one chip ceramic electronic part body having terminal electrodes and terminals provided on both sides. Each terminal is composed of a metal plate bent into a u shape. The outer face of a first leg of each bent terminal faces and is attached to a terminal electrode, and a second leg is attached to a substrate. The inner face of the bent terminal is provided with a solder-phobic surface not having affinity for solder, and the outer face of the bent terminal is provided with a solder-philic surface having high affinity for solder.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: August 27, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takuji Nakagawa, Yoshikazu Takagi, Masayoshi Miyazaki, Hideki Nakayama, Masaru Takahashi, Akira Nakamura
  • Patent number: 6430810
    Abstract: This invention pertains to methods of forming a patterned metal layer in an electronic device, wherein the metal layer is in contact with an underlying organic polymeric layer (e.g., a conductive or semiconductive organic polymeric layer), which methods comprise mechanically scribing the metal layer with a mechanical scribing instrument to form the patterned metal electrode.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: August 13, 2002
    Assignee: Uniax Corporation
    Inventor: Phillip Bailey
  • Patent number: 6427892
    Abstract: A tool for separating a common printed wiring board substrate into a plurality of substrates where, prior to separation, the plurality of substrates are connected by at least one circuit connector. The purpose of the tool is to apply pressure along a dividing line to break the common substrate into separate boards without crimping or breaking the connectors between the boards. In a preferred embodiment, the tool has a beveled edge for contacting the common substrate with mechanism for adjusting the location of notches in the beveled edge. The notches are for alignment with the location of the connectors between the boards.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: August 6, 2002
    Assignee: Xerox Corporation
    Inventor: Harry M. Reijnders
  • Patent number: 6370767
    Abstract: A method and apparatus for dissipating heat from an electrical component. The method includes providing a planar element including a first electrically and thermally conductive region and a second electrically and thermally conductive region, such that the first and second regions define a spacing therebetween, and wherein the planar element includes at least one mechanically stabilizing tie connected between the first and second regions across the spacing, directly connecting a first terminal of an electrical component to the first region, directly connecting a second terminal of the electrical component to the second regions, such that the electrical component bridges the spacing, and removing the at least one mechanically stabilizing tie from between the first and second regions.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: April 16, 2002
    Assignee: Artesyn Technologies, Inc.
    Inventors: Terry B. Solberg, Daryl E. Weispfennig, Michael K. Hennies
  • Publication number: 20020035782
    Abstract: The object of the present invention is to form individual packaged ICs by using a single apparatus to cut wiring boards on which a plurality of IC chips are mounted.
    Type: Application
    Filed: September 20, 2001
    Publication date: March 28, 2002
    Applicant: ISHII TOOL & ENGINEERING CORPORATION
    Inventor: Mitoshi Ishii
  • Patent number: 6344161
    Abstract: Segmentation of a flexible, elongated, strip-shaped substrate having a plurality of encapsulated semiconductor devices mounted thereon, for device singulation, is facilitated by pre-cutting pairs of slots through the substrate at each device mounting area, which slots minimize the amount of substrate material required to be removed during device singulation. Disadvantageous penetration of the slots by liquid encapsulant material is substantially prevented, or at least minimized, by forming slots having burrs or flaps at the upper, mounting surface of the substrate which seal off, or substantially reduce the width of the slots.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 5, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: L. K. Suresh, Kanchit Suphanpeasat, Sally Y Foong
  • Patent number: 6334971
    Abstract: A manufacturing method for a diode group processed by injection molding on the surface thereof, the diode group is formed by having a plurality of left and right elongate tapes which are pressed to form respectively left and right contact ends, each pair of the left and right elongate tapes have a left lap end and a right lap end to sandwich a chip therebetween. Then injection molding is performed to envelop the left and right elongate tapes and to form an elongate strip having an insulation outer layer with the left and right contact ends exposed and with a recess at the bottom of and between every two neighboring chips. The recesses separate the left contact ends of the left elongate tapes from the right contact ends of the right elongate tapes but still leave the plural diodes in series connected mutually in an insulation state. The strip can be broken off at desire recesses to get a diode group having desired number of diodes processed by injection molding on the surface of the strip.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: January 1, 2002
    Inventor: Wen-Ping Huang
  • Patent number: 6247229
    Abstract: Methods for forming packages for housing an integrated circuit device are disclosed. In one embodiment, step 1 provides a plastic sheet having an adhesive first surface. Step 2 provides a patterned metal sheet on the first surface of the plastic sheet. The patterned metal sheet includes an array of package sites. Each package site is formed to include a die pad and a plurality of leads around the die pad. Step 3 places an integrated circuit device on each of the die pads. Step 4 connects a conductor between the integrated circuit device and the leads of the respective package site. Step 5 applies an encapsulating material onto the array. Step 6 hardens the encapsulating material. Step 7 removes the first plastic sheet. Step 8 applies solder balls to the exposed surfaces of the leads. Finally, step 9 separates individual packages from the encapsulated array.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: June 19, 2001
    Assignee: Ankor Technology, Inc.
    Inventor: Thomas P. Glenn
  • Publication number: 20010001989
    Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element and a second microelectronic element with confronting, spaced-apart surfaces defining a space therebetween and providing one or more masses of a fusible conductive material having a melting temperature below about 150° C. in said space, whereby the fusible conductive masses connect the first and second microelectronic elements to one another. Next, a flowable material is introduced between the confronting surfaces of the first and second microelectronic elements and around the one or more fusible conductive masses and the flowable material is then cured to provide a compliant layer disposed between said confronting surfaces and intimately surrounding each fusible conductive mass. The fusible conductive masses are capable of electrically interconnecting the contacts on microelectronic elements confronting one another and/or conducting heat between confronting microelectronic elements.
    Type: Application
    Filed: January 10, 2001
    Publication date: May 31, 2001
    Inventor: John W. Smith
  • Patent number: 6201185
    Abstract: A plurality of side-surface patterns 11 and 12 are disposed on the wall surfaces of a mount opening portion 2 for mounting electronic parts thereat. The mount opening portion includes projection portions 21 that project toward an interior thereof from the wall surfaces thereof. End portions of the respective side-surface patterns 11 and 12 extend to the side surfaces of the projection portions 21. Also, a plurality of side-surface patterns can be provided on the wall surfaces of the mount opening portion by etching the side-surface pattern non-formation portions of the conductive layer formed on the entirety of the wall surfaces of the mount opening portion in a state where the side-surface pattern formation portions are coated with a side-surface pattern resist film made of a negative photosensitive resin. With this structure, the side-surface patterns can be prevented from being peeled off, and side-surface patterns having a plurality of potentials can be readily formed.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: March 13, 2001
    Assignee: Ibiden Co., Ltd.
    Inventors: Naoto Ishida, Teruo Hayashi, Kiyotaka Tsukada
  • Patent number: 6189201
    Abstract: In a method of tuning a high frequency printed resonance circuit having a conductive layer that is printed on a dielectric substrate and that serves as an inductance of the resonance circuit, the conductive layer is ground to mechanically remove a portion thereof from the dielectric substrate via a grinding pin that is rotated about a rotary axis perpendicular to a major printed surface of the dielectric substrate, thereby correcting the inductance of the resonance circuit in order to tune the same.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: February 20, 2001
    Assignee: Sino Dragon Inc.
    Inventors: Czeslaw Trzaskowski, Henryk Krzemieniewski
  • Patent number: 6161214
    Abstract: A method is presented of generating data on component arrangement capable of shortening the moving distance of the mounting head in an electronic component mounting machine, and enhancing the mounting efficiency.The distribution center coordinates and their distributed state values of electronic components on a circuit board grouped in accordance with their kind are determined. The arrangement position of each electronic component at a component feed section is determined based on the distribution center coordinates. When the arrangement positions of more than two kinds of electronic components thus determined are the same, the arrangement position of the electronic component having a smaller distributed state value is preferentially determined.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: December 12, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuko Ishihara, Yasuhiro Maenishi
  • Patent number: 6138347
    Abstract: A conductive strap configured to attach to a circuit board containing a component sensitive to electronmagnetic interference (EMI) and to slidably contact an enclosure having a conductive internal surface can reduce or eliminate EMI in an electronic device. The strap is positioned on the circuit board to shield the sensitive component from EMI. Slidable contact between the shielding strap and the enclosure internal surface renders the strap suitable for almost any enclosure configuration without any design modification.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: October 31, 2000
    Assignee: Ericsson GE Mobile Communications Inc.
    Inventors: Per-Hakan Persson, Nils Rutger Rydbeck
  • Patent number: 6079099
    Abstract: A manufacturing method of an electronic component comprises the steps of: mounting components on a sheet substrate having a plurality of component-mounting substrates and a plurality of through holes on which shield case-mounting electrodes are respectively formed; establishing a state in which a plurality of shield case pawls are inserted into the plurality of through holes to cover the components with shield cases, and solder is buried in the plurality of through holes; thereafter securing the plurality of shield cases to the sheet substrate to cover the components by melting the solder to secure the shield case pawls to the shield case-mounting electrodes of the through holes by the solder; and thereafter dividing the sheet substrate into the plurality of component-mounting substrates by cutting the sheet substrate, thereby producing a plurality of the electronic components each including the component-mounting substrate, the component mounted on the component-mounting substrate and the shield case secured
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: June 27, 2000
    Assignee: Sumitomo Metal Industries Limited
    Inventors: Hideyuki Uchida, Masanobu Ono
  • Patent number: 5920984
    Abstract: A conductive strap configured to attach to a circuit board containing a component sensitive to electronmagnetic interference (EMI) and to slidably contact an enclosure having a conductive internal surface can reduce or eliminate EMI in an electronic device. The strap is positioned on the circuit board to shield the sensitive component from EMI. Slidable contact between the shielding strap and the enclosure internal surface renders the strap suitable for almost any enclosure configuration without any design modification.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: July 13, 1999
    Assignee: Ericsson GE Mobile Communications Inc.
    Inventors: Per-Hakan Persson, Nils Rutger Rydbeck
  • Patent number: 5888627
    Abstract: It is an object of the present invention to provide a highly reliable printed circuit board subject to little bowing or twisting of the substrate, wherein the substrate and metal wiring are securely bonded together, and stable electrical and mechanical connection is achieved between the metal wiring and electroconductive resin paste filled into the through holes, and to provide a method of manufacture for same. The present invention relates to a printed circuit board having a multilayer wiring structure comprising a plurality of sheet substrates consisting of resin component layers containing an inorganic filler formed onto both sides of an organic nonwoven fabric material, and two or more circuit patterns, wherein through holes are formed in the sheet substrates in the thickness direction thereof and an electroconductive resin component is filled into the through holes, forming electrical connection between each of the electrode layers, and to a method of manufacture for same.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: March 30, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Seiichi Nakatani
  • Patent number: 5834084
    Abstract: A low particulating circuit board for a disc drive flex assembly, and a method for forming the same, are disclosed. The circuit board comprises a conductive metal substrate which has sufficient thickness to provide mechanical support and backplane suppression for the circuit board and to efficiently sink heat generated by preamplifier circuitry housed by the circuit board. The substrate has dielectric layers formed on the top and bottom surfaces thereof, the dielectric layers comprising an epoxy interleaved with nonparticulating fibers, such as tetrafluorethylene (TFE) fibers. Traces and pads are provided on the dielectric layers to provide the necessary electrical connections for the preamplifier circuitry. A plurality of circuit boards are formed from a panel and subsequently cut therefrom. Particulate generation is minimized through the use of the metal substrate, as well as recession of the substrate and the solder masks to reduce the amount of material cut during the cutting operation.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: November 10, 1998
    Assignee: Seagate Technology, Inc.
    Inventor: Mark S. Maggio
  • Patent number: 5777886
    Abstract: A lead conditioning system (10) conditions leads (74) of electronic component package (30) and includes a rotary table (16) for holding electronic component package (30) and making accessible the leads (74). A conditioning tool (20) includes conditioner arm (34) and conditioner blade (70) that selectively contacts a predetermined number of the leads (74). A manipulator (22) moves conditioning tool (20) to positions that contact a predetermined number of leads (74) to condition leads (74). A control system (24) controls the operation of manipulator (22).
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: July 7, 1998
    Assignee: Semiconductor Technologies & Instruments, Inc.
    Inventors: Michael D. Glucksman, Weerakiat Wahawisan, Troy D. Moore, Paul H. Hasten, Dennis M. Botkin, James E. Loveless, Joseph Antao, Michael C. Zemek, Rajiv Roy
  • Patent number: 5642049
    Abstract: A magnetic field producing apparatus is obtained which can easily perform a connection work, while securing a connection work space of a vortex coil, and can omit a base member. A width of a groove at an inner peripheral turned portion of a vortex coil is made wide to form a space without positionally shifting a center of the respective turned portions of the vortex coil. An inner peripheral end of the vortex coil can be easily picked up, a junction work with a connection lead can be readily performed, and also a bending work can be properly achieved.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: June 24, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiro Harada, Naoji Yoshida, Yasuyuki Tahara, Kazuki Moritsu
  • Patent number: 5638596
    Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 17, 1997
    Assignee: LSI Logic Corporation
    Inventor: John McCormick
  • Patent number: 5619017
    Abstract: A method of connecting a semiconductor chip assembly having at least first and second contacts to a connection component including at least first and second connection leads by means of a tool consisting of the steps of juxtaposing moving and connecting the leads to the corresponding contacts. The connection component is juxtaposed with the semiconductor chip assembly so that the first and second connection leads are aligned with the first and second contacts in such a manner that the first connection lead is offset from the first contact in the first direction and the second connection lead is offset from the second contact in the same first direction.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: April 8, 1997
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Zlata Kovac, John Grange
  • Patent number: 5559433
    Abstract: A magnetic sensor device having output characteristics with high precision and a method of manufacturing the same. A thick film resistor is trimmed while a magnetic field is applied to a circuit board at a predetermined angle, thereby adjusting output characteristics of a hybrid integrated circuit on the circuit board and eliminating undesirable misalignment of the mounting position between an MR device and the circuit board. Subsequently, a dowel recess used as a first positioning member formed on the circuit board receives a dowel projection used as a second positioning member formed on a frame, the dowel projection complementary to the dowel recess, thus positioning and assembling the circuit board into the frame. The output characteristics obtained during trimming conform with those after assembly, thus obtaining a magnetic sensor device having output characteristics with high precision and achieving correct detection as a sensor.
    Type: Grant
    Filed: February 3, 1994
    Date of Patent: September 24, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shoko Onizuka
  • Patent number: 5491302
    Abstract: A method of connecting a semiconductor chip assembly having at least first and second contacts to a connection component including at least first and second connection leads by means of a tool consisting of the steps of juxtaposing moving and connecting the leads to the corresponding contacts. The connection component is juxtaposed with the semiconductor chip assembly so that the first and second connection leads are aligned with the first and second contacts in such a manner that the first connection lead is offset from the first contact in the first direction and the second connection lead is offset from the second contact in the same first direction.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: February 13, 1996
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Zlata Kovac, John Grange
  • Patent number: 5489749
    Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: February 6, 1996
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gary W. Grube, Igor Y. Khandros, Gaetan Mathiew
  • Patent number: 5455384
    Abstract: A method of producing a high frequency module comprises the steps of connecting leads to a circuit board, covering the circuit board with an insulating member such that the leads protrude from the insulating member, cutting off portions of the leads protruding from the insulating member having been molded, forming a metal film on the entire periphery of the insulating member, and removing the metal film around the leads to thereby form electrodes which are separate from the other portions of the metal film. The metal film is formed by evaporation, spraying or plating while the portions of the metal film around the leads are removed by chemical etching or machining. Further, the leads are connected to the circuit board on the same surface as electronic parts. The circuit board is covered with the insulating member in a rectangular parallelepiped configuration. The electrodes individually extend from the sides where the leads are present to the surface contiguous with the sides.
    Type: Grant
    Filed: March 25, 1994
    Date of Patent: October 3, 1995
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 5443534
    Abstract: Electronic components are provided for connection in electronic circuits being manufactured on a production line. A supply of component blanks is provided, and each of the electronic components is formed by removing material from one of the blanks. The electronic component is delivered for connection in a corresponding one of the electronic circuits. The steps of forming and delivering the electronic component are coordinated with the manufacture of the corresponding electronic circuit. Another aspect features high-volume, high-mix manufacture of electronic circuits on a production line, where the mix requires a number M of different component values within a range of values R, and N (smaller than M) different supplies of component blanks are provided, each supply suitable for making components having values within a subrange S of range R. In another aspect, operating parameters of a laser are determined automatically for use in trimming resistor blanks belonging to a common batch of blanks.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: August 22, 1995
    Assignee: VLT Corporation
    Inventors: Patrizio Vinciarelli, Hubert R. Zeller, III
  • Patent number: 5386625
    Abstract: A method of assembling an integrated circuit (IC) by a TAB (Tape Automated Bonding) system, and an IC assembled thereby. Leads extending from a TAB tape and connected to an IC are each partly reduced in width. Hence, even when the end portions of the leads are deformed by some object by accident, it is not necessary to correct the shape of the leads since such end portions will be eventually cut off and discarded in the event of packaging of the IC.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: February 7, 1995
    Assignee: NEC Corporation
    Inventor: Kenji Tsukamoto
  • Patent number: 5383095
    Abstract: A circuit board (12) and electrical connector (10) mounted to an edge (18) thereof is disclosed. The circuit board (12) includes an edge (18) and two major surfaces (14, 16) extending therefrom having circuitry (20). Plated through holes (24) are arranged adjacent the edge and are interconnected to circuitry on the circuit board. Each plated through hole (24) is associated with an opening such as a slot (26) or partial slot (27) that is formed in the edge (18) of the board so that it intersects the hole. The posts (32) of the connector (10) extend into the openings (26, 27) preferably in interference fit therewith whereafter soldering completes the electrical connections of the posts to the through holes.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: January 17, 1995
    Assignee: The Whitaker Corporation
    Inventors: Iosif Korsunsky, Dimitry G. Grabbe, Robert C. Klotz
  • Patent number: 5381308
    Abstract: A device and method for locking an electrical component, having a body and a flange portion, with a panel through a panel opening, in which the flange abuts a first face of the panel, which includes moving an actuator on the body of the component to displace a cam follower on the body from a first to a second position in which the cam follower projects beyond the contour of the body enough to abut another panel face.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: January 10, 1995
    Inventors: Richard W. Wolpert, Alan T. Wolpert, Richard A. Wolpert
  • Patent number: 5313016
    Abstract: An electromagnetic shielding clip for providing an electrical connection between two mating surfaces. The clip of the present invention comprises an electrically conductive sheet. The sheet is curved into a series of interconnected arc-shaped sections, each oriented opposite to the arc-shaped section adjacent to it. Two of the arc-shaped sections appear at opposite ends of the clip and are used to attach the clip to a mating surface through two parallel slots. Another arc-shaped section curves away from the parallel slots for contract to another mating surface. The present invention also includes a tool and method for inserting the clip.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: May 17, 1994
    Assignee: SynOptics Communications, Inc.
    Inventors: Peter V. Brusati, Diane L. Boross
  • Patent number: 5307555
    Abstract: An apparatus for forming the leads of electrical components such as five-leaded TO-220 packages is provided. Taped components are supplied from a reel to a sensor which detects the presence of an electrical component contained on the tape, and stops advancement of the tape. While the tape is stopped, a cutter singulates a segment of tape having at least one electrical component from the remainder of the tape. The singulated tape is then advanced through a lead forming station, where the leads of the electrical component are formed into the desired configuration. A method is also disclosed for forming the leads of electrical components supplied on a roll of tape.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: May 3, 1994
    Assignee: Ford Motor Company
    Inventors: Scott T. Eder, Gerald M. Lepley, Glenn J. Kahle
  • Patent number: 5269705
    Abstract: An electrical connector assembly (10) includes at least one signal contact (22) and one grounding structure (16) mounted in a dielectric housing (12) having flat exterior surface portions (19). A filter (32) is associated with each signal contact, if desired, and is in tape form with dielectric material (36) laminated between broad area electrodes (34,38) with the tape attached to the housing exterior surface (14); the dielectric material is selected to have a dielectric constant and thickness to provide a desired capacitance between signal and ground electrodes (34,38). The method includes electrically joining the signal and ground electrodes to the signal contact (22) and grounding structure (16) while pressing the tape filter along and against the exterior housing surfaces (19) between the connections, for the electrodes (34,38) of the filter to be connected between the signal contact and ground structure to effectively insert the filter in the signal path to ground.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: December 14, 1993
    Assignee: The Whitaker Corporation
    Inventors: James F. Iannella, Paul J. Anastasio
  • Patent number: 5265322
    Abstract: A one-piece electronic module assembly is formed from a substantially rectangular baseplate on which an insulating film is mounted to carry circuit components. An enclosed assembly is completed by initially providing a pair of major bend axes across the baseplate, and forming inwardly extending notches at selected locations along lengthwise edges of the baseplate. The baseplate is bent at the notches to form a front wall, a pair of sidewalls and tabs that overlap the sidewalls. The baseplate is then bent over on itself along the major bend axes and sealed, if necessary, to form a completed assembly.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: November 30, 1993
    Assignee: Motorola, Inc.
    Inventors: Timothy S. Fisher, Michael I. Petrites, Al Ocken
  • Patent number: 5235131
    Abstract: An RF conductive shield can be fabricated from, and adhered to, a nonconductive substrate in the following manner. The RF conductive shield is fabricated in a predetermined geometric shape on the nonconductive substrate. Once the RF conductive shield is fabricated, it is cut from the nonconductive substrate to produce a separate RF shield. Having a separate RF shield, it can be placed on the nonconductive substrate in a predetermined location and adhered thereto.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: August 10, 1993
    Assignee: Motorola, Inc.
    Inventors: Gary E. Mueller, Robert T. Hirsbrunner
  • Patent number: 5230145
    Abstract: A laser assembly including a diamond film submount is formed by anisotropically etching a localized indentation (recess) region in an originally completely planar face of the film. The region has one or pair of intersecting sidewalls preferably making the same angle between them as an angle made between a pair of sides of a laser device. After metallizing the remaining top face of the film, the bottom of the indentation region, and one or both of the sidewalls of the indentation region, the laser device is pushed into position in the recess with its above-mentioned pair of sides lying against one of the sidewalls and the metallization of the other sidewall, or lying against the metallization of both sidewalls; and the bottom of the laser device is quickly bonded by means of solder to the metallization on the bottom of the recess.
    Type: Grant
    Filed: July 15, 1992
    Date of Patent: July 27, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: David I. Caplan, Avishay Katz
  • Patent number: 5159751
    Abstract: An electronic module assembly (31) is provided by assembling components (17) to a planar polyimide flex circuit film (14) laminated to an aluminum rigidizer plate (11). The flex circuit film and rigidizer are then bent by a sheet metal bending process such that the rigidizer plate forms an exterior protective housing and the components are provided in an interior space (30). Connector pins (23) provide external electrical access to the components and circuit patterns (15, 16, 19) on the film (14). Structures (24, 25, 29) mate with the bent plate and substantially enclose the interior space. Module cost is reduced since the existing flex circuit rigidizer plate is used to form part of the module housing, and economical planar component assembly techniques are utilized while eliminating the step of mounting the flex circuit rigidizer plate to an external module housing. Two techniques for using a mandrel shaft (26, 35) to bend the plate (11) without stressing the film (14) are disclosed.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: November 3, 1992
    Assignee: Motorola, Inc.
    Inventors: David J. Cottingham, Michael J. Petrites, Thomas J. Tischhauser
  • Patent number: 5143277
    Abstract: Disclosed is a method for the mounting, on an flexible substrate, of miniature electronic components of the beam lead type. Said method consists, after a first connection lead of a component has been soldered to the substrate, in arching each of the other connection leads of the component considered during their soldering by pressing the connection lead considered on a metallized zone of the substrate by means of a tip of a soldering tool while, at the same time, making a approaching movement towards the body of the component considered with this tip before carrying out the soldering operation itself. Through this mounting method, the beam lead electronic components are no longer placed flat against the substrate with their connection leads in an extended position but are arched on these leads. This gives them a freedom of play that enables them to absorb mechanical stresses by adopting positions of greater flatness or lesser flatness on the substrate.
    Type: Grant
    Filed: January 24, 1992
    Date of Patent: September 1, 1992
    Assignee: Thomson-CSF
    Inventors: Pascal Roche, Claude Courtin
  • Patent number: 5102828
    Abstract: Two superimposed series of electric contacts in the shape of metal-sheet strips, electrically connected to a metallic place which supports a semiconductor chip, are electrically separated but mechanically connected by an interposed layer of adhesive material at high insulation. The whole is completely inserted in a covering of insulating material, which forms a flat support, from which, at opposite faces, only limited adjacent contact portions of said electric contacts emerge.The place and at least one of the two series of contacts make part of a single starting metallic frame, on which the other series of contacts is superimposed. This latter in its turn can make part of the same metallic frame and to be superimposed by refolding or can be prepared separately and then applied on the first series.
    Type: Grant
    Filed: April 20, 1989
    Date of Patent: April 7, 1992
    Assignee: SGS-Ates Componenti Elettronici S.p.A.
    Inventor: Giuseppe Marchisi
  • Patent number: 5100492
    Abstract: In a process for manufacturing printed-circuit boards which have rigid and flexible areas or internal layers of printed-circuit boards, a piece of the surface is punched out to form a window in every area of the insulating layer material which is to be flexible. The punched out piece is reinserted into the punched-out window as a filling piece before laminating the compound of individual layers.
    Type: Grant
    Filed: January 16, 1990
    Date of Patent: March 31, 1992
    Assignee: Firma Carl Freudenberg
    Inventors: Horst Kober, Uwe Horch
  • Patent number: 5054192
    Abstract: A method and apparatus for interconnecting electronic circuits using nearly pure soft annealed gold mechanically compressed within through-plated holes. The invention has its application in attaching integrated circuit dice directly to circuit boards by ball bonding gold wires to the bonding pads of the integrated circuit dice in a substantially perpendicular relationship to the surfaces of the dice and inserting the gold leads into through-plated holes of circuit boards which provide an electrical and a mechanical connection once the leads are compressed within the through-plated holes. The present invention also finds its application in the interconnection of sandwiched circuit board assemblies where soft gold lead wires are inserted into axially aligned through-plated holes of the circuit boards and compressed so that the hold lead wires compress and buckle within the through-plated holes, forming an electrical connection between the circuit boards.
    Type: Grant
    Filed: May 21, 1987
    Date of Patent: October 8, 1991
    Assignee: Cray Computer Corporation
    Inventors: Seymour R. Cray, Nicholas J. Krajewski