By Metal Fusion Patents (Class 29/840)
  • Patent number: 11086307
    Abstract: A component mounting line control system controls a component mounting line. The component mounting line includes a component mounting device and a board retrieving unit. The component mounting line control system includes an acquirer and a controller. The acquirer acquires information from the board retrieving unit. The controller controls the component mounting device based on the information acquired by the acquirer. The controller lengthens a time taken for a manufacturing process in the component mounting device in a case where the acquirer acquires first warning information, which indicates that a board accommodation limit is about to be reached, from the board retrieving unit.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 10, 2021
    Inventor: Hiroyoshi Nishida
  • Patent number: 11081439
    Abstract: According to one embodiment, an integrated circuit includes a chip, a first pin, a second pin, and a third pin. The chip includes an internal circuit and a plurality of pads connected to the internal circuit. The first pin is connected to a first pad among the plurality of pads. The first pin is connected to a power supply provided outside the integrated circuit. The second pin is connected to a second pad among the plurality of pads. The second pin is connected to a ground provided outside the integrated circuit. The third pin is connected to the second pin inside the integrated circuit via a third pad among the plurality of pads. The third pin is insulated from the second pin outside the integrated circuit.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kentaro Watanabe
  • Patent number: 11075155
    Abstract: A package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface, at least one bonding electrode disposed on the first surface of the redistribution layer, and a mounting layer disposed on the second surface of the redistribution layer. The mounting layer includes a plurality of conductive pads that are spaced apart from each other. At least one of the conductive pads is exposed by the sidewall of the redistribution layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: July 27, 2021
    Assignee: InnoLux Corporation
    Inventors: Hsueh-Hsuan Chou, Chia-Chieh Fan, Cheng-Chi Wang, Kuan-Jen Wang
  • Patent number: 11062731
    Abstract: Approaches to pre-forming solder bumps, such as for use in electrically connecting a head slider and a suspension assembly for a hard disk drive, involves applying a height stabilizer plate over a shared solder paste applied over a substrate housing electrode pads, and reflowing the solder paste with the plate applied to create solder bumps electrically coupled to the pads. Use of such a plate functions to stabilize and contain the solder paste and create uniform solder bumps across the series of pads, where the plate may be composed of a heat-resistant and anti-solder-wetting material. The solder bump pre-forming techniques generally enable solder bonding of extremely small electrical interconnection pads.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Takuya Satoh, Yuhsuke Matsumoto, Hiroyasu Tsuchida, Kouji Takei
  • Patent number: 11053082
    Abstract: The invention relates to a method and an apparatus for handling piece goods (2) moved one after another being transported to a seizing range (4) of at least one manipulator (5). Hereby at least two transported piece goods (2) are seized, spatially separated from the closed formation (F) and brought into a specified relative first target position (P1) and/or target alignment in relation to the subsequent piece goods (2). There at least one of the piece goods (2) is released. The at least one second piece good (2) seized from the formation (F) is seized again and is brought into a specified relative second target position and/or target alignment that is spaced apart from the first target position (P1).
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 6, 2021
    Assignee: KRONES Aktiengesellschaft
    Inventors: Frank Winzinger, Johannes Kirzinger, Manuel Kollmuss
  • Patent number: 11029672
    Abstract: A manufacturing system includes a plurality of manufacturing facilities, a remote terminal, and a remote authority controller that controls authority of a remote operation from the remote terminal. When an error is detected in a first manufacturing facility out of the plurality of manufacturing facilities, the remote authority controller grants authority of a remote operation of a second manufacturing facility to the remote terminal. The second manufacturing facility causes the error and is other than the first manufacturing facility.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 8, 2021
    Inventor: Hideki Sumi
  • Patent number: 11018095
    Abstract: A semiconductor structure includes a plurality of devices, a molding disposed between the plurality of devices, and a RDL. Each of the plurality of devices includes a first surface disposed with a conductive structure. The molding includes a first surface coupled to the first surfaces of the plurality of devices. The RDL is disposed on the first surfaces of the plurality of devices and the first surface of the molding. The RDL includes a first portion directly over the first surface of the molding, a second portion directly over the first surfaces of the plurality of devices. A thickness of the first portion is greater than a thickness of the second portion.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 25, 2021
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Jui-Pin Hung
  • Patent number: 10998656
    Abstract: An electrical assembly for a motor vehicle transmission includes a printed circuit board (PCB), at least two contact surfaces, at least two contact elements, and a potting compound. The PCB has a component side and the two contact surfaces are arranged on the component side. The contact elements are each electrically connected by a PCB-side first end portion to one of the contact surfaces. The potting compound is arranged on the component side of the PCB, and the contact elements are partly embedded therein. The potting compound directly contacts the contact surfaces and the PCB-side end portions of the contact elements and covers the same. The contact elements protrude from the potting compound by second end portions facing away from the PCB. The electrical assembly includes a chip protection frame that protrudes outward from the potting compound and forms contact chambers for the second end portions of the contact elements.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 4, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Bernd-Guenter Sippel, Peter Zweigle, Helmut Deringer, Franco Zeleny, Uwe Katzenwadel, Jens Hoffmann
  • Patent number: 10971468
    Abstract: Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed on a substrate with contact pads aligned with channels on the substrate. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward the contact pads to obtain the automatic registration.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 6, 2021
    Inventors: Ankit Mahajan, Mikhail L. Pekurovsky, Matthew S. Stay, Daniel J. Theis, Ann M. Gilman, Shawn C. Dodds, Thomas J. Metzler, Matthew R. D. Smith, Roger W. Barton, Joseph E. Hernandez, Saagar A. Shah, Kara A. Meyers, James Zhu, Teresa M. Goeddel, Lyudmila A. Pekurovsky, Jonathan W. Kemling, Jeremy K. Larsen, Jessica Chiu, Kayla C. Niccum
  • Patent number: 10905006
    Abstract: A textile electronic device configured to be connected to a conductive zone of a textile, the device including: an electronic circuit; at least a first mechanical and electrical connection means configured to be connected to the conductive zone of a textile; a textile substrate having at least a second electrical connection means, the at least one second electrical connection means being electrically connected to the electronic circuit and to the at least one first mechanical and electrical connection means; and a flexible envelope totally or partially including said electronic circuit, the at least one first mechanical and electrical connection means and the textile substrate, the at least one first mechanical connection means and electric being at least partially accessible through the flexible envelope. Also, a manufacturing method of the textile electronic device.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 26, 2021
    Assignee: BIOSERENITY
    Inventors: Marion Gouthez, Marc Frouin
  • Patent number: 10895602
    Abstract: A state estimation device for a battery assembly including rechargeable batteries acquires battery information of each rechargeable battery, stores a battery model of the battery assembly including the battery information of a rechargeable battery, and estimates a battery state of the battery assembly based on the battery information of each rechargeable battery and the battery model. The state estimation unit estimates the battery state of the battery assembly based on the battery information of each rechargeable battery, uses the estimated battery states of the battery assembly as a state variable, and applies an optimum filter for performing optimization based on a distribution of a plurality of sample points to a state equation and an output equation included in the battery model to calculate a gain for correcting the state variable.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 19, 2021
    Inventors: Yosuke Sugiura, Naoshi Akamine
  • Patent number: 10867961
    Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Vijay K. Nair
  • Patent number: 10867878
    Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tsung-Ding Wang, An-Jhih Su, Chien Ling Hwang, Jung Wei Cheng, Hsin-Yu Pan, Chen-Hua Yu
  • Patent number: 10849238
    Abstract: One embodiment includes a method for manufacturing an electronic apparatus, including bonding an integrated circuit (IC) die to a substrate to form an IC package using a first reflow process, which causes the substrate to warp, reversibly connecting a lid with the IC package over the IC die so that the lid applies a force to the IC die, providing a printed circuit board (PCB) including an array of first contact pads, respectively disposing an array of bonding elements on an array of second contact pads of the substrate, placing the IC package on to the PCB with respective ones of the bonding elements contacting respective ones of the first contact pads, performing a second reflow process to apply heat to the bonding elements to bond the first contact pads with the second contact pads, and removing the lid from the IC package after the second reflow process.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 24, 2020
    Inventor: Yogev Buzaglo
  • Patent number: 10794779
    Abstract: Object: To provide a pressure sensor that can provide a reduced sensation of a foreign body and that has a good sensitivity to pressure from a low load region to a high load region. Resolution means: The pressure sensor includes a variable resistor and a plurality of electrodes. The variable resistor is made of an electrically conductive foam elastomer material. The electrically conductive foam elastomer material is a material imparted with electrical conductivity by dispersing electrically conductive fillers into an elastomer material and obtained by foaming the elastomer material. The plurality of electrodes are disposed at intervals from each other on one surface in contact with the variable resistor.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 6, 2020
    Inventors: Kazuki Yamada, Yasuo Kondo
  • Patent number: 10784421
    Abstract: A method of producing an optoelectronic component includes providing a carrier having an upper side; providing a mat configured as a fiber-matrix semifinished product and having a through-opening; arranging an optoelectronic semiconductor chip over the upper side of the carrier; arranging the mat over the upper side of the carrier such that the optoelectronic semiconductor chip is arranged in the opening of the mat; and compacting the mat to form a composite body including the mat and the optoelectronic semiconductor chip.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 22, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Boss, Tobias Gebuhr
  • Patent number: 10756039
    Abstract: The disclosure describes techniques for eliminating or reducing non-wet open (NWO) defect formation by using a low activity flux to prevent a solder paste from sticking to ball grid array (BGA) solder balls during reflow soldering. The low activity flux may be configured such that: i) it creates a barrier that prevents the solder paste from sticking to the solder balls of the BGA; and ii) it does not impede the formation of solder joints during reflow. In implementations, a solid coating of the low activity flux may be formed over balls of the BGA, and the BGA may then be bonded to a PCB during reflow. In implementations, the balls of a BGA may be dipped in a low-activity creamy or liquid flux prior to reflow. In some implementations, the flux may applied on a solder paste printed on pads of the PCB, followed by placement of a BGA.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: August 25, 2020
    Inventors: Fengying Zhou, Fen Chen, Ning-Cheng Lee
  • Patent number: 10730706
    Abstract: A hand for connector connection that grips a component including a main body component, a flexible board extending from the main body component, and a first connector disposed on the flexible board and connects the first connector to a second connector of a mount substrate includes a first gripping section that grips the main body component and a second gripping section that grips the first connector. The second gripping section includes a close contact surface brought into close contact with a back surface of the first connector and a suction pad that starts suction of the back surface of the first connector in a position further projecting than the close contact surface and is contracted to a position where the suction pad is disposed flush with the close contact surface in a sucked state.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Fanuc Corporation
    Inventor: Yoshio Motowaki
  • Patent number: 10605679
    Abstract: A pressure sensor is disclosed. The pressure sensor includes a common electrode, sensitized electrodes, mountain-shaped pressure-sensitive layers, and thin-film transistors. The common electrode is formed as a layer. The sensitized electrodes are arranged in a matrix opposing the common electrode. The mountain-shaped pressure-sensitive layers are respectively formed over the sensitized electrodes on a side close to the common electrode. The thin-film transistors are disposed to correspond to the sensitized electrodes on sides of the sensitized electrodes opposite to the common electrode.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 31, 2020
    Assignee: NISSHA CO., LTD.
    Inventor: Hideaki Nada
  • Patent number: 10573543
    Abstract: An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 25, 2020
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, Peter Scott Andrews
  • Patent number: 10515838
    Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 24, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10497708
    Abstract: A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 3, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: He Chen, Jin Wen Dong, Jifeng Zhu, Zi Qun Hua, Liang Xiao, Yong Qing Wang
  • Patent number: 10433430
    Abstract: A memory module card structure includes a main board, a plurality of adhesive layers and a plurality of conduction skirting boards. Two surfaces of the main board respectively are divided into a mounting section and an inserting section. The inserting section is formed with a binding region, and a soldering region having solder pads electrically connected to the mounting section. The conduction skirting boards are correspondingly fixed to the inserting section, and each has a rigid substrate and a plurality of conductive pads. The conductive pad has an outer contacting part disposed on an outer surface of the rigid substrate and an adapting part formed through the rigid substrate and connecting the outer contacting part. A part of the conductive pad correspondingly is soldered to the solder pad. A part of the rigid substrate is fixed connected to the binding region by the adhesive layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 1, 2019
    Inventor: Sung-Yu Chen
  • Patent number: 10381720
    Abstract: A matching network is integrated into a multilayer surface mount device containing an RFID integrated circuit to provide both an antenna and a matching network for the RFID integrated circuit in the ultra high frequency regime. The surface mount device may be mounted on a printed circuit board to provide RF and RFID functionality to the printed circuit board.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 13, 2019
    Assignee: NXP B.V.
    Inventors: Giuliano Manzi, Gerald Wiednig
  • Patent number: 10297478
    Abstract: An apparatus includes a product substrate having a transfer surface, and a semiconductor die defined, at least in part, by a first surface adjoined to a second surface that extends in a direction transverse to the first surface. The semiconductor die is disposed on the transfer surface of the product substrate such that at least a portion of the first surface is in contact with the transfer surface, and at least a portion of the second surface is embedded onto the product substrate, beneath a plane that extends across the transfer surface.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 21, 2019
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andrew Huska, Justin Wendt
  • Patent number: 10199297
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 5, 2019
    Inventors: Chun Song, Yi Zhong
  • Patent number: 10123430
    Abstract: Certain examples disclosed herein are directed to materials that are designed for use in interconnects of electrical devices such as, for example, printed circuit boards and solar cells. In certain examples, a two-step solder may be used to reduce stresses on the materials used in the production of the electrical devices.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: November 6, 2018
    Assignee: Alpha Assembly Solutions Inc.
    Inventors: Michael T. Marczi, Paul Koep, Michiel A. de Monchy, Martinus N Finke, Brian Lewis
  • Patent number: 10064293
    Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 28, 2018
    Inventors: Yutaro Kogawa, Mitsunori Sato, Yutaka Takezawa, Akitoshi Sakaue, Mitsutoshi Naito
  • Patent number: 9840305
    Abstract: A bicycle control device comprises a seat information generator and an assist controller. The seat information generator is configured to generate seat information. The assist controller is configured to control an assist actuator to assist a driving force of a bicycle based on the seat information.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: December 12, 2017
    Assignee: SHIMANO INC.
    Inventors: Yasuhiro Tsuchizawa, Hiroshi Matsuda
  • Patent number: 9704766
    Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 11, 2017
    Inventors: Sandeep Kumar Goel, Mill-Jer Wang, Chung-Sheng Yuan, Tom Chen, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee
  • Patent number: 9691734
    Abstract: A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: June 27, 2017
    Inventor: Brett Arnold Dunlap
  • Patent number: 9673162
    Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Scott M. Hayes, Scott D. Marshall, Mahesh K. Shah
  • Patent number: 9629241
    Abstract: A printed circuit board, a ball grid array package and a wiring method of a printed circuit board are provided. The printed circuit board comprises: a substrate, the substrate including a plurality of insulating layers stacked and a plurality of conductive layers disposed between adjacent insulating layers; a plurality of pads, disposed in a two-dimensional matrix on a surface of the substrate; and a plurality of via holes, disposed corresponding to each pad and running through the substrate and the corresponding pad. The ball grid array package according to an embodiment of the invention comprises the above-described printed circuit board.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 18, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Yue Wu
  • Patent number: 9610758
    Abstract: A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: April 4, 2017
    Assignee: General Electric Company
    Inventors: Charles Gerard Woychik, Raymond Albert Fillion
  • Patent number: 9532462
    Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: December 27, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yeong Uk Seo, Sung Woon Yoon, Jin Su Kim, Myoung Hwa Nam, Sang Myung Lee, Chi Hee Ahn
  • Patent number: 9524948
    Abstract: A package structure, comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die to the second die such that the first die and the second die are electrically connected; and at least one bonding wire, for electrically connecting the first die to the conductive units or the substrate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 20, 2016
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 9496297
    Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: November 15, 2016
    Assignee: Optiz, Inc.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 9449893
    Abstract: A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation portion. The resin portion includes first and second surfaces, which are opposed to each other and expand generally parallel to an imaginary plane; and a substrate is located on a first surface-side of the resin portion. The terminals project from the resin portion in a direction of the imaginary plane and are soldered onto the substrate. The heat dissipation portion is disposed on a second surface-side of the resin portion to release heat generated in the chip. One of the terminals is connected to the heat dissipation portion such that heat is transmitted from the one of the terminals to the heat dissipation portion.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: September 20, 2016
    Inventor: Shinsuke Oota
  • Patent number: 9446939
    Abstract: A functional element includes a first electrode section, a second electrode section, a first wiring line connected to the first electrode section, and a second wiring line connected to the second electrode section, the first wiring line is provided with at least one first intersecting section intersecting with a wiring line other than the second wiring line, the second wiring line includes at least one second intersecting section intersecting with a wiring line other than the first wiring line, and a difference between a number of the first intersecting sections and a number of the second intersecting sections satisfies a condition one of equal to and lower than 50% with respect to larger one of the number of the first intersecting sections and the number of the second intersecting sections.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: September 20, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Satoru Tanaka
  • Patent number: 9437791
    Abstract: Disclosed is a light emitting device package including a package body including at least one electrode pad disposed on a surface thereof, a light emitting device disposed on the package body, the light emitting device being electrically connected to the electrode pad through a wire, and a via hole electrode passing through the package body, wherein the wire forms a stitch on at least one of the light emitting device and the electrode pad, the light emitting device package further includes a bonding ball disposed on the stitch, and the via hole electrode non-overlaps the stitch and the bonding ball in a vertical direction.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 6, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Byung Mok Kim, Young Jin No, Bo Hee Kang, Hiroshi Kodaira
  • Patent number: 9425088
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Grant
    Filed: April 13, 2013
    Date of Patent: August 23, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Patent number: 9393633
    Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: July 19, 2016
    Inventors: Pascal P Blais, Paul F Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L Toutant, Alain A Warren
  • Patent number: 9398736
    Abstract: A mounting apparatus bonds an electrode of an electronic component and an electrode of a substrate with thermally fusible bond metal to mount the component on a substrate. The apparatus includes a heater base that moves on a path to and from the substrate, a bonding tool, a pedestal to hold the electronic component by vacuum. The bonding tool is heated with a ceramic heater in the heater base to thermally bond the electronic component retained on the pedestal. The bonding tool includes a cooling flow passage providing communication between the upper surface and a side surface of the pedestal. This offers the advantage of shortening the time for cooling during mounting of the electronic component.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 19, 2016
    Assignee: SHINKAWA LTD.
    Inventors: Satoru Nagai, Yukitaka Sonoda
  • Patent number: 9398700
    Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: July 19, 2016
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Charles G. Woychik, Michael Newman, Terrence Caskey
  • Patent number: 9385008
    Abstract: A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Helmut Kiendl, Horst Theuss, Michael Weber
  • Patent number: 9385014
    Abstract: A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: July 5, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Naomi Masuda
  • Patent number: 9379464
    Abstract: An adapter for connecting first and second modules in a device for handling notes of value. Also disclosed is a cover for such note handling device.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: June 28, 2016
    Assignee: Wincor Nixdorf International GmbH
    Inventor: Christian Fehrenbach
  • Patent number: 9368468
    Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 14, 2016
    Inventors: Michael A. Stuber, Stuart B. Molin, Mark Drucker, Peter Fowler
  • Patent number: 9305709
    Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: BlackBerry Limited
    Inventors: Ivoyl Koutsaroff, Mark Vandermeulen, Andrew Cervin-Lawry, Atin J. Patel
  • Patent number: 9301403
    Abstract: A cream solder obtained by kneading an Sn—Ag—Cu alloy together with a flux, wherein the Sn—Ag—Cu alloy includes a mixture of a first powdery alloy and a second powdery alloy, the first powdery alloy is represented by an Sn—Ag phase diagram having a solid-liquid coexistence region and has a given silver amount which is larger than that in the eutectic composition (3.5 wt. % silver), and the second powdery alloy has a silver amount which is that in the eutectic composition (3.5 wt. % silver) or which is close to that in the eutectic composition and is smaller than that in the first powdery alloy. This cream solder has excellent strength and thermal stability, and satisfactory bonding properties. It is based on an inexpensive Sn—Ag—Cu solder alloy. It is suitable for use as a high-temperature-side lead-free solder material conformable to temperature gradation bonding. Also provided is a method of soldering.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 29, 2016
    Inventors: Mitsuo Yamashita, Tomoaki Goto, Takeshi Asagi