By Metal Fusion Patents (Class 29/840)
  • Patent number: 10794779
    Abstract: Object: To provide a pressure sensor that can provide a reduced sensation of a foreign body and that has a good sensitivity to pressure from a low load region to a high load region. Resolution means: The pressure sensor includes a variable resistor and a plurality of electrodes. The variable resistor is made of an electrically conductive foam elastomer material. The electrically conductive foam elastomer material is a material imparted with electrical conductivity by dispersing electrically conductive fillers into an elastomer material and obtained by foaming the elastomer material. The plurality of electrodes are disposed at intervals from each other on one surface in contact with the variable resistor.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 6, 2020
    Inventors: Kazuki Yamada, Yasuo Kondo
  • Patent number: 10784421
    Abstract: A method of producing an optoelectronic component includes providing a carrier having an upper side; providing a mat configured as a fiber-matrix semifinished product and having a through-opening; arranging an optoelectronic semiconductor chip over the upper side of the carrier; arranging the mat over the upper side of the carrier such that the optoelectronic semiconductor chip is arranged in the opening of the mat; and compacting the mat to form a composite body including the mat and the optoelectronic semiconductor chip.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 22, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Boss, Tobias Gebuhr
  • Patent number: 10756039
    Abstract: The disclosure describes techniques for eliminating or reducing non-wet open (NWO) defect formation by using a low activity flux to prevent a solder paste from sticking to ball grid array (BGA) solder balls during reflow soldering. The low activity flux may be configured such that: i) it creates a barrier that prevents the solder paste from sticking to the solder balls of the BGA; and ii) it does not impede the formation of solder joints during reflow. In implementations, a solid coating of the low activity flux may be formed over balls of the BGA, and the BGA may then be bonded to a PCB during reflow. In implementations, the balls of a BGA may be dipped in a low-activity creamy or liquid flux prior to reflow. In some implementations, the flux may applied on a solder paste printed on pads of the PCB, followed by placement of a BGA.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: August 25, 2020
    Inventors: Fengying Zhou, Fen Chen, Ning-Cheng Lee
  • Patent number: 10730706
    Abstract: A hand for connector connection that grips a component including a main body component, a flexible board extending from the main body component, and a first connector disposed on the flexible board and connects the first connector to a second connector of a mount substrate includes a first gripping section that grips the main body component and a second gripping section that grips the first connector. The second gripping section includes a close contact surface brought into close contact with a back surface of the first connector and a suction pad that starts suction of the back surface of the first connector in a position further projecting than the close contact surface and is contracted to a position where the suction pad is disposed flush with the close contact surface in a sucked state.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Fanuc Corporation
    Inventor: Yoshio Motowaki
  • Patent number: 10605679
    Abstract: A pressure sensor is disclosed. The pressure sensor includes a common electrode, sensitized electrodes, mountain-shaped pressure-sensitive layers, and thin-film transistors. The common electrode is formed as a layer. The sensitized electrodes are arranged in a matrix opposing the common electrode. The mountain-shaped pressure-sensitive layers are respectively formed over the sensitized electrodes on a side close to the common electrode. The thin-film transistors are disposed to correspond to the sensitized electrodes on sides of the sensitized electrodes opposite to the common electrode.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 31, 2020
    Assignee: NISSHA CO., LTD.
    Inventor: Hideaki Nada
  • Patent number: 10573543
    Abstract: An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 25, 2020
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, Peter Scott Andrews
  • Patent number: 10515838
    Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 24, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10497708
    Abstract: A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 3, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: He Chen, Jin Wen Dong, Jifeng Zhu, Zi Qun Hua, Liang Xiao, Yong Qing Wang
  • Patent number: 10433430
    Abstract: A memory module card structure includes a main board, a plurality of adhesive layers and a plurality of conduction skirting boards. Two surfaces of the main board respectively are divided into a mounting section and an inserting section. The inserting section is formed with a binding region, and a soldering region having solder pads electrically connected to the mounting section. The conduction skirting boards are correspondingly fixed to the inserting section, and each has a rigid substrate and a plurality of conductive pads. The conductive pad has an outer contacting part disposed on an outer surface of the rigid substrate and an adapting part formed through the rigid substrate and connecting the outer contacting part. A part of the conductive pad correspondingly is soldered to the solder pad. A part of the rigid substrate is fixed connected to the binding region by the adhesive layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 1, 2019
    Inventor: Sung-Yu Chen
  • Patent number: 10381720
    Abstract: A matching network is integrated into a multilayer surface mount device containing an RFID integrated circuit to provide both an antenna and a matching network for the RFID integrated circuit in the ultra high frequency regime. The surface mount device may be mounted on a printed circuit board to provide RF and RFID functionality to the printed circuit board.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 13, 2019
    Assignee: NXP B.V.
    Inventors: Giuliano Manzi, Gerald Wiednig
  • Patent number: 10297478
    Abstract: An apparatus includes a product substrate having a transfer surface, and a semiconductor die defined, at least in part, by a first surface adjoined to a second surface that extends in a direction transverse to the first surface. The semiconductor die is disposed on the transfer surface of the product substrate such that at least a portion of the first surface is in contact with the transfer surface, and at least a portion of the second surface is embedded onto the product substrate, beneath a plane that extends across the transfer surface.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 21, 2019
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andrew Huska, Justin Wendt
  • Patent number: 10199297
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 5, 2019
    Inventors: Chun Song, Yi Zhong
  • Patent number: 10123430
    Abstract: Certain examples disclosed herein are directed to materials that are designed for use in interconnects of electrical devices such as, for example, printed circuit boards and solar cells. In certain examples, a two-step solder may be used to reduce stresses on the materials used in the production of the electrical devices.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: November 6, 2018
    Assignee: Alpha Assembly Solutions Inc.
    Inventors: Michael T. Marczi, Paul Koep, Michiel A. de Monchy, Martinus N Finke, Brian Lewis
  • Patent number: 10064293
    Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 28, 2018
    Inventors: Yutaro Kogawa, Mitsunori Sato, Yutaka Takezawa, Akitoshi Sakaue, Mitsutoshi Naito
  • Patent number: 9840305
    Abstract: A bicycle control device comprises a seat information generator and an assist controller. The seat information generator is configured to generate seat information. The assist controller is configured to control an assist actuator to assist a driving force of a bicycle based on the seat information.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: December 12, 2017
    Assignee: SHIMANO INC.
    Inventors: Yasuhiro Tsuchizawa, Hiroshi Matsuda
  • Patent number: 9704766
    Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 11, 2017
    Inventors: Sandeep Kumar Goel, Mill-Jer Wang, Chung-Sheng Yuan, Tom Chen, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee
  • Patent number: 9691734
    Abstract: A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: June 27, 2017
    Inventor: Brett Arnold Dunlap
  • Patent number: 9673162
    Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Scott M. Hayes, Scott D. Marshall, Mahesh K. Shah
  • Patent number: 9629241
    Abstract: A printed circuit board, a ball grid array package and a wiring method of a printed circuit board are provided. The printed circuit board comprises: a substrate, the substrate including a plurality of insulating layers stacked and a plurality of conductive layers disposed between adjacent insulating layers; a plurality of pads, disposed in a two-dimensional matrix on a surface of the substrate; and a plurality of via holes, disposed corresponding to each pad and running through the substrate and the corresponding pad. The ball grid array package according to an embodiment of the invention comprises the above-described printed circuit board.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 18, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Yue Wu
  • Patent number: 9610758
    Abstract: A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: April 4, 2017
    Assignee: General Electric Company
    Inventors: Charles Gerard Woychik, Raymond Albert Fillion
  • Patent number: 9532462
    Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: December 27, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yeong Uk Seo, Sung Woon Yoon, Jin Su Kim, Myoung Hwa Nam, Sang Myung Lee, Chi Hee Ahn
  • Patent number: 9524948
    Abstract: A package structure, comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die to the second die such that the first die and the second die are electrically connected; and at least one bonding wire, for electrically connecting the first die to the conductive units or the substrate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 20, 2016
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 9496297
    Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: November 15, 2016
    Assignee: Optiz, Inc.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 9449893
    Abstract: A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation portion. The resin portion includes first and second surfaces, which are opposed to each other and expand generally parallel to an imaginary plane; and a substrate is located on a first surface-side of the resin portion. The terminals project from the resin portion in a direction of the imaginary plane and are soldered onto the substrate. The heat dissipation portion is disposed on a second surface-side of the resin portion to release heat generated in the chip. One of the terminals is connected to the heat dissipation portion such that heat is transmitted from the one of the terminals to the heat dissipation portion.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: September 20, 2016
    Inventor: Shinsuke Oota
  • Patent number: 9446939
    Abstract: A functional element includes a first electrode section, a second electrode section, a first wiring line connected to the first electrode section, and a second wiring line connected to the second electrode section, the first wiring line is provided with at least one first intersecting section intersecting with a wiring line other than the second wiring line, the second wiring line includes at least one second intersecting section intersecting with a wiring line other than the first wiring line, and a difference between a number of the first intersecting sections and a number of the second intersecting sections satisfies a condition one of equal to and lower than 50% with respect to larger one of the number of the first intersecting sections and the number of the second intersecting sections.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: September 20, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Satoru Tanaka
  • Patent number: 9437791
    Abstract: Disclosed is a light emitting device package including a package body including at least one electrode pad disposed on a surface thereof, a light emitting device disposed on the package body, the light emitting device being electrically connected to the electrode pad through a wire, and a via hole electrode passing through the package body, wherein the wire forms a stitch on at least one of the light emitting device and the electrode pad, the light emitting device package further includes a bonding ball disposed on the stitch, and the via hole electrode non-overlaps the stitch and the bonding ball in a vertical direction.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 6, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Byung Mok Kim, Young Jin No, Bo Hee Kang, Hiroshi Kodaira
  • Patent number: 9425088
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Grant
    Filed: April 13, 2013
    Date of Patent: August 23, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Patent number: 9398700
    Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: July 19, 2016
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Charles G. Woychik, Michael Newman, Terrence Caskey
  • Patent number: 9398736
    Abstract: A mounting apparatus bonds an electrode of an electronic component and an electrode of a substrate with thermally fusible bond metal to mount the component on a substrate. The apparatus includes a heater base that moves on a path to and from the substrate, a bonding tool, a pedestal to hold the electronic component by vacuum. The bonding tool is heated with a ceramic heater in the heater base to thermally bond the electronic component retained on the pedestal. The bonding tool includes a cooling flow passage providing communication between the upper surface and a side surface of the pedestal. This offers the advantage of shortening the time for cooling during mounting of the electronic component.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 19, 2016
    Assignee: SHINKAWA LTD.
    Inventors: Satoru Nagai, Yukitaka Sonoda
  • Patent number: 9393633
    Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: July 19, 2016
    Inventors: Pascal P Blais, Paul F Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L Toutant, Alain A Warren
  • Patent number: 9385014
    Abstract: A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: July 5, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Naomi Masuda
  • Patent number: 9385008
    Abstract: A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Helmut Kiendl, Horst Theuss, Michael Weber
  • Patent number: 9379464
    Abstract: An adapter for connecting first and second modules in a device for handling notes of value. Also disclosed is a cover for such note handling device.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: June 28, 2016
    Assignee: Wincor Nixdorf International GmbH
    Inventor: Christian Fehrenbach
  • Patent number: 9368468
    Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 14, 2016
    Inventors: Michael A. Stuber, Stuart B. Molin, Mark Drucker, Peter Fowler
  • Patent number: 9305709
    Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: BlackBerry Limited
    Inventors: Ivoyl Koutsaroff, Mark Vandermeulen, Andrew Cervin-Lawry, Atin J. Patel
  • Patent number: 9301403
    Abstract: A cream solder obtained by kneading an Sn—Ag—Cu alloy together with a flux, wherein the Sn—Ag—Cu alloy includes a mixture of a first powdery alloy and a second powdery alloy, the first powdery alloy is represented by an Sn—Ag phase diagram having a solid-liquid coexistence region and has a given silver amount which is larger than that in the eutectic composition (3.5 wt. % silver), and the second powdery alloy has a silver amount which is that in the eutectic composition (3.5 wt. % silver) or which is close to that in the eutectic composition and is smaller than that in the first powdery alloy. This cream solder has excellent strength and thermal stability, and satisfactory bonding properties. It is based on an inexpensive Sn—Ag—Cu solder alloy. It is suitable for use as a high-temperature-side lead-free solder material conformable to temperature gradation bonding. Also provided is a method of soldering.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 29, 2016
    Inventors: Mitsuo Yamashita, Tomoaki Goto, Takeshi Asagi
  • Patent number: 9287157
    Abstract: A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 15, 2016
    Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
  • Patent number: 9287232
    Abstract: The invention relates to a method for producing a connection between a semiconductor component and semiconductor component and semiconductor module resistant to high temperatures and temperature changes by means of a temperature impinging process, wherein a metal powder suspension is applied to the areas of the semiconductor module to be connected later; the suspension layer is dried, outgassing the volatile components and generating a porous layer; the porous layer is pre-sealed without complete sintering taking place throughout the suspension layer; and, in order to obtain a solid electrically and thermally conductive connection of a semiconductor module to a connection partner from the group of: substrate, further semiconductor or interconnect device, the connection is a sintered connection generated without compression by increasing the temperature and made of a dried metal powder suspension that has undergone a first transport-safe contact with the connection partner in a pre-compression step and has bee
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: March 15, 2016
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Mathias Kock, Ronald Eisele
  • Patent number: 9275961
    Abstract: A low-cost high-frequency electronic device package and associated fabrication method are described wherein waveguide structures are formed from the high frequency device to the package lead transition. The package lead transition is optimized to take advantage of waveguide interconnect structure.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 1, 2016
    Assignee: Rosenberger Hochfrequenztechnik GmbH & Co. KG
    Inventors: Eric A. Sanjuan, Sean S. Cahill
  • Patent number: 9230933
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 5, 2016
    Assignee: STATS ChipPac, Ltd
    Inventors: JaeHyun Lee, KyungHoon Lee, SeongWon Park, KiYoun Jang
  • Patent number: 9232658
    Abstract: This publication discloses a method for manufacturing an electronic module, in which manufacture commences from an insulating-material sheet (1). At least one recess (2) is made in the sheet (1) and extends through the insulating-material layer (1) as far as the conductive layer on the opposite surface (1a). A component (6) is set in the recess, with its contact surface towards the conductive layer and the component (6) is attached to the conductive layer. After this, a conductive pattern (14) is formed from the conductive pattern closing the recess, which is electrically connected from at least some of the contact areas or contact protrusions of the component (6) set in the recess.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: January 5, 2016
    Assignee: GE Embedded Electronics Oy
    Inventors: Antti Iihola, Timo Jokela
  • Patent number: 9212588
    Abstract: An exhaust gas treatment device (1), which contains at least one exhaust gas treatment insert (2) in a tubular housing (4), especially for an exhaust system of an internal combustion engine. A circumferential geometry of the at least one insert (2) is measured in at least one axial section of the particular insert (2). The at least one insert (2) is inserted axially into the housing (4). The measured circumferential geometry of the at least one insert (2) is taken into account during the deformation of the housing (4).
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: December 15, 2015
    Assignee: Eberspächer Exhaust Technology GmbH & Co. KG
    Inventor: Georg Wirth
  • Patent number: 9202769
    Abstract: A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: December 1, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim
  • Patent number: 9198277
    Abstract: A height of a signal transmission device is decreased as low as possible as maintaining or improving a cooling performance for the communication module. Ina signal transmission device provided with a communication module provided on a substrate and a cooling mechanism for cooling the communication module, the cooling mechanism includes: a heat-transfer plate including a first region which overlaps with bottom surfaces of a plurality of the communication modules and is thermally connected to the bottom surfaces and a second region which does not overlap with the bottom surfaces of the communication modules; and a heat-release fin provided in the second region of the heat-transfer plate.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: November 24, 2015
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yoshinori Sunaga, Yoshiaki Ishigami, Hidetaka Kawauchi, Hidenori Yonezawa, Kinya Yamazaki
  • Patent number: 9190384
    Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: November 17, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
  • Patent number: 9184103
    Abstract: A semiconductor device includes a first conductive layer and conductive pillars disposed over the first conductive layer and directly contacting the first conductive layer. The semiconductor device includes an Integrated Passive Device (IPD) mounted to the first conductive layer such that the IPD is disposed between the conductive pillars. The IPD is self-aligned to the first conductive layer, and includes a metal-insulator-metal capacitor disposed over a first substrate and a wound conductive layer forming an inductor disposed over the first substrate. The semiconductor device includes a discrete capacitor mounted over the first conductive layer. The discrete capacitor is electrically connected to one of the conductive pillars. The semiconductor device includes an encapsulant disposed around the IPD, discrete capacitor, and conductive pillars, a first insulation layer disposed over the encapsulant and conductive pillars, and a second conductive layer disposed over the first insulating layer.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Kang Chen, Jianmin Fang
  • Patent number: 9171797
    Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye
  • Patent number: 9173315
    Abstract: A package carrier enclosing at least one microelectronic element has a pattern of electrically conductive connection pads for electric connection of the microelectronic element to the package carrier. The package carrier is manufactured by providing a sacrificial carrier; applying an electrically conductive pattern to one side of the carrier; bending the carrier to create a shape having an elevated portion and a recessed portion; forming a body member on the carrier at the side where the electrically conductive pattern is present; removing the sacrificial carrier; and placing a microelectronic element in a recess created in the body member at the position where the elevated portion of the carrier has been, and connecting the microelectronic element to the electrically conductive pattern. Furthermore, a hole in the package provides access to a sensitive surface of the microelectronic element.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 27, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Johannes Wilhelmus Weekamp, Antonius Constant Johanna Cornelis Van Den Ackerveken, Will J. H. Ansems
  • Patent number: 9171882
    Abstract: According to one embodiment, a semiconductor light emitting device includes a plurality of chips, a first insulating layer provided between the chips, one p-side external terminal, and one n-side external terminal. Each of the chips includes a semiconductor layer, a p-side electrode, and an n-side electrode. Each of the chips is separated from each other. The one p-side external terminal is provided corresponding to one chip on the second face side. The p-side external terminal is electrically connected to the p-side electrode. The one n-side external terminal is provided corresponding to one chip on the second face side. The n-side external terminal is electrically connected to the n-side electrode.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Akimoto, Yoshiaki Sugizaki, Akihiro Kojima, Kazuhito Higuchi, Hideo Nishiuchi, Susumu Obata
  • Patent number: 9158078
    Abstract: The semiconductor laser module (1) includes: a laser mount (31) having thereon a semiconductor laser chip (32); a fiber mount (40) having thereon an optical fiber (2); a submount (20) on which the laser mount (31) and the fiber mount (40) are placed; and a substrate (10) on which the submount 20 is placed, the substrate (10) having protrusions (11a to 11d) on a top surface thereof, the submount 20 being joined to the substrate (10) with a soft solder (61) spread between the submount (20) and the substrate (10).
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 13, 2015
    Assignee: FUJIKURA LTD.
    Inventors: Nozomu Toyohara, Akira Sakamoto, Yohei Kasai