By Metal Fusion Patents (Class 29/840)
  • Patent number: 11510350
    Abstract: The unloading operation of winding the carrier tape on the component supply reel by driving the component supply reel to extract the component supply reel from the tape feeder is performed. That is, the carrier tape removed from the tape feeder is wound on the component supply reel. Thus, it is possible to suppress the interference of the preceding tape removed from the tape feeder with the succeeding tape.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 22, 2022
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventor: Yuzuru Taniguchi
  • Patent number: 11456259
    Abstract: Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: September 27, 2022
    Assignee: PYXIS CF PTE. LTD.
    Inventor: Amlan Sen
  • Patent number: 11445615
    Abstract: The present invention relates to a touch sensor module and an image display device including the same. The touch sensor module includes a touch sensor including pad portions, a flexible printed circuit board (FPCB) including terminal portions, and a solder joint interposed between the touch sensor and the flexible printed circuit board, in which the solder joint includes a solder paste including solder balls and a flux, the pad portions and the terminal portions are electrically connected through the solder balls compressed by heating and pressing, the flux is used in an amount of 5 to 40 wt % based on the total weight of the solder paste, and the ratio of the diameter of the solder balls included in the solder paste to the gap between the pad portions of the touch sensor and the terminal portions of the flexible printed circuit board is 1:0.2-0.6.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 13, 2022
    Assignee: Dongwoo Fine-Chem Co., Ltd.
    Inventors: Jun-Ha Kim, Dong-Jin Son
  • Patent number: 11412620
    Abstract: The invention relates to a process for manufacturing a roll of flexible carrier bearing electronic components. This process includes a step consisting in adding, to this flexible carrier, electronic components, themselves manufactured from a roll of flexible initial substrate. For example, the electronic components may be manufactured on an initial substrate having a width allowing advantage to be taken of densification of the manufacture of the components on this initial substrate. Subsequently, the singulated electronic components are added to the flexible carrier, allowing, for example, packaging that is more suitable, than possible with the initial substrate, to a use of the electronic components, notably when the latter must be integrated into a chip-card. Thus, for example, the flexible carrier may be, or include, an adhesive, which may or may not be conductive, and which is used to fasten, and optionally connect, each electronic component to a chip-card.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 9, 2022
    Assignee: Linxens Holding
    Inventor: Christophe Mathieu
  • Patent number: 11395448
    Abstract: Provided is a method for the throughput-optimised production of printed circuit boards on least two assembly lines, wherein: the printed circuit boards are divided into clusters; each cluster is produced using a set-up system that is carried out by changeover tables that can be attached to the assembly line, each changeover table having at least one feed device for keeping ready stocks of components; and a changeover table set and an empty changeover table set comprises changeover tables with feed devices that are empty.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 19, 2022
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Alexander Pfaffinger, Christian Royer
  • Patent number: 11392241
    Abstract: An electrode connection structure includes a substrate layer, a plurality of pads on the substrate layer, and an insulation layer at least partially covering the substrate layer and the pads. The insulation layer includes a plurality of holes on the pads and at least one first groove line extending between the pads neighboring each other.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 19, 2022
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Byung Jin Choi, Jae Hyun Lee
  • Patent number: 11380816
    Abstract: Embodiments relate to mass-transfer methods useful for fabricating products containing Light Emitting Diode (LED) structures. LED arrays are transferred from a source substrate to a target substrate by an in-process functional test Known-Good Die (KGD) driven mass-transfer of a plurality of LED devices in a high-speed flexible manner. Certain preferred embodiments using beam-addressed release (BAR) mass-transfer approaches are able to utilize a Known Good Die (KGD) data file of the source substrate in a manner that avoids additional steps, rework and yield losses.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 5, 2022
    Assignee: Apple Inc.
    Inventor: Francois J. Henley
  • Patent number: 11373976
    Abstract: A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 28, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Nathan P. Lower, Haley M. Steffen, Ross K. Wilcoxon, David L. Westergren, Brian K. Otis, Pete Sahayda
  • Patent number: 11355443
    Abstract: Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 7, 2022
    Assignee: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Patent number: 11330750
    Abstract: An electronic component mounting device including a component holding device to hold and mount on a board an electronic component supplied by a component supply device; a motor to drive the component holding device; a motor control device to control the motor; a load measurement device to measure a load applied from the component holding device upon being pressed by the component holding device while the component holding device performs the same operation as when mounting an electronic component on a board, by replacing the board with the load measurement device; a motor information acquisition section to obtain motor information corresponding to the force with which the motor drives the component holding device in the pressing direction against the load measurement device while the motor control device performs the same operation as when mounting an electronic component on the board, by replacing the board with the load measurement device.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 10, 2022
    Assignee: FUJI CORPORATION
    Inventor: Naohiro Kato
  • Patent number: 11315879
    Abstract: A package substrate, including a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, and a second wiring layer disposed on the first insulating layer, and a multi-chip package, including the package substrate, are provided.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Je Ji, Tae Seong Kim
  • Patent number: 11302610
    Abstract: In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
  • Patent number: 11295972
    Abstract: The present disclosure provides a method for transfer and assembly of RGB micro-light-emitting diodes using vacuum suction force whereby the vacuum state of micrometer-sized adsorption holes to which micro-light-emitting diodes formed on a mother substrate or a temporary substrate are bonded is controlled selectively, so that only the micro-light-emitting diode devices desired to be detached from the mother substrate or the temporary substrate are detached from the mother substrate or the temporary substrate using vacuum suction force and then transferred to a target substrate.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 5, 2022
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Keon Jae Lee, Han Eol Lee, Tae Jin Kim, Jung Ho Shin, Sang Hyun Park
  • Patent number: 11276666
    Abstract: A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 15, 2022
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Ivy Wei Qin, Ray L. Cathcart, Cuong Huynh, Deepak Sood, Paul W. Sucro, Joseph O. DeAngelo
  • Patent number: 11264349
    Abstract: A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jungbae Lee
  • Patent number: 11259406
    Abstract: A flexible connector comprises a first plurality of pads disposed within an integrated circuit (IC) area, a second plurality of pads disposed in the IC area, and a plurality of through holes disposed in the IC area. The flexible connector further comprises first wiring coupled to the plurality of through holes and the first plurality of pads, and a rigidity element at least partially disposed between the plurality of through holes and the second plurality of pads.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 22, 2022
    Assignee: Synaptics Incorporated
    Inventors: Shinya Suzuki, Naoyuki Narita, Tsuyoshi Koga, Yuichi Nakagomi
  • Patent number: 11239146
    Abstract: A package structure is provided. The package structure includes a substrate. The package structure also includes a hybrid pad disposed on the substrate. The hybrid pad includes a metal layer and a buffer layer connected to the metal layer. The Young's modulus of the buffer layer is less than the Young's modulus of the metal layer. The package structure further includes an electrically connecting structure disposed on the hybrid pad. The package structure includes a chip layer electrically connected to the electrically connecting structure. The package structure also includes a bonding pad disposed between the electrically connecting structure and the chip layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: February 1, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Chih-Ming Shen
  • Patent number: 11217576
    Abstract: Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Quang Nguyen, Christopher Glancey, Shams U Arifeen, Koustav Sinha
  • Patent number: 11211332
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 28, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal
  • Patent number: 11211322
    Abstract: A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a surface of a printed wiring board. The surface of the package substrate and the surface of the printed wiring board face each other. The plurality of lands and another plurality of lands are bonded to each other with solder having a height of 30% or less of a diameter of a solder bonding portion at the corresponding land. A ratio of a solder bonded area of at least each of lands, among another plurality of the lands, of which distance value to a corresponding one of the lands is larger than an average distance value between the lands and another lands, to a solder bonded area of the corresponding one of the lands is 56% or more and 81% or less.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 28, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kunihiko Minegishi
  • Patent number: 11201200
    Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Sheng-Yu Chen, Chang-Lin Yeh, Yung-I Yeh
  • Patent number: 11184975
    Abstract: According to one embodiment is a flexible circuit comprising a flexible base, a conductive polymer supported by the base, and an integrated circuit component having an elongated electrical contact, wherein the elongated electrical contact penetrates into the conductive polymer, thereby providing a robust electrical connection. According to methods of certain embodiments, the flexible circuit is manufactured using a molding process, where a conductive polymer is deposited into recesses in a mold, integrated circuit components are placed in contact with the conductive polymer, and a flexible polymer base is poured over the mold prior to curing. In an alternative embodiment, a multiple-layer flexible circuit is manufacturing using a plurality of molds.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 23, 2021
    Assignee: CARNEGIE MELLON UNIVERSITY
    Inventors: Alexandros Charalambides, Carmel Majidi
  • Patent number: 11163124
    Abstract: Compact ASIC, chip-on-board, flip-chip, interposer, and related packaging techniques are incorporated to minimize the footprint of optoelectronic interconnect devices, including the Optical Data Pipe. In addition, ruggedized packaging techniques are incorporated to increase the durability and application space for optoelectronic interconnect devices, including an Optical Data Pipe.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 2, 2021
    Assignee: Wavefront Research, Inc.
    Inventors: Randall C. Veitch, Thomas W. Stone
  • Patent number: 11152315
    Abstract: An electronic device package includes a first conductive substrate, a second conductive substrate and a dielectric layer. The first conductive substrate has a first coefficient of thermal expansion (CTE). The second conductive substrate is disposed on an upper surface of the first conductive substrate and electrically connected to the first conductive substrate. The second conductive substrate has a second CTE. The dielectric layer is disposed on the upper surface of the first conductive substrate and disposed on at least one sidewall of the second conductive substrate. The dielectric layer has a third CTE. A difference between the first CTE and the second CTE is larger than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 19, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Tung Chang, Cheng-Nan Lin
  • Patent number: 11086307
    Abstract: A component mounting line control system controls a component mounting line. The component mounting line includes a component mounting device and a board retrieving unit. The component mounting line control system includes an acquirer and a controller. The acquirer acquires information from the board retrieving unit. The controller controls the component mounting device based on the information acquired by the acquirer. The controller lengthens a time taken for a manufacturing process in the component mounting device in a case where the acquirer acquires first warning information, which indicates that a board accommodation limit is about to be reached, from the board retrieving unit.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 10, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Hiroyoshi Nishida
  • Patent number: 11081439
    Abstract: According to one embodiment, an integrated circuit includes a chip, a first pin, a second pin, and a third pin. The chip includes an internal circuit and a plurality of pads connected to the internal circuit. The first pin is connected to a first pad among the plurality of pads. The first pin is connected to a power supply provided outside the integrated circuit. The second pin is connected to a second pad among the plurality of pads. The second pin is connected to a ground provided outside the integrated circuit. The third pin is connected to the second pin inside the integrated circuit via a third pad among the plurality of pads. The third pin is insulated from the second pin outside the integrated circuit.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kentaro Watanabe
  • Patent number: 11075155
    Abstract: A package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface, at least one bonding electrode disposed on the first surface of the redistribution layer, and a mounting layer disposed on the second surface of the redistribution layer. The mounting layer includes a plurality of conductive pads that are spaced apart from each other. At least one of the conductive pads is exposed by the sidewall of the redistribution layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: July 27, 2021
    Assignee: InnoLux Corporation
    Inventors: Hsueh-Hsuan Chou, Chia-Chieh Fan, Cheng-Chi Wang, Kuan-Jen Wang
  • Patent number: 11062731
    Abstract: Approaches to pre-forming solder bumps, such as for use in electrically connecting a head slider and a suspension assembly for a hard disk drive, involves applying a height stabilizer plate over a shared solder paste applied over a substrate housing electrode pads, and reflowing the solder paste with the plate applied to create solder bumps electrically coupled to the pads. Use of such a plate functions to stabilize and contain the solder paste and create uniform solder bumps across the series of pads, where the plate may be composed of a heat-resistant and anti-solder-wetting material. The solder bump pre-forming techniques generally enable solder bonding of extremely small electrical interconnection pads.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Takuya Satoh, Yuhsuke Matsumoto, Hiroyasu Tsuchida, Kouji Takei
  • Patent number: 11053082
    Abstract: The invention relates to a method and an apparatus for handling piece goods (2) moved one after another being transported to a seizing range (4) of at least one manipulator (5). Hereby at least two transported piece goods (2) are seized, spatially separated from the closed formation (F) and brought into a specified relative first target position (P1) and/or target alignment in relation to the subsequent piece goods (2). There at least one of the piece goods (2) is released. The at least one second piece good (2) seized from the formation (F) is seized again and is brought into a specified relative second target position and/or target alignment that is spaced apart from the first target position (P1).
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 6, 2021
    Assignee: KRONES Aktiengesellschaft
    Inventors: Frank Winzinger, Johannes Kirzinger, Manuel Kollmuss
  • Patent number: 11029672
    Abstract: A manufacturing system includes a plurality of manufacturing facilities, a remote terminal, and a remote authority controller that controls authority of a remote operation from the remote terminal. When an error is detected in a first manufacturing facility out of the plurality of manufacturing facilities, the remote authority controller grants authority of a remote operation of a second manufacturing facility to the remote terminal. The second manufacturing facility causes the error and is other than the first manufacturing facility.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 8, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Hideki Sumi
  • Patent number: 11018095
    Abstract: A semiconductor structure includes a plurality of devices, a molding disposed between the plurality of devices, and a RDL. Each of the plurality of devices includes a first surface disposed with a conductive structure. The molding includes a first surface coupled to the first surfaces of the plurality of devices. The RDL is disposed on the first surfaces of the plurality of devices and the first surface of the molding. The RDL includes a first portion directly over the first surface of the molding, a second portion directly over the first surfaces of the plurality of devices. A thickness of the first portion is greater than a thickness of the second portion.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Jui-Pin Hung
  • Patent number: 10998656
    Abstract: An electrical assembly for a motor vehicle transmission includes a printed circuit board (PCB), at least two contact surfaces, at least two contact elements, and a potting compound. The PCB has a component side and the two contact surfaces are arranged on the component side. The contact elements are each electrically connected by a PCB-side first end portion to one of the contact surfaces. The potting compound is arranged on the component side of the PCB, and the contact elements are partly embedded therein. The potting compound directly contacts the contact surfaces and the PCB-side end portions of the contact elements and covers the same. The contact elements protrude from the potting compound by second end portions facing away from the PCB. The electrical assembly includes a chip protection frame that protrudes outward from the potting compound and forms contact chambers for the second end portions of the contact elements.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 4, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Bernd-Guenter Sippel, Peter Zweigle, Helmut Deringer, Franco Zeleny, Uwe Katzenwadel, Jens Hoffmann
  • Patent number: 10971468
    Abstract: Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed on a substrate with contact pads aligned with channels on the substrate. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward the contact pads to obtain the automatic registration.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 6, 2021
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ankit Mahajan, Mikhail L. Pekurovsky, Matthew S. Stay, Daniel J. Theis, Ann M. Gilman, Shawn C. Dodds, Thomas J. Metzler, Matthew R. D. Smith, Roger W. Barton, Joseph E. Hernandez, Saagar A. Shah, Kara A. Meyers, James Zhu, Teresa M. Goeddel, Lyudmila A. Pekurovsky, Jonathan W. Kemling, Jeremy K. Larsen, Jessica Chiu, Kayla C. Niccum
  • Patent number: 10905006
    Abstract: A textile electronic device configured to be connected to a conductive zone of a textile, the device including: an electronic circuit; at least a first mechanical and electrical connection means configured to be connected to the conductive zone of a textile; a textile substrate having at least a second electrical connection means, the at least one second electrical connection means being electrically connected to the electronic circuit and to the at least one first mechanical and electrical connection means; and a flexible envelope totally or partially including said electronic circuit, the at least one first mechanical and electrical connection means and the textile substrate, the at least one first mechanical connection means and electric being at least partially accessible through the flexible envelope. Also, a manufacturing method of the textile electronic device.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 26, 2021
    Assignee: BIOSERENITY
    Inventors: Marion Gouthez, Marc Frouin
  • Patent number: 10895602
    Abstract: A state estimation device for a battery assembly including rechargeable batteries acquires battery information of each rechargeable battery, stores a battery model of the battery assembly including the battery information of a rechargeable battery, and estimates a battery state of the battery assembly based on the battery information of each rechargeable battery and the battery model. The state estimation unit estimates the battery state of the battery assembly based on the battery information of each rechargeable battery, uses the estimated battery states of the battery assembly as a state variable, and applies an optimum filter for performing optimization based on a distribution of a plurality of sample points to a state equation and an output equation included in the battery model to calculate a gain for correcting the state variable.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 19, 2021
    Assignee: PRIMEARTH EV ENERGY CO., LTD.
    Inventors: Yosuke Sugiura, Naoshi Akamine
  • Patent number: 10867878
    Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tsung-Ding Wang, An-Jhih Su, Chien Ling Hwang, Jung Wei Cheng, Hsin-Yu Pan, Chen-Hua Yu
  • Patent number: 10867961
    Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Vijay K. Nair
  • Patent number: 10849238
    Abstract: One embodiment includes a method for manufacturing an electronic apparatus, including bonding an integrated circuit (IC) die to a substrate to form an IC package using a first reflow process, which causes the substrate to warp, reversibly connecting a lid with the IC package over the IC die so that the lid applies a force to the IC die, providing a printed circuit board (PCB) including an array of first contact pads, respectively disposing an array of bonding elements on an array of second contact pads of the substrate, placing the IC package on to the PCB with respective ones of the bonding elements contacting respective ones of the first contact pads, performing a second reflow process to apply heat to the bonding elements to bond the first contact pads with the second contact pads, and removing the lid from the IC package after the second reflow process.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 24, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventor: Yogev Buzaglo
  • Patent number: 10794779
    Abstract: Object: To provide a pressure sensor that can provide a reduced sensation of a foreign body and that has a good sensitivity to pressure from a low load region to a high load region. Resolution means: The pressure sensor includes a variable resistor and a plurality of electrodes. The variable resistor is made of an electrically conductive foam elastomer material. The electrically conductive foam elastomer material is a material imparted with electrical conductivity by dispersing electrically conductive fillers into an elastomer material and obtained by foaming the elastomer material. The plurality of electrodes are disposed at intervals from each other on one surface in contact with the variable resistor.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 6, 2020
    Assignee: KITAGAWA INDUSTRIES CO., LTD.
    Inventors: Kazuki Yamada, Yasuo Kondo
  • Patent number: 10784421
    Abstract: A method of producing an optoelectronic component includes providing a carrier having an upper side; providing a mat configured as a fiber-matrix semifinished product and having a through-opening; arranging an optoelectronic semiconductor chip over the upper side of the carrier; arranging the mat over the upper side of the carrier such that the optoelectronic semiconductor chip is arranged in the opening of the mat; and compacting the mat to form a composite body including the mat and the optoelectronic semiconductor chip.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 22, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Boss, Tobias Gebuhr
  • Patent number: 10756039
    Abstract: The disclosure describes techniques for eliminating or reducing non-wet open (NWO) defect formation by using a low activity flux to prevent a solder paste from sticking to ball grid array (BGA) solder balls during reflow soldering. The low activity flux may be configured such that: i) it creates a barrier that prevents the solder paste from sticking to the solder balls of the BGA; and ii) it does not impede the formation of solder joints during reflow. In implementations, a solid coating of the low activity flux may be formed over balls of the BGA, and the BGA may then be bonded to a PCB during reflow. In implementations, the balls of a BGA may be dipped in a low-activity creamy or liquid flux prior to reflow. In some implementations, the flux may applied on a solder paste printed on pads of the PCB, followed by placement of a BGA.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: August 25, 2020
    Assignee: INDIUM CORPORATION
    Inventors: Fengying Zhou, Fen Chen, Ning-Cheng Lee
  • Patent number: 10730706
    Abstract: A hand for connector connection that grips a component including a main body component, a flexible board extending from the main body component, and a first connector disposed on the flexible board and connects the first connector to a second connector of a mount substrate includes a first gripping section that grips the main body component and a second gripping section that grips the first connector. The second gripping section includes a close contact surface brought into close contact with a back surface of the first connector and a suction pad that starts suction of the back surface of the first connector in a position further projecting than the close contact surface and is contracted to a position where the suction pad is disposed flush with the close contact surface in a sucked state.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Fanuc Corporation
    Inventor: Yoshio Motowaki
  • Patent number: 10605679
    Abstract: A pressure sensor is disclosed. The pressure sensor includes a common electrode, sensitized electrodes, mountain-shaped pressure-sensitive layers, and thin-film transistors. The common electrode is formed as a layer. The sensitized electrodes are arranged in a matrix opposing the common electrode. The mountain-shaped pressure-sensitive layers are respectively formed over the sensitized electrodes on a side close to the common electrode. The thin-film transistors are disposed to correspond to the sensitized electrodes on sides of the sensitized electrodes opposite to the common electrode.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 31, 2020
    Assignee: NISSHA CO., LTD.
    Inventor: Hideaki Nada
  • Patent number: 10573543
    Abstract: An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 25, 2020
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, Peter Scott Andrews
  • Patent number: 10515838
    Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 24, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10497708
    Abstract: A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 3, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: He Chen, Jin Wen Dong, Jifeng Zhu, Zi Qun Hua, Liang Xiao, Yong Qing Wang
  • Patent number: 10433430
    Abstract: A memory module card structure includes a main board, a plurality of adhesive layers and a plurality of conduction skirting boards. Two surfaces of the main board respectively are divided into a mounting section and an inserting section. The inserting section is formed with a binding region, and a soldering region having solder pads electrically connected to the mounting section. The conduction skirting boards are correspondingly fixed to the inserting section, and each has a rigid substrate and a plurality of conductive pads. The conductive pad has an outer contacting part disposed on an outer surface of the rigid substrate and an adapting part formed through the rigid substrate and connecting the outer contacting part. A part of the conductive pad correspondingly is soldered to the solder pad. A part of the rigid substrate is fixed connected to the binding region by the adhesive layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 1, 2019
    Inventor: Sung-Yu Chen
  • Patent number: 10381720
    Abstract: A matching network is integrated into a multilayer surface mount device containing an RFID integrated circuit to provide both an antenna and a matching network for the RFID integrated circuit in the ultra high frequency regime. The surface mount device may be mounted on a printed circuit board to provide RF and RFID functionality to the printed circuit board.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 13, 2019
    Assignee: NXP B.V.
    Inventors: Giuliano Manzi, Gerald Wiednig
  • Patent number: 10297478
    Abstract: An apparatus includes a product substrate having a transfer surface, and a semiconductor die defined, at least in part, by a first surface adjoined to a second surface that extends in a direction transverse to the first surface. The semiconductor die is disposed on the transfer surface of the product substrate such that at least a portion of the first surface is in contact with the transfer surface, and at least a portion of the second surface is embedded onto the product substrate, beneath a plane that extends across the transfer surface.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 21, 2019
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andrew Huska, Justin Wendt
  • Patent number: 10199297
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chun Song, Yi Zhong