By Metal Fusion Patents (Class 29/840)
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Patent number: 9171882Abstract: According to one embodiment, a semiconductor light emitting device includes a plurality of chips, a first insulating layer provided between the chips, one p-side external terminal, and one n-side external terminal. Each of the chips includes a semiconductor layer, a p-side electrode, and an n-side electrode. Each of the chips is separated from each other. The one p-side external terminal is provided corresponding to one chip on the second face side. The p-side external terminal is electrically connected to the p-side electrode. The one n-side external terminal is provided corresponding to one chip on the second face side. The n-side external terminal is electrically connected to the n-side electrode.Type: GrantFiled: February 10, 2014Date of Patent: October 27, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yosuke Akimoto, Yoshiaki Sugizaki, Akihiro Kojima, Kazuhito Higuchi, Hideo Nishiuchi, Susumu Obata
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Patent number: 9158078Abstract: The semiconductor laser module (1) includes: a laser mount (31) having thereon a semiconductor laser chip (32); a fiber mount (40) having thereon an optical fiber (2); a submount (20) on which the laser mount (31) and the fiber mount (40) are placed; and a substrate (10) on which the submount 20 is placed, the substrate (10) having protrusions (11a to 11d) on a top surface thereof, the submount 20 being joined to the substrate (10) with a soft solder (61) spread between the submount (20) and the substrate (10).Type: GrantFiled: December 12, 2013Date of Patent: October 13, 2015Assignee: FUJIKURA LTD.Inventors: Nozomu Toyohara, Akira Sakamoto, Yohei Kasai
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Patent number: 9151300Abstract: The present invention relates to a vacuum pump, and more particularly, to an inline vacuum pump. The inline vacuum pump according to the present invention comprises a cylinder-type housing, an ejector, and a guide which are mounted in series on the upper side and the lower side in the housing, and a gripper connector coupled to the lower portion of the housing. The guide is provided with a passage and a path through which compressed air is discharged and exhaust air is absorbed. According to the present invention, device design and production are easier than in the related art, and a vacuum is generated and maintained in a stable manner. Also, the ejector can be relatively freely selected and applied.Type: GrantFiled: March 29, 2013Date of Patent: October 6, 2015Assignee: KOREA PNEUMATIC SYSTEM CO., LTD.Inventor: Ho-Young Cho
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Patent number: 9142533Abstract: A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.Type: GrantFiled: May 20, 2010Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Wei Shen, Ying-Ching Shih, Chen-Shien Chen, Ming-Fa Chen
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Patent number: 9138899Abstract: A suction device includes a suction head, a fixing assembly, a rotating assembly, and a sliding assembly. The rotating assembly includes a shaft defining a spiral sliding slot. The suction head is attached to an end of the shaft. The sliding assembly is slidable and attached to the fixing assembly and includes a guiding post. An end of the guiding post is slidable and received in the spiral sliding slot. The sliding assembly is able to slide relative to the fixing assembly to slide the guiding post along the spiral sliding slot, thereby urging the shaft together with the suction head to rotate.Type: GrantFiled: October 20, 2014Date of Patent: September 22, 2015Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITEDInventors: Xu Gong, Bing Yu, Jian-Ping Jin
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Patent number: 9136237Abstract: This chip package includes a substrate having a multilayer electroplated stack disposed on a surface of the substrate. The multilayer electroplated stack may include one or more instances of alternating layers of gold and tin, where relative thicknesses of the alternating layers, when melted, result in a chemical composition having an initial melting temperature to form a bump and a subsequent melting temperature to reflow the bump that is higher than the initial melting temperature. For example, the chemical composition may correspond to a non-equilibrium gold-tin alloy.Type: GrantFiled: December 17, 2013Date of Patent: September 15, 2015Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Hiren D. Thacker, John E. Cunningham
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Patent number: 9136462Abstract: A method of manufacturing a conductive adhesive bond assembly consisting of a piezoactuator and a printed circuit board that are connected by at least one adhesive connection, with at least one electrical connection created by an electrically conductive adhesive between a first connection contact on the printed circuit board and between a second connection contact on the piezoactuator, whereby the connection contacts face in the same direction and the adhesive connection takes place through an opening in one of the components.Type: GrantFiled: November 22, 2011Date of Patent: September 15, 2015Assignee: VEGA GRIESHABER KGInventors: Joern Jacob, Holger Gruhler
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Patent number: 9129971Abstract: A semiconductor device includes a semiconductor die having contact pads disposed over a surface of the semiconductor die, a die attach adhesive layer disposed under the semiconductor die, and an encapsulant material disposed around and over the semiconductor die. The semiconductor device further includes bumps disposed in the encapsulant material around a perimeter of the semiconductor die. The bumps are partially enclosed by the encapsulant material. The semiconductor device further comprises first vias disposed in the encapsulant. The first vias expose surfaces of the contact pads. The semiconductor device further includes a first redistribution layer (RDL) disposed over the encapsulant and in the first vias, and a second RDL disposed under the encapsulant material and the die attach adhesive layer. The first RDL electrically connects each contact pad of the semiconductor die to one of the bumps, and the second RDL is electrically connected to one of the bumps.Type: GrantFiled: January 6, 2011Date of Patent: September 8, 2015Assignee: STATS ChipPAC, Ltd.Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Jeffrey D. Punzalan
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Patent number: 9112616Abstract: An optical transceiver system is provided that comprises multiple parallel transceiver modules that are mounted on a card. The transceiver card is small in terms of spatial dimensions, has very good heat dissipation characteristics, and is capable of simultaneously transmitting and receiving data at a rate equal to or greater than approximately one Tb per second (1 Tb/s). A plurality of the transceiver systems may be interconnected to achieve a communications hub system having even higher bandwidths. In addition, the transceiver system may be configured such that each card has a routing controller mounted thereon for performing router functions.Type: GrantFiled: August 13, 2008Date of Patent: August 18, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Laurence R. McColloch
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Patent number: 9099460Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.Type: GrantFiled: August 22, 2014Date of Patent: August 4, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Rae Cho, Tae-Hoon Kim, Ho-Geon Song, Seok-Won Lee
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Patent number: 9071893Abstract: A multi-array type ultrasonic probe apparatus includes n tiles which transmit and receive an ultrasonic beam; and a substrate having n guide portions on which the n tiles are mounted, respectively, to be aligned in a multi-array. The multi-array ultrasonic probe apparatus may align tiles in identical directions and at identical levels to control a direction and a time for transmitting and receiving an ultrasonic beam to be transmitted and received at the tiles, thereby providing a stable ultrasonic beam.Type: GrantFiled: January 15, 2013Date of Patent: June 30, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Il Kim, Dong Wook Kim, Bae Hyung Kim, Jong Keun Song, Seung Heun Lee, Kyung Il Cho
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Patent number: 9070662Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.Type: GrantFiled: March 2, 2010Date of Patent: June 30, 2015Assignee: Volterra Semiconductor CorporationInventors: Mihalis Michael, Ilija Jergovic
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Publication number: 20150146380Abstract: An electronic device includes a bottom case, an accommodation unit, an electromagnetic induction module, a heat-dissipating component, an elastic clip, a printed wiring board, and an electronic component. The accommodation unit is disposed on the bottom case. At least one portion of the electromagnetic induction module is disposed in the accommodation unit. The heat-dissipating component is disposed on the bottom case and is separated from the accommodation unit. The elastic clip is partially mounted on the heat-dissipating component. The printed wiring board has a first surface and a second surface, and the first surface faces the accommodation unit. The electronic component includes a main body and pin feet. The pin feet are electrically connected to the printed wiring board, and the main body is clamped between the heat-dissipating component and the elastic clip.Type: ApplicationFiled: July 24, 2014Publication date: May 28, 2015Inventors: Xing-Xian LU, Pei-Ai YOU, Gang LIU, Jin-Fa ZHANG
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Publication number: 20150131250Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming a first through hole through the thermal pad, the second dielectric layer, the at least one conductive layer, and the first dielectric layer. The fabricating includes filling the first through hole with a conductive material to form a plated through hole. The fabricating includes topdrilling the plated through hole to remove a top portion of the conductive material from a top of the plated through hole, wherein a bottom portion of the conductive material remains in the plated through hole after removal of the top portion.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventor: Phillip D. Isaacs
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Publication number: 20150121692Abstract: Provided is an electronic component mounting method including the steps of: placing an electronic component having a primary surface on which a first electrode is formed, on a circuit member having a primary surface on which a second electrode corresponding to the first electrode is formed, with solder and a bonding material including a thermosetting resin interposed between the first and second electrodes; subjecting the thermosetting resin to a first heating at a temperature lower than the melting point of the solder and thus causing the resin to cure, while pressing the electronic component against the circuit member, and then releasing pressure applied for the pressing; and subjecting the solder interposed between the first and second electrodes to a second heating with the pressure released, and thus melting the solder to electrically connect the first and second electrodes.Type: ApplicationFiled: March 15, 2013Publication date: May 7, 2015Inventor: Hideki Eifuku
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Patent number: 9021692Abstract: A printed wiring board includes a resin insulation layer having a first surface and a second surface on an opposite side of the first surface, the resin insulation layer having an opening for a first via conductor, a pad formed on the first surface of the resin insulation layer and provided to mount an electronic component, a first conductive circuit formed on the second surface of the resin insulation layer, and a first via conductor formed in the opening and connecting the pad and the first conductive circuit. The pad has an embedded portion embedded in the resin insulation layer and a protruding portion protruding from the resin insulation layer, and the embedded portion has an external shape which is greater than an external shape the protruding portion.Type: GrantFiled: November 29, 2011Date of Patent: May 5, 2015Assignee: Ibiden Co., Ltd.Inventors: Satoru Kawai, Kenji Sakai, Liyi Chen
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Patent number: 9021669Abstract: Provided is a method for manufacturing a surface acoustic wave apparatus that can reduce degradation of electric characteristics and also reduce the number of manufacturing processes. The method for manufacturing a surface acoustic wave apparatus includes the steps of: forming an IDT electrode on an upper surface of a piezoelectric substrate, forming a frame member surrounding a formation area in which the IDT electrode is formed on the piezoelectric substrate, and mounting a film-shaped lid member on the upper surface of the frame member so as to be joined to the frame member so that a protective cover, used for covering the formation area and for providing a tightly-closed space between it and the formation area, is formed.Type: GrantFiled: August 7, 2007Date of Patent: May 5, 2015Assignee: KYOCERA CorporationInventor: Toru Fukano
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Publication number: 20150103491Abstract: An unpacked structure for a power device of radio frequency power amplification module and assembly method therefor. The radio frequency power amplification module includes the power device, a heat dissipating plate and a printed circuit board, wherein the power device is embedded into the printed circuit board; the heat dissipating plate is arranged below the power device and the printed circuit board; the power device includes a carrier flange, a plurality of electronic elements and a plurality of lead wires; the electronic elements are directly welded on the carrier flange according to a design requirement; the power device and the printed circuit board are welded and fixed on the heat dissipating plate; and the electronic elements on the power device are connected with one another through the lead wires and directly connected with the printed circuit board through the lead wires.Type: ApplicationFiled: March 18, 2013Publication date: April 16, 2015Applicant: Innogration (SuZhou) Co., Ltd.Inventor: Gordon Chiang Ma
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Patent number: 9003649Abstract: A fluid cooled electrical assembly that includes a metal box, having a bottom wall, side walls and a top wall. A set of straight-edged pins, each smaller than 3 mm across in widest dimension, extend down from the top wall and up from the bottom wall. Also, electrical components are mounted on top of the top wall and on bottom of the bottom wall.Type: GrantFiled: January 25, 2012Date of Patent: April 14, 2015Assignee: Maxq Technology, LLCInventors: Guillermo L. Romero, Joe L Martinez, Jr.
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Patent number: 8997340Abstract: A method of manufacturing an insulating sheet, the method including providing a reinforcement material having a thermoplastic resin layer stacked thereon; stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate; and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate.Type: GrantFiled: September 21, 2011Date of Patent: April 7, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
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Publication number: 20150089805Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: International Business Machines CorporationInventors: Stephen P. Ayotte, Glen E. Richard, Timothy D. Sullivan, Timothy M. Sullivan
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Publication number: 20150092373Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) comprising a ball grid array (BGA) of BGA pads on one side of the PCB, arranged in a grid pattern; through-hole vias, including a via pad, arranged in said grid pattern electrically connected to said BGA pads; a solder mask covering the via pad with an opening; a solder pad within said opening electrically connected to said via pad; and a two-lead component attached to said solder pad.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: ALCATEL-LUCENT CANADA INC.Inventors: Alex CHAN, Paul J. BROWN
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Publication number: 20150092374Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The fabricating includes backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: International Business Machines CorporationInventor: Phillip D. Isaacs
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Patent number: 8991043Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.Type: GrantFiled: July 19, 2012Date of Patent: March 31, 2015Assignee: Subtron Technology Co., Ltd.Inventor: Chao-Min Wang
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Publication number: 20150085504Abstract: In one aspect, a circuit board includes a base board and a layer of an elastic material comprising a first surface and a second surface. The layer of elastic material is adhered to the base board via the first surface. The circuit board further includes an electrical trace disposed on the second surface of the layer of elastic material. At least a portion of the layer of elastic material stretches or shrinks when the base board expands or contracts. A method of manufacturing a circuit includes obtaining an aluminum board, obtaining a layer of an elastic material, and applying a layer of adhering material to a surface of the aluminum board. The method further includes disposing the layer of the elastic material onto the layer of adhering material, and adhering the layer of the elastic material onto the aluminum board via the layer of adhering material.Type: ApplicationFiled: September 23, 2014Publication date: March 26, 2015Inventor: Ellis W. Patrick
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Patent number: 8978246Abstract: A method of attaching two wafers in a seismometer comprising the steps of forming a patterned wetting metal layer on a first wafer and forming a plurality of cavities mirroring the pattern of the wetting metal layer on the first wafer. The steps further include pouring a plurality of solder balls on the surface of an alignment wafer, pouring off excess solder balls, aligning the first wafer with the alignment wafer, and connecting the first wafer with the alignment wafer. The solder balls are immobilized on the wetting metal layer by performing a partial reflow onto the wetting metal layer and removing the alignment wafer. The first and second wafers are aligned so that each solder ball is immobilized between the first and second wafer. The wafers are then bonded together.Type: GrantFiled: January 17, 2011Date of Patent: March 17, 2015Assignee: Kinemetrics, Inc.Inventors: William T. Pike, Ian Standley
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Patent number: 8978245Abstract: A method includes securing a midplane to a bracket disposed between a first and second ends of a chassis, wherein a first surface of the midplane engages the bracket and faces the first end of the chassis. A first electronic device is secured within the first end of the chassis with a first device connector coupled to a first midplane connector on the first surface of the midplane and a first device latch secured directly to a first slot in the chassis adjacent the first end. A sub-chassis is secured within the second end of the chassis, wherein the sub-chassis has a proximal end that engages a second surface of the midplane. Furthermore, a second electronic device is secured within the sub-chassis with a second device connector coupled to a second midplane connector on the second surface of the midplane and a second device latch secured directly to a slot in the sub-chassis adjacent the distal end of the sub-chassis.Type: GrantFiled: December 30, 2012Date of Patent: March 17, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Karl K. Dittus, David J. Jensen, Brian A. Trumbo
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Patent number: 8966747Abstract: A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation with the mold forming part of the finished product, e.g. providing heat sink fins or a surface mount solderable surface. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features such as registration features accurately locating the circuit board within the mold cavity, interlocking contours for structural integrity of the singulated module, contours to match component shapes and sizes enhancing heat removal from internal components and reducing the required volume of encapsulant, clearance channels providing safety agency spacing and setbacks for the interconnects.Type: GrantFiled: May 11, 2011Date of Patent: March 3, 2015Assignee: VLT, Inc.Inventors: Patrizio Vinciarelli, Michael B. Lafleur, Sean Timothy Fleming, Rudolph Mutter, Andrew T. D'Amico
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Patent number: 8968608Abstract: An object of the present invention is to provide a method for producing a conductive material that allows a low electric resistance to be generated, and that is obtained by using an inexpensive and stable conductive material composition containing no adhesive. The conductive material can be provided by a producing method that includes the step of sintering a first conductive material composition that contains silver particles having an average particle diameter (median diameter) of 0.1 ?m to 15 ?m, and a metal oxide, so as to obtain a conductive material. The conductive material can be provided also by a method that includes the step of sintering a second conductive material composition that contains silver particles having an average particle diameter (median diameter) of 0.1 ?m to 15 ?m in an atmosphere of oxygen or ozone, or ambient atmosphere, at a temperature in a range of 150° C. to 320° C., so as to obtain a conductive material.Type: GrantFiled: January 9, 2009Date of Patent: March 3, 2015Assignee: Nichia CorporationInventors: Masafumi Kuramoto, Satoru Ogawa, Katsuaki Suganuma, Keun-Soo Kim
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Publication number: 20150055310Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.Type: ApplicationFiled: August 21, 2013Publication date: February 26, 2015Inventors: LAKSHMINARAYAN VISWANATHAN, Jaynal A. Molla, Mahesh K. Shah
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Patent number: 8959757Abstract: In one embodiment, a shielded electronic module is formed on a substrate. The substrate has a component area and one or more electronic components attached to the component area. One set of conductive pads may be attached to the component area and another set of conductive pads may be provided on the electronic component. The conductive pads on the component area are electrically coupled to the conductive pads of the electronic component by a conductive layer. A first insulating layer is provided over the component area and underneath the conductive layer that may insulate the electronic component and the substrate from the conductive layer. A second insulating layer is provided over the first insulating layer that covers at least the conductive layer. In this manner, the conductive layer is isolated from an electromagnetic shield formed over the component area.Type: GrantFiled: December 29, 2011Date of Patent: February 24, 2015Assignee: RF Micro Devices, Inc.Inventors: Thong Dang, Mohsen Haji-Rahim, Mark Charles Held
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Publication number: 20150050028Abstract: A structured substrate for optical fiber alignment is produced at least in part by forming a substrate with a plurality of buried conductive features and a plurality of top level conductive features. At least one of the plurality of top level conductive features defines a bond pad. A groove is then patterned in the substrate utilizing a portion of the plurality of top level conductive features as an etch mask and one of the plurality of buried conductive features as an etch stop. At least a portion of an optical fiber is placed into the groove.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: International Business Machines CorporationInventors: Russell A. Budd, Paul F. Fortier
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Patent number: 8955215Abstract: A method of forming an interconnect assembly including forming a substrate with a plurality of through holes extending from a first major surface to a second major surface. A plurality of recesses are formed in the second major surface of the substrate that at least partially overlap with the plurality of through holes. The recesses have a cross-sectional area greater than a cross-sectional area of the through holes. At least one discrete contact member is inserted in a plurality of the through holes. The contact members include proximal ends extending into the recesses, distal ends extending above the first major surface, and intermediate portions engaged with an engagement region of the substrate located between the first major surface and the recesses. Retention members at least partially deposited in the recesses bond to the proximal ends to retain the contact members in the through holes.Type: GrantFiled: May 25, 2010Date of Patent: February 17, 2015Assignee: Hsio Technologies, LLCInventor: James Rathburn
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Patent number: 8955214Abstract: A method for securing a signal propagating line to a downhole component includes configuring the downhole component in a final form prior to securing the line thereto; positioning the line at an outside dimension of the component; and fusing the line to the component with a heat based fusion method and apparatus therefore.Type: GrantFiled: November 30, 2007Date of Patent: February 17, 2015Assignee: Baker Hughes IncorporatedInventors: Vinay Varma, Stephen L. Crow, Martin P. Coronado
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Publication number: 20150041200Abstract: The invention relates to a soldering method and a corresponding soldering device for soldering a printed circuit board (2) to an electric component (8) using a solder (6, 7), said solder (6, 7) being melted by heat and then connecting the component (8) to the printed circuit board (2). The heat required to melt the solder (6, 7) is generated by electrically energizing the component (8), thereby generating an electric heat loss in the component (8), said heat loss being transferred from the component (8) to the solder (6, 7) and melting the solder (6, 7).Type: ApplicationFiled: December 21, 2012Publication date: February 12, 2015Inventors: Ullrich Hetzler, Ruediger Stuehn
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Publication number: 20150040390Abstract: A manufacturing method of laser diode unit of the present invention includes steps: placing a laser diode on top of a solder member formed on a mounting surface of a submount, applying a pressing load to the laser diode and pressing the laser diode against the solder member, next, melting the solder member by heating the solder member at a temperature higher than a melting point of the solder member while the pressing load is being applied, and thereafter, bonding the laser diode to the submount by cooling and solidifying the solder member, thereafter, removing the pressing load, and softening the solidified solder member by heating the solder member at a temperature lower than the melting point of the solder member after the pressing load has been removed, and thereafter cooling and re-solidifying the solder member.Type: ApplicationFiled: September 22, 2014Publication date: February 12, 2015Inventors: Koji SHIMAZAWA, Osamu SHINDO, Yoshihiro TSUCHIYA, Yasuhiro ITO, Kenji SAKAI
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Patent number: 8950067Abstract: An electronic component device having a first sealing frame formed on a main substrate and a second sealing frame formed on a cover substrate, the first and second sealing frames being composed of a Ni film. A bonding section constituted by a Ni—Bi alloy is formed between the first and second sealing frames. For example, a Bi layer is formed on the first sealing frame, and then the first sealing frame and the second sealing frame are heated at a temperature of 300° C. for at least 10 seconds while applying pressure in the direction in which the first sealing frame and the second sealing frame are in close contact with each other, and thus the bonding section, which bonds the first sealing frame to the second sealing frame, is formed.Type: GrantFiled: September 6, 2013Date of Patent: February 10, 2015Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroki Horiguchi, Yuji Kimura
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Patent number: 8938880Abstract: A cold plate is manufactured by obtaining a base plate with a top surface, a bottom surface, and an edge. An inlet trough and an outlet trough are machined in the top surface. Fins are cut into the base plate with a tool that contacts the base plate in either the inlet trough and the outlet trough and then exits the base plate in the other of the inlet trough and the outlet trough. An inlet nozzle indent is machined from the inlet trough to the edge of the base plate, and an outlet nozzle indent is machined from the outlet trough to the edge of the base plate. A cover covers the inlet and outlet nozzle indents, and an inlet nozzle and outlet nozzle are secured to the inlet and outlet nozzle indents.Type: GrantFiled: February 19, 2013Date of Patent: January 27, 2015Assignee: Wolverine Tube, Inc.Inventors: Sy-Jenq Loong, Donald Lynn Smith, Matthew Reeves, Peter Beucher
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Patent number: 8935848Abstract: The present invention is a method for providing an integrated circuit assembly, the integrated circuit assembly including an integrated circuit and a substrate. The method includes mounting the integrated circuit to the substrate. The method further includes, during assembly of the integrated circuit assembly, applying a low processing temperature, at least near-hermetic, glass-based coating directly to the integrated circuit and a localized interconnect interface, the interface being configured for connecting the integrated circuit to at least one of the substrate and a second integrated circuit of the assembly. The method further includes curing the coating. Further, the integrated circuit may be a device which is available for at least one of sale, lease and license to a general public, such as a Commercial off the Shelf (COTS) device. Still further, the coating may promote corrosion resistance and reliability of the integrated circuit assembly.Type: GrantFiled: October 16, 2013Date of Patent: January 20, 2015Assignee: Rockwell Collins, Inc.Inventors: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon
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Publication number: 20150016116Abstract: The present invention discloses a flexible LED light bar, which includes a flexible circuit board, a light cup, an LED chip, and an LED encapsulation material. The light cup is formed on the flexible circuit board. The LED chip is encapsulated in the light cup and is bonded to the flexible circuit board to form electrical connection therebetween. The present invention also provides a manufacturing method of a flexible LED light bar.Type: ApplicationFiled: January 28, 2014Publication date: January 15, 2015Applicant: XIAMEN CHANGELIGHT CO., LTD.Inventors: ZUNXIANG HUANG, YUANMING LI
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Publication number: 20150011112Abstract: The invention relates to a device (2) for electrically connecting an electronic board (22), including at least one electrical conductor (23) for conducting a current to and/or from said electronic board (22), a body (24) extending in at least one plane (26) and retaining said electrical conductor (23) in said plane via a portion of said conductor, and at least one outgrowth (28) extending from said body (24), said outgrowth (28) including at least one member (30) for assembling said connection device (20) to said electronic board (22), such that the body (24) is opposite the electronic board (22).Type: ApplicationFiled: July 31, 2012Publication date: January 8, 2015Applicant: VALEO SYSTEMES DE CONTROLE MOTEURInventors: Pierre Smal, Guillaume Sanvito
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Patent number: 8927873Abstract: There is provide a manufacturing method of a fin-integrated substrate capable of producing by simple process a fin-integrated substrate with heat radiating fins at fine pitches by a processing method in which warpage of a metal base plate and corrugation (wavy shape) of the heat radiating fins are suppressed. There is provided a manufacturing method of a fin-integrated substrate in which bonding of the metal circuit board to the ceramic substrate is performed by a molten metal bonding method, and formation of the plurality of heat radiating fins at a cut part that is a part of the metal base plate is performed by fixing by a jig to apply a tensile stress on a surface of the cut part where the heat radiating fins are to be formed, and performing grooving processing of forming a plurality of grooves by moving a multi-cutter composed of a plurality of stacked disc-shaped cutters, on the surface to which the tensile stress is applied, while rotating the multi-cutter.Type: GrantFiled: January 12, 2011Date of Patent: January 6, 2015Assignees: Dowa Metaltech Co., Ltd, Nippon Light Metal Company, Ltd.Inventors: Hisashi Hori, Hideyo Osanai, Takayuki Takahashi
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Publication number: 20150003023Abstract: An electronic component module includes a board having an electronic component mounted on a surface of the board and a shield case mounted on the surface of the board and covering the electronic component. The board includes a projecting part projecting from the surface of the board. The projecting part is formed of plating at a position along a sidewall of the shield case and is soldered to the shield case.Type: ApplicationFiled: June 20, 2014Publication date: January 1, 2015Applicant: FUJITSU COMPONENT LIMITEDInventors: Shinya Yamamoto, Tohru Muramatsu, Masakazu Muranaga
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Publication number: 20140374395Abstract: A power conversion assembly for use in a welding power supply includes a power magnetics module and a power electronics module. The power magnetics module includes at least one transformer disposed on a first wind tunnel housing. The power electronics module is separate from and electrically coupled to the power magnetics module. The power electronics module includes switching circuitry and one or more heat sinks to remove heat from the switching circuitry. The switching circuitry and the heat sinks are disposed on a second wind tunnel housing coupled to the first wind tunnel housing.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Jason Alan Dunahoo, Ronald Dewayne Woodward, Benjamin David Romenesko, Chris J. Roehl, Craig Steven Knoener, Joshua Thomas Stiever
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Patent number: 8904630Abstract: A land grid array (LGA) socket uses a series of inclined engagement features to transfer a lateral load into a normal load to retain the LGA package in the socket. The number and position of the engagement features along the side of the socket permits a more uniform transfer of load to the solder ball array as compared to current mechanisms.Type: GrantFiled: February 28, 2012Date of Patent: December 9, 2014Assignee: Intel CorporationInventors: Rick Canham, Tozer Bandorawalla, Alan McAllister, Kelly Eakins
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Publication number: 20140347822Abstract: A module includes a wiring board; a plurality of mounting electrodes for component mounting, the mounting electrodes being disposed on one principal surface of the wiring board; a plurality of components mounted on the one principal surface of the wiring board and solder-connected to the mounting electrodes; a solder resist being a photosensitive resin configured to cover the one principal surface of the wiring board, with a plating electrode layer of each mounting electrode exposed; and a sealing resin layer disposed on the one principal surface of the wiring board, the sealing resin layer being configured to cover the photosensitive resin and the components connected to the mounting electrodes. A recess substantially wedge-shaped in cross section is provided at a boundary between the plating electrode layer of each mounting electrode and the solder resist, and the recess is filled with resin of the sealing resin layer.Type: ApplicationFiled: March 24, 2014Publication date: November 27, 2014Applicant: Murata Manufacturing Co., Ltd.Inventor: Masaaki MIZUSHIRO
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Patent number: 8893379Abstract: A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.Type: GrantFiled: December 3, 2012Date of Patent: November 25, 2014Assignee: Subtron Technology Co., Ltd.Inventors: Shih-Hao Sun, Chang-Fu Chen
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Patent number: 8889994Abstract: A single layered printed circuit board and a method of manufacturing the same are disclosed. In accordance with an embodiment of the present invention, the method can include forming a bonding pad, a circuit pattern and a post on a surface of an insulation film, in which one end part of the post is electrically connected to at least a portion of the circuit pattern, pressing an insulator on the surface of the insulation film, in which the circuit pattern and the post are buried in the insulator, selectively etching the insulator such that the other end part of the post is exposed, and opening a portion of the insulation film such that at least a portion of the bonding pad is exposed.Type: GrantFiled: February 1, 2011Date of Patent: November 18, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Young-Ji Kim, Kyung-Ro Yoon, Sang-Duck Kim, Jung-Hyun Park, Nam-Keun Oh, Jong-Gyu Choi, Ji-Eun Kim
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Patent number: 8891242Abstract: A heat sinking device for a component mounted on an electronic circuit board, including: a hollow body, of straight cylindrical or prismatic form, including a first material, arranged vertically on top of the electronic circuit board, the useful volume of the body including at least the component, a resin including a second material, at least partially filling the internal volume of the body so as to contain the component. The heat sinking device can be arranged on an insulating separator element, the resin can be introduced in the liquid state.Type: GrantFiled: November 19, 2010Date of Patent: November 18, 2014Assignee: ThalesInventors: Pierre Borrat-Michaud, Anne-Gaëlle Tallec
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Patent number: 8887382Abstract: The invention relates to a pendulous accelerometer including a pendulous electrode formed in a substrate, at least one counter electrode, and an encapsulation cover. The at least one counter electrode is formed under the cover, and spacers are positioned between the cover and the substrate.Type: GrantFiled: December 5, 2008Date of Patent: November 18, 2014Assignee: MEMSCAPInventors: Béatrice Wenk, Jean-Francois Veneau, Greg Hames