By Metal Fusion Patents (Class 29/840)
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Patent number: 8079139Abstract: A method for producing an electro-thermal separation type light emitting diode support structure is provided. One of the embodiments for the support structure has at least two heat dissipation bases and at least two conductive supports which are coupled by a heat dissipation plate and a support plate. Another embodiment for the support structure has at least two heat dissipation bases and at least two conductive supports which are formed by a thick-thin plate. The light emitting diode chips of different types can be configured on the heat dissipation bases of these designs, respectively. Therefore, the invention achieves the goal of using different types of light emitting diode chips at the same time.Type: GrantFiled: August 27, 2010Date of Patent: December 20, 2011Assignee: I-Chiun Precision Industry Co., Ltd.Inventors: Shih Chieh Lin, Li Min Chen, Yung Chieh Chen
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Patent number: 8079142Abstract: A method for manufacturing a printed circuit board, including providing a core substrate and an electronic component contained in the core substrate, the electronic component having a die pad, forming a positioning mark on the core substrate, forming an interlayer insulating layer over the core substrate and the electronic component, forming a via hole opening connecting to the die pad of the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate, and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the die pad.Type: GrantFiled: November 19, 2008Date of Patent: December 20, 2011Assignee: Ibiden Co., Ltd.Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
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Patent number: 8079141Abstract: The method for providing the solder connection of the present invention is a method for providing a solder connection, which electrically connects a first electronic component having a solder bump to a second electronic component having a protruded electrode to provide electrical connection between the first solder bump and the protruded electrode, wherein a relation of: A+B>C is satisfied, where a height of the first solder bump from one surface of the first electronic component is presented as A [?m], a height of the protruded electrode before the compressive deformation from one surface of the second electronic component is presented as B [?m], and a thickness of the adhesive agent layer is presented as C [?m], and further comprising: disposing the adhesive agent layer in the first electronic component; and deforming the first solder bump and the protruded electrode and providing a contact of the above-described protruded electrode with the above-described first solder bump, so that the sum of the heighType: GrantFiled: February 24, 2009Date of Patent: December 20, 2011Assignee: Sumitomo Bakelite Co., Ltd.Inventor: Toru Meura
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Publication number: 20110307911Abstract: A circuit board for supplying therethrough an electric current to a stator including windings arranged to generate magnetic fields includes a body portion having a rectangular shape when seen in a plan view and mounted with electronic parts, and an extension portion protruding from the body portion substantially along a circumferential direction around a rotation axis of the motor when seen in a plan view. The extension portion includes a distal end extension opposed to the body portion through a gap when seen in a plan view. The transverse width of the extension portion is smaller than the gap. The body portion includes an outward connector portion connected to an external power source or an external circuit board. The extension portion includes a winding connection portion connected to the outward connector portion through a wiring portion. The windings are soldered to the winding connection portion.Type: ApplicationFiled: June 7, 2011Publication date: December 15, 2011Applicant: NIDEC CORPORATIONInventors: Masahiro Yamada, Satoshi Komatsu
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Publication number: 20110296680Abstract: A vented BGA package is reconfigured by first applying a continuous bead of adhesive around the perimeter of the package to seal the gap between the lid and substrate. The continuous bead defines a channel through the pressure relief vents to a polarity through-hole in the lid. The BGA package is reflow soldered to a PWB at an elevated temperature using solder flux, clean or no-clean. The IC die achieves elevated temperature pressure relief through the pressure relief vents along the channel and out the polarity through-hole. After reflow a seal is applied to plug the polarity through-hole. The PWB is washed in an aqueous cleaner solution to remove flux residue. The continuous bead of adhesive and the seal form a cleaner solution barrier that prevents the solution from contacting conductors inside the package. The seal may be removed or left intact depending on the operating environment.Type: ApplicationFiled: June 5, 2010Publication date: December 8, 2011Inventors: Robert H. Dennis, Amanda Loehr, Robert E. Morris, Peter D. Patalano, Aaron J. Stein, John Stephens, Harold L. Wieck, Eli Holzman
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Patent number: 8069559Abstract: An insulated metal substrate laminate includes a metal substrate, a dielectric layer disposed upon the metal substrate, wherein the dielectric layer comprises a thermoplastic film having a thickness of less than or equal to 10 micrometers, a thermal resistance of less than or equal to 0.050 Kelvin-square inches per watt, and a breakdown voltage greater than or equal to 1000 volts (alternating current), and an electrically conductive layer disposed upon the dielectric layer.Type: GrantFiled: August 21, 2008Date of Patent: December 6, 2011Assignee: World Properties, Inc.Inventor: Seung B. Chun
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Patent number: 8065793Abstract: An application method for resin includes applying resin to a first electronic component in an application chamber under a first internal pressure, moving a second electronic component into an internal pressure adjustment chamber under a second internal pressure which is higher than the first internal pressure and adjusting an internal pressure of the internal pressure adjustment chamber from the second internal pressure to the first internal pressure, and moving the second electronic component into the application chamber while moving the first electronic component into the internal pressure adjustment chamber after the step of application of the resin has been completed.Type: GrantFiled: November 12, 2009Date of Patent: November 29, 2011Assignee: Fujitsu LimitedInventors: Kazuyuki Ikura, Junzou Une, Jun Matsueda
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Publication number: 20110285406Abstract: A sensor includes a coil arranged in a housing. The coil is electrically connected to a printed circuit board, which is likewise arranged in the housing. Sensor terminals are arranged at the printed circuit board on a side of the housing opposite the coil. The coil has at least two contacts running asymmetrically to a coil axis, which are connected to the printed circuit board. A method of assembling the sensor is also provided.Type: ApplicationFiled: May 19, 2011Publication date: November 24, 2011Inventors: Burkhard REETMEYER, Thomas Röhm, Pietrino Pirisinu
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Patent number: 8061022Abstract: A method for manufacturing a hybrid printed circuit board having two kinds of wiring boards. The circuit board has method has a first wiring board having a first terminal and, a second wiring board wherein a dent wherein the first wiring board is fitted and equipped with a second terminal is formed, and forming the same plane as the first wiring board. The board also has an insulating adhesive material disposed around the first terminal, and a conductive adhesive joining the first terminal with the second terminal.Type: GrantFiled: March 12, 2008Date of Patent: November 22, 2011Assignee: Fujitsu LimitedInventor: Takashi Kanda
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Publication number: 20110278054Abstract: Various circuit board conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided. The method includes forming a first conductor pad on a circuit board. The first conductor pad includes a first notch and is adapted to couple to a first solder portion.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Inventors: I-Tseng Lee, Yi-Hsiu Liu, Jen-Yi Tsai
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Publication number: 20110273857Abstract: A method for manufacturing a silicon chip package for a circuit board assembly is provided with a package substrate having a silicon chip and an array of contact pads provided by conductive material. A plurality of conductive springs are affixed to the array of contact pads for providing conductive contact with the corresponding array of contacts on a circuit board assembly.Type: ApplicationFiled: May 7, 2010Publication date: November 10, 2011Applicant: ORACLE INTERNATIONAL CORPORATIONInventor: Ashur S. Bet-Shliemoun
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Patent number: 8051560Abstract: A method for fabricating a solder pad structure. A circuit board having thereon at least one copper pad is provided. A solder resist is formed on the circuit board and covers the copper pad. A solder resist opening, which exposes a portion of the copper pad, is formed in the solder resist by laser. The laser also creates a laser activated layer on sidewalls of the solder resist opening. A chemical copper layer is then grown from the exposed copper pad and concurrently from the laser activated layer.Type: GrantFiled: October 16, 2009Date of Patent: November 8, 2011Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang
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Patent number: 8046911Abstract: A method for mounting an electronic component on a substrate includes: forming an Au bump (24) on a surface of an electrode (20) of a substrate (10); placing an Sn-based solder sheet (26) on the Au bump; subjecting the Sn-based solder sheet and the Au bump to reflow soldering, to thus form an Au—Sn eutectic alloy (28); smoothing the eutectic alloy; and bonding an electronic component (30) on a surface of the smoothed eutectic alloy.Type: GrantFiled: October 25, 2007Date of Patent: November 1, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Kei Murayama
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Patent number: 8044427Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.Type: GrantFiled: June 24, 2008Date of Patent: October 25, 2011Assignee: DiCon Fiberoptics, Inc.Inventors: Wen-Herng Su, Junying Lu, Ho-Shang Lee
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Publication number: 20110253430Abstract: A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.Type: ApplicationFiled: April 19, 2010Publication date: October 20, 2011Applicant: GENERAL ELECTRIC COMPANYInventors: Charles Gerard Woychik, John Eric Tkaczyk, Brian David Yanoff, Tan Zhang
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Patent number: 8033012Abstract: A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. In some embodiments, the test pads may be C4 test pads.Type: GrantFiled: July 1, 2008Date of Patent: October 11, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming Cheng Hsu, Clinton Chih-Chieh Chao
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Publication number: 20110239456Abstract: Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Inventors: Robert O. Conn, Daniel S. Stevenson
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Publication number: 20110240352Abstract: A printed circuit board includes a printed circuit board body and a resin layer. The printed circuit board body includes a plurality of mounting pads. The resin layer, containing a thermoplastic resin, is formed on the surface of the printed circuit board body. The resin layer includes a plurality of holes disposed to be aligned with the positions of the mounting pads on a one-to-one basis for exposing the mounting pads therethrough. In a method of fabricating the printed circuit board, the resin layer is formed atop the printed circuit board body.Type: ApplicationFiled: March 25, 2011Publication date: October 6, 2011Applicant: FUJITSU LIMITEDInventors: Naoki NAKAMURA, Nobuo TAKETOMI, Kiyoyuki HATANAKA, Shigeo IRIGUCHI
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Patent number: 8031473Abstract: A control device has a base plate, a cover plate coupled to the base plate, a cavity formed between the base plate and the cover plate, a circuit carrier disposed in the cavity, and a conducting track carrier electrically coupled to the circuit carrier. The base plate has a continuous recess that is configured and arranged for feeding a casting compound into the cavity between the base plate and the cover plate. The casting compound is embodied to at least partly enclose the circuit carrier and/or the conducting track carrier in a vibration-damping manner.Type: GrantFiled: July 14, 2008Date of Patent: October 4, 2011Assignee: Continental Automotive GmbHInventors: Stefan Beer, Josef Loibl, Hermann-Josef Robin, Karl Smirra
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Patent number: 8028403Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: GrantFiled: February 13, 2009Date of Patent: October 4, 2011Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny
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Publication number: 20110235283Abstract: Various exemplary embodiments relate to a brace for use with an integrated circuit (IC), and to an IC package with a brace, having a main body portion and a fastening portion for mechanically fastening the main body portion to the IC, by for example clipping or sliding attachment. Other exemplary embodiments relate to a method of stabilizing an IC during an operation carried out on the IC, such as a soldering operation, involving for example steps of attaching a brace to the IC, performing the operation on the IC, and/or removing the brace after performing the operation.Type: ApplicationFiled: March 23, 2010Publication date: September 29, 2011Applicant: Alcatel-Lucent Canada, Inc.Inventors: Paul J. Brown, Alex L. Chan
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Patent number: 8024856Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.Type: GrantFiled: January 22, 2008Date of Patent: September 27, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Jong-Jin Lee
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Patent number: 8023269Abstract: A circuit assembly (34) resistant to high-temperature and high g centrifugal force is disclosed. A printed circuit board (42) is first fabricated from alumina and has conductive traces of said circuit formed thereon by the use of a thick film gold paste. Active and passive components of the circuit assembly are attached to the printed circuit board by means of gold powder diffused under high temperature. Gold wire is used for bonding between the circuit traces and the active components in order to complete the circuit assembly (34). Also, a method for manufacturing a circuit assembly resistant to elevated temperature is disclosed.Type: GrantFiled: August 15, 2008Date of Patent: September 20, 2011Assignees: Siemens Energy, Inc., Arkansas Power Electronics International, Inc.Inventors: David J. Mitchell, Anand A. Kulkarni, Ramesh Subramanian, Edward R. Roesch, Rod Waits, Roberto Schupbach, John R. Fraley, Alexander B. Lostetter, Brice McPherson, Bryon Western
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Patent number: 8020292Abstract: Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies are provided. In one embodiment, the invention relates to a method of manufacturing a printed circuit board including providing a core subassembly including at least one metal layer, providing a plurality of one-metal layer carriers after parallel processing each of the plurality of one-metal layer carriers, and attaching at least two of the plurality of one-metal layer carriers with each other and with the core subassembly.Type: GrantFiled: April 30, 2010Date of Patent: September 20, 2011Assignee: DDI Global Corp.Inventors: Rajesh Kumar, Monte P. Dreyer, Michael J. Taylor
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Patent number: 8020289Abstract: A method of producing an electronic device includes a molding of a first casing to seal a first face of a circuit board and electronic parts mounted on the first face. The producing method further includes a mounting of electronic parts on a second face of the circuit board opposite from the first face, after the molding of the first casing is finished. The producing method further includes a molding of a second casing to seal the second face of the circuit board and the electronic parts mounted on the second face. The molding of the second casing integrates the first casing and the second casing with each other.Type: GrantFiled: March 18, 2010Date of Patent: September 20, 2011Assignee: Denso CorporationInventors: Keiichi Sugimoto, Mitsuru Nakagawa
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Patent number: 8015700Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.Type: GrantFiled: May 23, 2006Date of Patent: September 13, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Junichi Nakamura, Yuji Kobayashi
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Patent number: 8012865Abstract: A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling.Type: GrantFiled: January 7, 2010Date of Patent: September 6, 2011Assignee: Astriphey Applications L.L.C.Inventor: Vivek Mehrotra
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Patent number: 8001682Abstract: A high-efficiency production method for a power module substrate with reduced line width of a conductive pattern provides an insulation substrate suitable for realizing a large current and a high voltage of a power module. According to the method, a brazing sheet is temporarily fixed on a first surface of a ceramics substrate by surface tension of a volatile organic liquid. The brazing sheet is also temporarily fixed on the first surface of a conductive pattern member punched from a base material by surface tension of same type of volatile organic liquid. The brazing sheet and the conductive pattern member are heated so as to volatilize the volatile organic liquid and a pressure is applied to the conductive pattern member in its thickness direction. The brazing sheet is melted to join the conductive pattern member with the first surface of the ceramics substrate.Type: GrantFiled: August 16, 2005Date of Patent: August 23, 2011Assignee: Mitsubishi Materials CorporationInventors: Takeshi Negishi, Toshiyuki Nagase
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Publication number: 20110198115Abstract: An electronic component built-in module includes an electronic component, a substrate on which the electronic component is mounted, a first resin covering the electronic component and the substrate, and a second resin covering the surface of the first resin. The first resin is formed of a resin including pores. The first resin is formed so that the thickness of the first resin on an area where the electronic component is not mounted is larger than that on an area where the electronic component is mounted on the surface of the substrate. A porosity of the second resin is smaller than that of the first resin.Type: ApplicationFiled: February 11, 2011Publication date: August 18, 2011Applicant: TDK CORPORATIONInventors: Yukihiro AZUMA, Seiichi TAJIMA, Shigeru ASAMI, Hiroki HARA, Shuichi TAKIZAWA, Kenichi KAWABATA
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Patent number: 7993417Abstract: A connecting structure of PCB using an anisotropic conductive film according to the present invention having members connected to each other by heat-compression using the anisotropic conductive film including an insulating adhesive as a base material and conductive particles dispersed in the insulating adhesive, wherein at least any one of the members has a flexible property, and a surface roughness value (Ra) of the member having a flexible property is 0.1 to 5.0 ?m due to dents formed by heat-compression.Type: GrantFiled: January 22, 2007Date of Patent: August 9, 2011Assignee: LS Cable Ltd.Inventors: Chul-Jong Han, Yoon-Jae Chung, Jong-Yoon Jang, Jeong-Beom Park, Yong-Seok Han, Sung-Uk Choi, Il-Rae Cho, Hyuk-Soo Moon, Kyung-Joon Lee
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Patent number: 7992291Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.Type: GrantFiled: October 19, 2007Date of Patent: August 9, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hoe-Ku Jung, Je-Gwang Yoo, Myung-Sam Kang, Ji-Eun Kim, Jeong-Woo Park, Jung-Hyun Park
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Patent number: 7995353Abstract: A circuit board includes four positioning pads placed on a surface of the circuit board, four positioning holes corresponding to the positioning pads, respectively, and a solder mask placed on the surface around the periphery of the positioning pads. An arc-shaped recess is defined at a side of each positioning pad near the corresponding positioning hole and the space between the edges of the positioning pad and the positioning hole ranges from 0.2 mm to 0.5 mm.Type: GrantFiled: August 12, 2008Date of Patent: August 9, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chang-Te Liao
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Patent number: 7987591Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: August 13, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Patent number: 7984891Abstract: A space-conserving integrated fluid delivery system which is particularly useful for gas distribution in semiconductor processing equipment. The fluid delivery system includes an integrated fluid flow network architecture, which may include, in addition to a layered substrate containing fluid flow channels, various fluid handling and monitoring components. The layered substrate is diffusion bonded, and the various fluid handling and monitoring components may be partially integrated or fully integrated into the substrate, depending on design and material requirements.Type: GrantFiled: April 20, 2007Date of Patent: July 26, 2011Assignee: Applied Materials, Inc.Inventors: Mark Crockett, John W. Lane, Michael J. DeChellis, Chris Melcer, Erica R. Porras, Aneesh Khullar, Balarabe N. Mohammed
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Patent number: 7984546Abstract: An apparatus tool for filling vias in a product greensheet and/or repairing vias in a product greensheet. The apparatus tool utilizes a transfer greensheet having filled vias in a fixed array, which vias are punched into the product greensheet to either repair or fill the via of the product greensheet. The apparatus tool employs position determining means such as a camera, a punch head and a corresponding punch die and an activating means to activate the punch head to punch the transfer greensheet via to fill the product greensheet via. The transfer greensheet has a fixed array of filled vias and a transfer greensheet station employs a fixed plate having a plurality of vacuum ports positioned in the non-via areas of the transfer greensheet which secures the transfer greensheet during the repair or fill method. The product greensheet is held by a vacuum plate.Type: GrantFiled: July 2, 2008Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Mark J. LaPlante, Thomas Weiss
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Publication number: 20110173808Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: INVENTEC CORPORATIONInventors: Chung-Yang Wu, Hung-Tao Wong
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Patent number: 7979984Abstract: An improved LED lamp manufacturing method is described. An LED lamp bulb and a pair of electrical cables are provided. The LED lamp bulb is electrically coupled with the pair of electrical cables. A main body is provided to enclose the LED lamp bulb, wherein the main body consists of a first plastic member and a second plastic member. The first plastic member is coupled with the second plastic member.Type: GrantFiled: May 28, 2009Date of Patent: July 19, 2011Assignee: Everlight Electronics Co., LtdInventors: Shang-Lin Chen, Chih-Hung Hsu
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Publication number: 20110167627Abstract: A method of mounting electronic components on a PCB, includes following steps. The PCB is placed with a first side of the PCB facing upwards. A plurality of solder is applied on bonding pads of the first side. A plurality of electronic components is stuck on the bonding pads of the first side. The PCB is turned over with a second side of the PCB facing upwards and the first side of the PCB facing downwards. A plurality of solder is applied on bonding pads of the second side. A plurality of electronic components is stuck on the bonding pads of the second side. The PCB is placed in a reflow oven to weld the electronic components on the first side and the second side of the PCB.Type: ApplicationFiled: April 2, 2010Publication date: July 14, 2011Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: JI MA, LI-BING LU, HUI LUO, QI HUANG
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Publication number: 20110167628Abstract: A method of attaching a component to a substrate, including providing a component guide attached to a substrate, the component guide having a cavity substantially conforming to contours of a portion of a component, attaching a first solder pad to the component, inserting the component into the guide cavity, providing a second solder pad, offset from the first solder pad and near the cavity, and inserting the component, the component guide and the substrate into an oven heating the solder pads, wherein the component is drawn further into the guide cavity by a capillary effect of the heated solder pads.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: Neonode, Inc.Inventors: Magnus Goertz, Thomas Eriksson, Joseph Shain, Anders Jansson, Niklas Kvist, Robert Pettersson, Lars Sparf, John Karlsson
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Patent number: 7975378Abstract: Described are methods for fabricating high speed metallic electrical interconnects for printed wiring board for high speed transmission of a data signal across an interconnect in a systems. The trench under electrical signal line is made using the separate dielectric layer having through holes opened through that said dielectric layer and aligned with electrical signal line. The layer with through holes aligned with electrical signal line sandwiched in between layer carrying the electrical signal line and a layer carrying ground conducting line for the case of microstrip-type transmission line. The two separate layers with the through-holes opened and aligned with the electrical signal line are needed for the stripline-type transmission line. Multi-layers board having high speed electrical signal lines can be made utilizing the configuration described.Type: GrantFiled: January 6, 2010Date of Patent: July 12, 2011Assignee: Banpil Photonics, Inc.Inventor: Achyut Kumar Dutta
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Patent number: 7975371Abstract: The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.Type: GrantFiled: June 21, 2006Date of Patent: July 12, 2011Assignee: Sehyang Industrial Co., Ltd.Inventor: Jae-Ho Ha
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Patent number: 7975379Abstract: LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating surfaces.Type: GrantFiled: August 11, 2009Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Brian S. Beaman, John S. Corbin, Paul Coteus, Shawn A. Hall, Kathleen C. Hinge, Theron L. Lewis, Frank R. Libsch, Amanda E. E. Mikhail
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Patent number: 7971349Abstract: In a method of bonding a first bump on a surface of a first member and a second bump on a surface of a second member, a tip portion of the first bump is provided with a projection having a hardness greater than a hardness of each of the first and second bumps. The first and second members are positioned with respect to each other such that the first and second bumps face each other. The tip portion of the first bump is brought into contact with a tip portion of the second bump by sticking the projection into the tip portion of the second bump.Type: GrantFiled: March 26, 2009Date of Patent: July 5, 2011Assignee: DENSO CORPORATIONInventors: Masaaki Tanaka, Kimiharu Kayukawa
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Patent number: 7971352Abstract: A method of manufacturing a printed circuit board having solder balls. The method may include: stacking a second carrier, in which at least one hole is formed, over one side of a first carrier; forming at least one solder bump by filling the hole with a conductive material; forming a circuit pattern layer, which is electrically connected with the solder bump, on the second carrier; and exposing the solder bump by removing the first carrier and the second carrier. Using this method, uniform hemispherical solder balls with fine pitch can be formed as a part of the manufacturing process, without having to attach the solder balls separately. Carriers may be used to serve as supports during the manufacturing process, whereby deformations can be prevented in the board.Type: GrantFiled: June 19, 2008Date of Patent: July 5, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Shuhichi Okabe, Jin-Yong An, Seok-Kyu Lee, Soon-Oh Jung, Jong-Kuk Hong, Hae-Nam Seo
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Patent number: 7971350Abstract: A shielding assembly is configured to provide electromagnetic shielding and environmental protection to one or more electronic components coupled to a substrate. The shielding assembly includes a non-conductive mold compound layer, such as a dielectric epoxy. The mold compound layer is applied to a top surface of the substrate, thereby covering the electronic components and providing protection against environmentally induced conditions such as corrosion, humidity, and mechanical stress. The shielding assembly also includes a conductive layer applied to a top surface of the mold compound layer. The conductive layer is coupled to a ground plane in the substrate, thereby enabling the electromagnetic shielding function. The conductive layer is coupled to the ground plane via one or more metallized contacts that are coupled to the substrate and extend through the mold compound layer.Type: GrantFiled: July 31, 2008Date of Patent: July 5, 2011Assignee: Flextronics AP, LLCInventor: Rajeev Joshi
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Patent number: 7971348Abstract: A component-embedded substrate includes a component embedded in an uncured resin layer of a second layer. After curing the resin layer, a hole passing through the second layer in the vertical direction is formed. The hole is filled with an electroconductive paste to form a second interlayer connection conductor. A first in-plane conductor including a plurality of lands, a first layer, and the second layer are respectively stacked in that order and pressed to join together, and the first layer is heated to form an integrated structure. A method for manufacturing the component-embedded substrate can form an interlayer connection conductor having a small diameter and high straightness and thus can achieve a miniaturized component-embedded substrate including interlayer connection conductors at a narrow pitch.Type: GrantFiled: January 5, 2009Date of Patent: July 5, 2011Assignee: Murata Manufacturing Co., Ltd.Inventor: Yusuke Yamakoshi
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Publication number: 20110154659Abstract: Apparatuses and methods that provide for enhanced connections between PTHs of multi-layer PCBs and electronic component leads, pins or the like. The apparatuses and methods improve the likelihood that the PTHs are completely filled with solder thereby advantageously allowing the PCBs to exhibit high mechanical and electrical reliability. Complete filling of PTHs is achieved by configuring the electrically conductive layers within the multi-layer PCB stack in a manner that reduces the heat sinking effects of the layers during the soldering process. In this regard, the PTHs may not directly contact all of the internal ground or power planes, so the heat sinking or heat transfer effects are reduced. This feature enables molten solder to substantially or completely fill an entire PTH before freezing.Type: ApplicationFiled: January 4, 2011Publication date: June 30, 2011Applicant: ORACLE AMERICA, INC.Inventors: James David Britton, Jorge Eduardo Martinez-Vargas, JR.
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Patent number: 7966721Abstract: In order to mount an electronic component, a connection terminal of the electronic component is bonded to electrodes of a substrate. This is done by using solder paste which mixes solder particles in a thermosetting adhesive. The solder paste is supplied to the electrodes and a recess. Solder print parts are formed. The electronic component is mounted and the connection terminal and the main body of the electronic component are adhered to the solder print parts, and are heated in this state by reflow. As a result, the connection terminal and the electrodes are bonded by a solder junction.Type: GrantFiled: December 21, 2005Date of Patent: June 28, 2011Assignee: Panasonic CorporationInventors: Yoshiyuki Wada, Tadahiko Sakai
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Patent number: 7958627Abstract: A method of forming an electrical component is provided. The method comprises preparing a subassembly by electrically connecting an integrated circuit to a flexible circuit; and attaching the subassembly to a multilayer ceramic capacitor having a mounting surface with a curvature deviation exceeding 0.008 inches per inch.Type: GrantFiled: September 23, 2008Date of Patent: June 14, 2011Assignee: Kemet Electronics CorporationInventors: Michael S. Randall, Chris Wayne, John McConnell
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Patent number: 7958629Abstract: A method for making an electronic module with an integrated electromagnetic shield uses surface mount shield wall components. At least one electronic component and two or more of the shield wall components are mounted on a surface of a circuit board panel using a pick-and-place process. Each shield wall component has a conductive portion and a non-conductive portion mounted in contact with the surface of the circuit board panel. The mounted shield wall components form a conductive wall to electromagnetically shield the electronic component. The non-conductive portion of one or more of the mounted shield wall components is sawn through, leaving some or all of the conductive portion of the mounted shield wall components. A top conductive shield can be applied. The non-conductive portions can provide stability during a reflow soldering process, while the sacrificial non-conductive portions are sawn through so that they can be removed to reduce the amount of area occupied by the overmoldable shield structure.Type: GrantFiled: June 15, 2009Date of Patent: June 14, 2011Assignee: Skyworks Solutions, Inc.Inventors: Philip H. Thompson, Larry D. Pottebaum