Abstract: Provided are a multi-layer interconnection structure and a manufacturing method thereof. The multi-layer interconnection structure includes a substrate; a first wiring on the substrate; an interlayer insulation layer on the first wiring; a second wiring on the interlayer insulation layer; and a via contact including at least one conductive filament penetrating through the interlayer insulation layer between the second wiring and the first wiring to be electrically connected to the first wiring and the second wiring.

Abstract: A solder layer, a substrate for device joining utilizing the same and a method of manufacturing the substrate are provided whereby the device joined remains thermally unaffected, an initial bonding strength in solder joint is enhanced and the device can be soldered reliably. The solder layer formed on a base substrate (2) consists of a plurality of layers (5a) of a solder free from lead, which are different in its phase from one another. They are constituted by a layer of a phase that is completely melted, and a layer of a phase that is not completely melted at a temperature not less than a eutectic temperature of the solder. The solder layer (5) can be applied to a device joining substrate (1) comprising an electrode layer (4) formed on the base substrate (2) and the solder layer (5) formed on the electrode layer.

Abstract: A method of fabricating a printed-wiring board, includes: forming a through-hole across a thickness of a printed-wiring board, the forming of the through-hole including forming a first opening part having a first diameter, forming a second opening part having a second diameter, and forming a third opening part provided between the first opening part and the second opening part, wherein the second diameter is larger than the first diameter, and the third opening part is formed in a tapered shape whose diameter decreases toward the first opening part from the second opening part.

Abstract: A method is described for manufacturing a flexible electronic product, the method comprising the steps of—providing (S1) a flexible foil (10; 110) with a first and a second, mutually opposite main side (11, 12; 111, 112),—placing (S2) a component (30; 130) at the first foil at the first main side (11; 111), the component having at least one electrical terminal (31; 131) facing towards the second main side (12; 112)—estimating (S3) a position of the at least one electrical terminal (131),—adaptively forming (S4) a conductive path (40A, 40B, 40C) to the at least one electrical terminal, based on said estimated position.

Abstract: The invention offers a board-connecting structure that can provide electrodes with a fine pitch and that can combine the insulating property and the connection reliability. The structure of connecting printed wiring boards 10 and 20 electrically connects a plurality of first electrodes 12 and 13 provided to be adjacent to each other on a first board 11 with a plurality of second electrodes 22 and 23 provided to be adjacent to each other on a second board 21 through an adhesive 30 that contains conductive particles 31 and that has anisotropic conductivity. By heating and pressing the adhesive placed between the mutually facing first electrode 12 and second electrode 22 and between the mutually facing first electrode 13 and second electrode 23, an adhesive layer 30a is formed between the first board 11 and the second board 21 and in the adhesive layer 30a, a cavity portion 33 is formed between the first electrodes 12 and 13 and between the second electrodes 22 and 23.

Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 ?m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 ?m.

Abstract: A portable device includes a substrate, a number of electronic components, and a battery having an anode and a cathode for energizing at least some of the components. The application further relates to a method of protection a portable device against corrosion and to the use of a portable device. An object of the present application is to protect selected metallic parts of a bodyworn electronic device against corrosion in a flexible and controlled manner. The problem is solved in that the portable device includes a sacrificial anode in the form of a component adapted to be surface mounted on the substrate. This has the advantage that corrosion can be contained at a specific location. The device may e.g. be used for portable listening devices, e.g. hearing aids or headsets or earphones including a part adapted for being worn at or in an ear of a user.

Abstract: The invention relates to a method to conductively connect an electrical component with at least one conductive layer, whereby the conductive layer is applied to a substrate which is essentially transparent in the visible wavelength zone of light, comprising the following steps: the electrical component or the conductive layer is provided with a soldering material in the area where the component is to be connected to the conductive layer; the soldering material is provided with energy supplied by an energy source, such that the soldering material melts and a non-detachable, material-bonded conductive connection between the electrical component and the conductive layer is established.

Abstract: The disclosure relates to a component carrier or printed circuit board for electronic components. According to embodiments, a component carrier may include a first contact face for a contact to a first component, a second contact face for a contact to a second component as well as a conductor track that electrically couples the first and the second contact face. The conductor track may include a conductor recess along the conductor track extending through the printed circuit board. An electric conductor may be arranged in the conductor recess extending over the entire course thereof and electrically coupled to the conductor track.

Abstract: A method of producing a wiring substrate includes producing a substrate body including a first primary surface on which a semiconductor chip mounting area is provided and a second primary surface opposed to the first primary surface; attaching a stiffener member on the first primary surface, the stiffener member including an opening which the semiconductor chip mounting area is exposed from; and connecting lead pins to corresponding connection pads provided on the second primary surface by way of electrically conductive members.

Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.

Abstract: A manufacturing method of a semiconductor device include forming a capacitor by forming an oxide film on a surface of a valve metal based on anodic oxidization and by forming a conductive part made of a conductive material on the oxide film; adhering the capacitor on a semiconductor element mounted on a supporting substrate; and coupling the capacitor to the supporting substrate via an outside connection terminal.

Abstract: A cooling device for cooling electronic components includes a base plate, a power source, and a cooling module. The cooling module includes a cooling sheet and a thermal conductive base. The cooling sheet includes a hot surface and a cooling surface. The thermal conductive base is located above the cooling surface of the cooling sheet, and configured to support electronic components on a printed circuit board and transfer heat between the electronic components and the cooling surface. When the cooling sheet is powered on, the cooling surface is in a constant state of low temperature. Due to the heat transfer between the cooling surface and the thermal conductive base, heat from the electronic components can be transferred from the thermal conductive base to the cooling surface continuously.

Abstract: Methods of fabricating a base layer circuit structure are provided. One fabrication method includes: providing an alignment carrier having a support surface; forming a plurality of electrically conductive structures above the support surface of the alignment carrier; disposing a structural material around and physically contacting the side surfaces of the electrically conductive structures formed above the support surface, the structural material having an upper surface coplanar with or parallel to the upper surface of one or more of the electrically conductive structures; exposing, if covered, the upper surfaces of the electrically conductive structures to facilitate electrical connection to the structures; and separating the alignment carrier from the base layer circuit structure. The base layer circuit structure includes the plurality of electrically conductive structures and the structural material surrounding and physically contacting the electrically conductive structures.

Abstract: Disclosed is a one-pack type epoxy resin composition containing an epoxy resin, dicyandiamide, an epoxy resin adduct compound, and a non-latent imidazole compound. The one-pack type epoxy resin composition is capable of being cured at a low temperature, while having excellent heat resistance and sealing properties. Also disclosed is use of the one-pack type epoxy resin composition.

Abstract: A process for manufacturing an electronic module including a printed-circuit board, at least one first-type component and one second-type component is disclosed. The process involves placing solder on the board, putting the first-type component in a first position, heating the entire board to melt the solder, resulting in soldering of the first-type component, putting the second-type component in a second position such that the second-type component has leads bearing on the board via the solder, and heating the solder locally to melt the solder such that the second-type component is soldered by applying two electrodes on each lead of the second-type component and making an electrical current flow between the electrodes to heat each lead of the second-type component. Each of the two electrodes directly contacts each lead of the second-type component to make the current flow between the two electrodes via the corresponding lead of the second-type component.

Abstract: An arrangement including an electrical conductor track carrier and a component applied on the conductor track carrier. The component is a fiber-optoelectronic component and has: a housing, at least one electro-optical or optoelectronic component, at least one fiber-optic interface connected to the electro-optical or optoelectronic component, and at least one electrical interface for connecting the component on the conductor track carrier. The electrical interface has at least one bent electrical soldering connection element which is attached by one end to a base connection section of the housing base and extends from there laterally toward the outside so that the other end of the soldering connection element projects laterally and is soldered laterally outside the outer housing contour on the conductor track carrier. The soldering connection element is bent away from the base connection section so that the base connection section is at a distance from the conductor track carrier.

Abstract: The invention relates to a method for producing an electrical circuit. A prefabricated substrate is provided, said substrate having a first and a second conductor layer and having a dielectric between the first and the second conductor layers. According to the invention, the first conductor layer is multiple times thicker than the second conductor layer. At least one component to be cooled is mounted on the first conductor layer of the prefabricated substrate, forming a heat-transferring connection between the component and the first conductor layer. The invention further relates to an electrical circuit produced in said manner. According to the invention, the electrical circuit comprises a prefabricated substrate which is produced having a first and a second conductor layer and a dielectric located therebetween. According to the invention, the first conductor layer is multiple times thicker than the second conductor layer. At least one component to be cooled is mounted on the first conductor layer.

Abstract: A circuit assembly (34) resistant to high-temperature and high g centrifugal force is disclosed. A printed circuit board (42) is first fabricated from alumina and has conductive traces of said circuit formed thereon by the use of a thick film gold paste. Active and passive components of the circuit assembly are attached to the printed circuit board by means of gold powder diffused under high temperature. Gold wire is used for bonding between the circuit traces and the active components in order to complete the circuit assembly (34). Also, a method for manufacturing a circuit assembly resistant to elevated temperature is disclosed.

Abstract: A method for manufacturing a printed circuit board, including providing a core substrate having an electronic component accommodated in the core substrate; forming a positioning mark on the core substrate; forming an interlayer insulating layer over the core substrate, the positioning mark and the electronic component; forming a via hole opening connecting to the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate; and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the electronic component.

Abstract: An illumination device includes a base, a flexible circuit board disposed on the base, and a plurality of illumination units. The flexible circuit board has a plurality of first branches and at least one second branch which are connected together. Each of the first branches has a radius of curvature, and the radii of curvature of the first branches are different from or identical to one another, so that the first branches are assembled to form a curved surface. The second branch extends from one of the first branches. After the first branches are assembled, the second branch is overlapped with another first branch. The illumination units are packaged onto the first branches of the flexible circuit board. Here, the illumination units located on one of the first branches is electrically connected to the illumination units located on another of the first branches through the second branch.

Abstract: The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.

Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.

Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.

Abstract: An RF shield formed of RF opaque material that permits access to components on a printed circuit board is described. The RF shield can include a first portion attached to the PCB and a removable top portion attached to the first portion at an interface. The top portion is removed from the first portion to expose the components on the PCB. In one aspect of the described embodiment, the top portion is peeled away from the first portion. The components are enclosed within the RF shield after the removal of the top portion by attaching and sealing another top portion to the first portion at the interface by, for example, laser attaching the first portion and the other top portion at the interface.

Abstract: Electronic devices may be provided with printed circuits to which integrated circuits and other electrical components may be mounted. A first printed circuit may have a first surface with an array of contact pads arranged in rows and columns. Each column of contact pads may have a series of contact pads separated by gaps. The contact pads in each column may be staggered with respect to the contact pads in adjacent columns such that each contact pad in a given column is horizontally adjacent to associated gaps in the adjacent columns. A component may be mounted to an opposing surface of the printed circuit such that it overlaps one of the gaps between the staggered contact pads. By mounting the component to portions of the first printed circuit that do not overlap the staggered contact pads, the risk of damaging the electrical component during solder reflow operations may be minimized.

Abstract: A resist film is formed on a conductor layer of a two-layered base material composed of a carrier layer and the conductor layer. Next, the resist film is exposed and developed, so that an etching resist pattern is formed. A region of the conductor layer that is exposed while not covered with the etching resist pattern is removed by etching. A conductor pattern is formed by removing the etching resist pattern. Then, an adhesive layer precursor is applied on an entire surface including an upper surface of the conductor pattern. The adhesive layer precursor is exposed and developed, so that an adhesive pattern is formed on the conductor pattern. After that, a base insulating layer is joined onto the conductor pattern with the adhesive pattern sandwiched therebetween. Finally, a carrier layer is separated from the conductor pattern, so that the FPC board is manufactured.

Abstract: A universal silicon interposer system and method to enabling the selective use of multiple proprietary microelectronic devices without the need to substantially alter the end-use application(s). The system may be used in the implementation of three-dimensional (stacked) microelectronics having proprietary contact pin patterns.

Abstract: A method of manufacturing an electrical device that is electrically and mechanically connectable to another electrical device is presented. The electrical device includes a face equipped with contact pads. The method includes applying an adhesive layer on the face equipped with contact pads. The adhesive layer is composed of a substance with adhesive properties. The method further includes creating a plurality of openings through the adhesive layer over each contact pad, and growing, electrolessly or electrochemically, small metal sticks in the areas where the openings have been created to form a plurality of conductive paths over each contact pad, the volume of which is defined by the openings.

Abstract: In an exemplary method a piezoelectric wafer is prepared on which multiple piezoelectric frames are formed. Each frame has a piezoelectric vibrating piece including excitation electrodes, and a frame portion surrounds the vibrating piece. A lid wafer is prepared on which multiple respective lids are formed, each sized substantially similarly to the respective frames. A base wafer is prepared on which multiple of bases are formed, each sized substantially similarly to the respective frames. Each base has through-holes. Stripes of a first bonding film are formed on both major surfaces of the piezoelectric wafer around the periphery of each frame. Stripes of a second bonding film are formed on the inner major surface of the lid wafer, corresponding to respective stripes of the first bonding film. Stripes of a third bonding film are formed on the inner major surface of the base wafer, corresponding to respective stripes of the first bonding film.

Abstract: Disclosed are an electronic component, an assembly of an electronic component and an electronic carrier substrate, and a method of connecting the electronic component to the carrier substrate. The carrier substrate has a first coefficient of thermal expansion (CTE), and the electronic component has a second CTE. The assembly further comprises a conductive material on the carrier substrate for connecting the electronic component to the carrier substrate, and the electrical component is connected to the carrier substrate by heating and then cooling this conductive material. The electronic component includes an expansion joint to allow the electronic component to expand and contract relative to the carrier substrate during the heating and cooling of the conductive material.

Abstract: A photosensitive conductive film 10 according to the invention includes a support film 1, a conductive layer 2 containing conductive fiber formed on the support film 1, and a photosensitive resin layer 3 formed on the conductive layer 2.

Abstract: A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.

Abstract: In some embodiments, a method removes gold plating on an electronic component. The method includes forming a gold and solder mixture on the electronic component via a first incrementally controlled heating procedure; incrementally cooling the electronic component via a first cooling procedure; wicking part or all of the gold and solder mixture from the electronic component to a metallic screen via a second incrementally controlled heating procedure; and incrementally cooling the electronic component via a second cooling procedure.

Abstract: The present invention relates to a multi-layer laminate or substrate manufacturing process for forming soldering surfaces on a substrate of a module without requiring a solder mask. In one embodiment, a substrate is provided having a substrate body, soldering pads, and a metal segment. A patterned mask is formed over the substrate such that soldering surfaces of the soldering pads remain exposed. The soldering surfaces of the soldering pads are plated to create plated soldering surfaces over the soldering pads. The plated soldering surfaces are the regions for solder placement. The patterned mask is then removed from the substrate. Next, an anti-wetting treatment is applied to the substrate such that any unplated metal surfaces react to the anti-wetting treatment to form treated surfaces. As such, the plated soldering surfaces will wet solder while the treated surface will not wet solder. In a preferred embodiment, the anti-wetting treatment is an oxidation process.

Abstract: An embodiment of an electronic component includes a circuit element disposed within a package, which includes a surface and at least one standoff protruding from the surface. For example, where the circuit element is an inductor in a power supply, the standoff may allow one to mount the inductor component over another component, such as a transistor component. Therefore, the layout area of such a power supply may be smaller than the layout area of a power supply in which the inductor and transistor components are mounted side by side.

Abstract: A method for manufacturing a silicon chip package for a circuit board assembly is provided with a package substrate having a silicon chip and an array of contact pads provided by conductive material. A plurality of conductive springs are affixed to the array of contact pads for providing conductive contact with the corresponding array of contacts on a circuit board assembly.

Abstract: A power board is provided. The power board includes a board housing; a board included in an inside of the board housing; a plurality of parts mounted in the board; and a supporting member configured to be mounted in the board and to support the board to prevent each of the plurality of parts from being damaged. The supporting member includes a supporting member mounted by using a surface mounted technology (SMT) process.

Abstract: It is an object to provide an electronic component mounting system capable of concurrently, efficiently subjecting a plurality of substrates to component mounting operation and accomplishing both high productivity and a capability of addressing production of multiple products. An electronic component mounting system is configured by arranging, on an upstream side of a component loading unit having a plurality of substrate conveyance mechanisms, a screen printer M2 having a plurality of individual printing mechanisms and a coating and inspection machine M4 that applies a coat of a resin for use in boding an electronic component and that inspects a coated state. The coating and inspection machine M4 is equipped with a coating head 15 that performs operation for coating substrates conveyed by substrate conveyance mechanisms 12A and 12B from the screen printer M2 with the resin and an inspection head 16 that performs pre-coating inspection and post-coating inspection.

Abstract: A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.

Abstract: A method for fabricating a ceramic substrate includes: preparing a ceramic substrate; disposing a metal mask having a plurality of holes at an upper side of the ceramic substrate; and injecting a polyimide resin into the holes of the metal mask to form a polyimide thin film on the ceramic substrate. A thin film is formed on a ceramic substrate in a simpler manner, so the fabrication cost can be reduced and a fixed time can be shortened, thus increasing the efficiency of a product.

Abstract: A component is electrically connected to an electrical circuit by a method that comprises forming an intermediate product in which the component (3) is disposed on one side of an electrically conducting sheet (1) so that at least one pair of contacts (4) of the component are electrically connected by the sheet and in which a patterned etch resist layer (2) is disposed on the other side of the sheet in registration with the component on said one side of the sheet, and then exposing the other side of the sheet to an etching agent and thereby removing areas of the sheet to leave the electrical circuit and also to remove the electrical interconnection between the contacts.

Abstract: According to exemplary embodiments, a controlled-depth slot extending into a circuit board is provided. The controlled depth slot may be milled, and may comprise ½ radial plated through-holes to generate a solderable “D” interconnect feature. The slot may include interconnect features on one to five sides. According to another exemplary embodiment, a circuit board having a depth-controlled interconnect slot is provided in conjunction with one or more solderable technology modules. The one or more solderable technology modules may include memory devices, power devices such as Point of Load Supplies (POLS), security devices and anti-tamper devices, capacitance devices, and other types of chips such as Field Programmable Gate Arrays (FPGAs). The solderable technology modules may be soldered into the slot to secure the modules in the slot and connect the modules to interconnects on the circuit board.

Abstract: A fluid cooled light emitting diode and associated lighting unit is disclosed. A fluid, preferably a liquid, cools and stabilizes the p-n junction of the light emitting diode thereby reducing the energy required to power the light emitting diode, lengthening its usable lifetime, and outputting more consistent light. The fluid cools the lens surrounding the light emitting diode, a printed circuit board on which the light emitting diode resides, or other heat transferring elements proximate to the lens of the light emitting diode.

Abstract: In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.

Abstract: A thermal management system/method allowing efficient electrical/thermal attachment of heat sourcing PCBs to heat sinking PCBs using reflow/wave/hand soldering is disclosed. The disclosed system/method may incorporate a combination of support pins, spacer pads, and/or contact paste that mechanically attaches a heat sourcing PCB (and its associated components) to a heat sinking PCB such that thermal conductivity between the two PCBs can be optimized while simultaneously allowing controlled electrical conductivity between the two PCBs. Controlled electrical isolation between the two PCBs is provided for using spacer pads that may also be thermal conductive. Contact paste incorporated in some embodiments permits enhanced conductivity paths between the heat sourcing PCB, a thermally conductive plate mounted over the heat sourcing PCB, and the heat sinking PCB. The use of self-centering support pins incorporating out-gassing vents in some embodiments allows reflow/wave/hand soldering as desired.

Abstract: A circuit module can include a substrate, photonic conversion units placed on the substrate; and a retention assembly. The retention assembly can include a heat sink in thermal contact with the photonic conversion units and a fastener. The fastener can be mechanically coupled to both the substrate and the heat sink, and configured to press the heat sink against the photonic conversion units. The plurality of photonic conversion units are removably secured to the substrate by the retention assembly without the use of a bonding material.

Abstract: A substrate with spring terminals includes a substrate including a connection pad, a spring terminal whose connection portion is connected to the connection pad by a solder layer, and a resin portion formed to cover a side surface of the solder layer, thereby the failure that the spring terminal falls down is prevented.

Abstract: A method for mounting a component to an electric circuit board (10), comprising: providing at least one cavity in the electric circuit board; arranging the component in the at least one cavity; and generating in the at least one cavity mechanical and/or electrical connections simultaneously to at least two locations of the component. A method for making an electric circuit board arrangement comprising at least one electric circuit board, comprising: providing at least one cavity and/or through-hole in the at least one electric circuit board; arranging the component in the at least one cavity and/or in a through-hole, the component being mechanically and/or electrically connectable by contact in the at least one cavity and/or through-hole; and stacking one or more electric circuit boards on top of the at least one electric circuit board and coupling the electric circuit boards by solderable terminal pads of the component.

Abstract: A method for making an assembly of chips equipped with radiofrequency transmission-reception means, including successively: making a plurality of chips, on a substrate, each chip having at least one reception area, connecting the reception areas of the chips of the assembly in series with an electrically insulating flat ribbon having a plurality of metallic patterns electrically insulated from one another, each pattern forming at least a part of a flat antenna electrically connected at the level of at least one connection area of the antenna to a corresponding reception area, and separating the chips at the level of the substrate, the chips being mechanically connected to one another by the ribbon.