Assembling Terminal To Base Patents (Class 29/842)
  • Patent number: 7658772
    Abstract: The present invention is a process for making a matching pair of surfaces, which involves creating a network of channels on one surface of two substrate. The substrates are then coated with one or more layers of materials, the coating extending over the regions between the channels and also partially into the channels. The two coated surfaces are then contacted and pressure is applied, which causes the coatings to be pressed into the network of channels, and surface features on one of the layers of material creates matching surface features in the other, and vice versa. It also results in the formation of a composite. In a final step, the composite is separated, forming a matching pair of surfaces.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: February 9, 2010
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Stuart Harbron
  • Patent number: 7653991
    Abstract: A method for manufacturing a printed circuit board having an embedded component is disclosed. The method includes: forming at least one contact bump and at least one electrode bump on one side of a base substrate; mounting the component such that the electrode bump is in correspondence with a contact terminal of the component; stacking an insulation layer, in which an opening is formed in correspondence to the component, on the one side of the base substrate, such that the contact bump penetrates the insulation layer; filling a filler in the opening; and stacking a metal layer on the insulation layer. Using the method, the reliability of circuit connections between the component and the circuit patterns can be improved, and the manufacturing process can be reduced in embedding the component in the printed circuit board.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: February 2, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee-Soo Mok, Jun-Heyoung Park, Ki-Hwan Kim, Sung-Yong Kim
  • Publication number: 20100018050
    Abstract: A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 28, 2010
    Inventors: Benjamin J. Feldman, Adam Heller, Ephraim Heller, Fei Mao, Joseph A. Vivolo, Jeffery V. Funderburk, Fredric C. Colman, Rajesh Krishnan
  • Publication number: 20100018051
    Abstract: A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 28, 2010
    Inventors: Benjamin J. Feldman, Adam Heller, Ephraim Heller, Fei Mao, Joseph A. Vivolo, Jeffery V. Funderburk, Fredric C. Colman, Rajesh Krishnan
  • Patent number: 7647695
    Abstract: An OCR system for matching wire harnesses and connectors facilitates precise registration of wire number strings, uses geometric modeling for character recognition, and restricts searches by region and character to ensure speed and accuracy. A string location algorithm is used to search for and identify the location of the beginning of a wire number string. The horizontal edges of the wire in the image are located, a diameter of the wire is determined, light intensity is confirmed, and the first character is found. The resulting coordinate is used by the algorithm for character definition. Geometric shapes are used for identification in order to overcome twisted wires, poorly printed markings, ink color variations, and contacting characters.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: January 19, 2010
    Assignee: Lockheed Martin Corporation
    Inventors: William Phillip MacNutt, Richard A. Malleck
  • Publication number: 20100006333
    Abstract: Provided is a wiring substrate which enables wiring density to be increased and enables transmission speed of signals to be adjusted without making a design change of wirings. A wiring substrate 100 is provided with a first terminal 110, a second terminal 120, a first wiring 112 and a second wiring 114. The first wiring 112 is such that one end thereof is connected to the first terminal 110, and is formed on the wiring substrate 100. The second wiring 114 is such that one end thereof is connected to the second terminal 120, and is formed on the wiring substrate 100. One end of each of a plurality of third wirings formed on the wiring substrate 100 is connected to the other end of the first wiring 112, and one end of each of a plurality of fourth wirings formed on the wiring substrate 100 is connected to the other end of the second wiring 114. The other end of at least one third wiring and the other end of at least fourth wiring are connected together.
    Type: Application
    Filed: July 6, 2009
    Publication date: January 14, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Nobuhiko Ishizuka
  • Patent number: 7644495
    Abstract: Electrical interfaces formed into a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is between about 20% and 50% of the weight of the conductive loaded resin-based material. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, or the like.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: January 12, 2010
    Assignee: Integral Technologies, Inc.
    Inventor: Thomas Aisenbrey
  • Patent number: 7644497
    Abstract: To provide a component built-in wiring board and a manufacturing method thereof capable of further improving component mounting density without deteriorating-reliability.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: January 12, 2010
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Tatsuro Imamura, Yuji Yamaguchi, Kazuhiro Shinozaki, Satoshi Shibazaki, Yoshitaka Fukuoka, Hiroyuki Hirai, Osamu Shimada, Kenji Sasaoka, Kenichi Matsumura
  • Publication number: 20100000085
    Abstract: A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
    Type: Application
    Filed: March 13, 2008
    Publication date: January 7, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 7640647
    Abstract: Projecting elongate stub walls are provided on the planar surfaces of a substrate at positions where bonding of the substrate to a clamping lid or base is to be carried out. On firing of the substrate, the surfaces thereof are mechanically processed but since the stub walls protrude from the substrate, the grinding and polishing tools make contact with the surfaces of these stub walls, rather than with the entire substrate surface. As a result, the area of the substrate to be processed is minimised and problems with dishing and erosion are alleviated. This allows the clamping lid, or frame to be bonded, using conventional conductive adhesive processes, avoiding the cracking and stress problems associated with non-uniformity of the surface of the ceramic substrates.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 5, 2010
    Assignee: Astrium Limited
    Inventor: Simon Leonard Rumer
  • Patent number: 7640658
    Abstract: A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: January 5, 2010
    Assignee: Teledyne Technologies Incorporated
    Inventors: Cuong V. Pham, David E. Chubin, Robert A. Clarke, Aaron D. Kuan
  • Publication number: 20090320281
    Abstract: Embodiments of an apparatus and methods of forming a package on package interconnect and its application to the packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 31, 2009
    Inventors: Leonel Arana, Rob Nickerson, Lim Chong Sim, Edward Prack, Yoshihiro Tomita
  • Patent number: 7637007
    Abstract: An approach for fabricating cantilever probes for a probe card assembly includes forming posts on conductive traces on a substrate. A beam panel having beam elements formed therein is aligned to the substrate so that the beam elements are in contact with the plurality of posts. Each beam element is in contact with a post at a portion of the beam element so that both a first end portion and a second end portion overhang the post element. Each beam element is also attached to the beam panel by the first end portion. The beam elements are bonded to the plurality of posts. The first end portion of each beam element is cut, for example using an electrode, laser ablation or by dicing, to release the beam element from the beam panel. The beam panel is then removed, leaving the beam elements attached to the posts.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: December 29, 2009
    Assignee: SV Probe Pte. Ltd.
    Inventors: Bahadir Tunaboylu, Horst Clauberg, Mark Cunningham, Senthil Theppakuttai, John McGlory
  • Patent number: 7637004
    Abstract: A method for manufacturing an electronic device includes: preparing an electronic component having an electrode; fixing the electronic component to a supporter, the supporter having a support surface and an inlet disposed in a position that is at a side of the support surface and lower than the support surface, by supporting the electronic component with the support surface so that the electronic component does not come into contact with the inlet and so that a part of a surface of the electronic component adjacent to the support surface is exposed out of the support surface and by attracting a region of the electronic component exposed out of the support surface toward the inlet; and electrically coupling the electrode and a conductive pattern with the electronic component fixed to the supporter.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 29, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shingo Kuroda
  • Publication number: 20090314538
    Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 24, 2009
    Inventors: Houssam Jomaa, Omar J. Bchir
  • Publication number: 20090314519
    Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Javier Soto, Charan Gurumurthy, Robert Nickerson, Debendra Mallik
  • Patent number: 7631423
    Abstract: A method is provided for fabricating a multilayer printed circuit board, including embedded electrically conductive elements formed as part of the fabrication of the layers of the printed circuit board. An insulating layer and a conductive layer are then pressed over the electrically conductive elements such that the electrically conductive elements protrude from the surface of the conductive layer. A mechanical process is the applied to remove these protrusions to expose the embedded electrically conductive elements. An electrically conductive undercoat may be applied over the surface of the conductive layer and a second circuit pattern is formed over the electrically conductive undercoat.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: December 15, 2009
    Assignee: Sanmina-Sci Corporation
    Inventors: Lim Siong San, Neo Mok Choon, Kevin Lim, Kelvin Yeow, Tan Kwang Chiah
  • Patent number: 7631414
    Abstract: Methods for assembling an active array system are described. In one exemplary embodiment, an active subarray panel assembly having a first surface with a first array of electrical contacts and a radiator aperture with an array of radiator structure and an aperture mounting surface with a second array of electrical contacts are assembled together. The first surface of the panel assembly and the aperture mounting surface of the radiator aperture are brought into contact with an adhesive layer including microwave interconnects in a pattern corresponding to the first array of electrical contacts and the second array of electrical contacts so that the adhesive layer is between the first surface of the panel assembly and the aperture mounting surface of the radiator aperture. Pressure, heat and vacuum are applied to cure the adhesive and complete engagement of the microwave interconnects.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: December 15, 2009
    Assignee: Raytheon Company
    Inventors: Avery Y. Quil, Clifton Quan, Alec Ekmekji, Jason G. Milne
  • Publication number: 20090300913
    Abstract: A method is for connecting a tab pattern formed on a base sheet and a lead wire, wherein the tab pattern includes: a tab main portion; and a connecting portion formed to continue from one edge line of the tab main portion and to extend from the tab main portion along an extension line that is substantially orthogonal to the edge line, and wherein the method includes: connecting the lead wire on the tab main portion by bonding the lead wire at a position being displaced from the extension line of the connecting portion for more than a given offset amount where the extension line is identical to a center line of the connecting portion, the position being within a given distance from the edge line of the tab main portion.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 10, 2009
    Applicant: Minebea Co., Ltd.
    Inventors: Eiji Misaizu, Makoto Hiramoto
  • Patent number: 7627946
    Abstract: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a portion of the conductive film in an electrically connecting pad area intended for the circuit layer; removing a portion of the conductive film not covered with the resist; forming another resist on the substrate to cover a portion of the conductive film residually exposing from the resist; electroplating nickel/gold on at least one electrically connecting pad on the substrate such that the electrically connecting pad is electroplated with a nickel/gold layer; removing the resists and the conductive film thereunder; and forming a solder mask on the substrate, wherein the electrically connecting pad electroplated with the nickel/gold layer is exposed from the solder mask.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: December 8, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Pao-Hung Chou
  • Patent number: 7621044
    Abstract: Resilient spring contact structures are manufactured by plating the contact structures on a reusable mandrel, as opposed to forming the contact structures on sacrificial layers that are later etched away. In one embodiment, the mandrel includes a form or mold area that is inserted through a plated through hole in a substrate. Plating is then performed to create the spring contact on the mold area of the mandrel as well as to attach the spring contact to the substrate. In a second embodiment, the mandrel includes a form that is initially plated to form the resilient contact structure and then attached to a region of a substrate without being inserted through the substrate. Attachment in the second embodiment can be achieved during the plating process used to form the spring contact, or by using a conductive adhesive or solder either before or after releasing the spring contact from the mandrel.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: November 24, 2009
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gaetan L. Mathieu
  • Patent number: 7621041
    Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: November 24, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Sounak Banerji, G. Sidney Cox, Karl Hartmann Dietz
  • Publication number: 20090282674
    Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.
    Type: Application
    Filed: December 29, 2008
    Publication date: November 19, 2009
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
  • Patent number: 7617601
    Abstract: The present invention generally relates to a method for forming a flat panel for an X-ray detector device. The method comprises forming an active area of a first size on a substrate of a second size and extending at least one contact of the active area. The method further comprises trimming the substrate to the first size forming the flat panel.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: November 17, 2009
    Assignee: General Electric Company
    Inventors: Jeffrey A. Kautzer, Richard Aufrichtig, John French
  • Patent number: 7614148
    Abstract: Cable connection unions are rapidly replaced in a universal seismic data acquisition-module without opening a main electronic circuitry protective chamber. Different connector types required for the many data transmission cable designs needed to service a wide range of survey conditions are more easily accommodated without exposing primary circuitry to the elements.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: November 10, 2009
    Assignee: Geo-X Systems, Ltd
    Inventor: Donald G. Chamberlain
  • Patent number: 7614128
    Abstract: While a piezoelectric element is being formed by sequentially laminating a lower electrode whose uppermost layer is made of iridium, a titanium layer, a piezoelectric layer and an upper electrode to each other on a substrate, the piezoelectric layer is formed, by an MOD method, on the titanium layer with an contact angle of water to the surface thereof which is no less than 40°.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: November 10, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Kamei
  • Patent number: 7607223
    Abstract: An electro-fluidic interconnection. The interconnection includes a body (200) formed of a ceramic material. The body (200) is provided with an aperture (206) having a profile suitable for receiving an interconnecting conduit (400). The interconnecting conduit (400) can be formed of the same type of ceramic material as the body (200). The conduit (400) is defined by an outer shell (403) with a hollow bore (402) for transporting a fluid. A mating portion (404) of the conduit has an exterior profile that matches the profile of the aperture. Moreover, the mating portion (404) of the conduit (400) can be compression fitted within the aperture (206). Conductive traces (406, 208) on the conduit and the body can be electrically connected to complete the electro-fluidic interconnection.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: October 27, 2009
    Assignee: Harris Corporation
    Inventors: Mihael Pleskach, Paul Koeneman, Carol Gamlen, Steven R. Snyder
  • Patent number: 7603769
    Abstract: Methods of coupling a surface mount device with a substrate such as a printed circuit, for example, are disclosed. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed there between, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventor: My Jang
  • Patent number: 7600315
    Abstract: This invention relates to a method of manufacturing a printed circuit board, in which a dummy metal frame enclosing the outer periphery of a product part is formed, thus simultaneously assuring the rigidity of the printed circuit board and minimizing the warping thereof thanks to the dummy metal frame left in place on a finished product, thereby realizing a structure compatible with conventional flip chip mounting lines.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 13, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Takayuki Haze
  • Patent number: 7596864
    Abstract: A method for soldering a soft wire to a printed circuit board conveniently includes the following step: providing a bracket having a through hole and an enameled wire; fastening the enameled wire to the bracket with the conductive wire crossing over the through hole; providing a printed circuit board formed with conductive pads thereon and setting the printed circuit board onto the bracket with the pad aligned to the through hole so that a portion of the magnet wire crossing the through hole lies on the conductive pad; providing a soldering tool having a thermal contact portion and inserting the thermal contact portion into the through hole to solder the magnet wire to the conductive pad.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: October 6, 2009
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: John Chow, Huan Chen, Chih-Min Lin
  • Publication number: 20090231788
    Abstract: Electrical communication between an information handling system chassis having a non-conductive surface and processing components within the chassis is established through the non-conductive surface with conductive elements extending from a conductive pad. A protruding element extending from a conductive pad engages the conductive elements through the non-conductive surface when the protruding element is coupled to a cavity formed in the chassis. Alternatively, the protruding element extends from the chassis to couple to a cavity in the conductive pad. Processing components have electrical communication with the chassis through the conductive pad.
    Type: Application
    Filed: February 21, 2008
    Publication date: September 17, 2009
    Inventors: Chase Berry, Gary Thomason, James Utz, Steven L. Williams, Jorge C. Marcet
  • Publication number: 20090229860
    Abstract: The present invention relates to a green sheet for multi-layered electronics parts and a manufacturing method of a green chip using the same. The present invention provides a green sheet for multi-layered electronics parts including a green sheet; and an internal electrode formed on the green sheet and having a gap formed therein. Further, the present invention provides the manufacturing method of the green chip using the green sheet for the multi-layered electronics parts.
    Type: Application
    Filed: May 12, 2008
    Publication date: September 17, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Joo Shin, Young Woo Lee, Jeong Min Cho
  • Patent number: 7589398
    Abstract: A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches are formed into the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can be very accurately controlled.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: September 15, 2009
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner, Nozad Osman Karim
  • Publication number: 20090224785
    Abstract: Devices and methods for providing, making, and/or using an electronic apparatus having a wall structure adjacent a resilient contact structure on a substrate. The electronic apparatus can include a substrate and a plurality of electrically conductive resilient contact structures, which can extend from the substrate. A first of the contact structures can be part of an electrical path through the electronic apparatus. A first electrically conductive wall structure can also extend from the substrate, and the first wall structure can be disposed adjacent one of the contact structures. The first wall structure can be electrically connected to a return current path within the electronic apparatus for an alternating current signal or power on the first contact structure.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Inventors: Keith J. Breinlinger, Benjamin N. Eldridge, David P. Pritzkau
  • Patent number: 7578057
    Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: August 25, 2009
    Assignee: FormFactor, Inc.
    Inventors: Mohammad Eslamy, David V. Pedersen, Harry D. Cobb
  • Publication number: 20090188108
    Abstract: Techniques for producing a flexible structure attached to a device. One embodiment includes the steps of providing a first substrate, providing a second substrate with a releasably attached flexible structure, providing a bonding layer on at least one of the first substrate and the flexible structure, adjoining the first and second substrate such that the flexible structure is attached at the first substrate by means of the bonding layer, and detaching the second substrate in such a way that the flexible structure remains on the first substrate.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 30, 2009
    Inventors: Roger Dangel, Laurent Dellmann, Michel Despont, Bert Jan Offrein, Stefano Sergio Oggioni
  • Patent number: 7565725
    Abstract: A method for forming a variable capacitor including a conductive strip covering the inside of a cavity, and a flexible conductive membrane placed above the cavity, the cavity being formed according to the steps of: forming a recess in the substrate; placing a malleable material in the recess; having a stamp bear against the substrate at the level of the recess to give the upper part of the malleable material a desired shape; hardening the malleable material; and removing the stamp.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 28, 2009
    Assignees: STMicroeectronics S.A., Commissariat a l'energie Atomique
    Inventors: Guillaume Bouche, Fabrice Casset, Pascal Ancey
  • Publication number: 20090174423
    Abstract: A probe card assembly includes a substrate and a plurality of probes bonded to a surface of the substrate. The probe card assembly also includes a reinforcing layer provided on the surface of the substrate. The reinforcing layer is in contact with a lower portion of each of the probes, where a remaining portion of each of the probes is free from the reinforcing layer. The reinforcing layer may be a composite reinforcing layer that includes multiple layers of material to achieve a particular result. According to one embodiment of the invention, the reinforcing layer includes a powder layer disposed on the substrate and an adhesive layer formed on the powder layer. The composite reinforcing layer may be compliant to allow the probes to flex and move as intended, without limiting deflection capability. The composite reinforcing layer may be removable to allow access to probes for repair.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 9, 2009
    Inventors: Peter J. Klaerner, Son N. Dang, Pastor Yanga, Gerald W. Back, Victor Golubic, Bahadir Tunaboylu
  • Patent number: 7555834
    Abstract: Methods of manufacture of interconnection devices that include using a non-forming process to manufacture a plurality of compression contacts, each compression contact including a cantilevered beam portion that is tapered along its length, and disposing each of the plurality of contacts within a respective cavity in a substantially planar carrier housing lying in a plane defined by x and y axes, the housing having an upper surface and a lower surface, each cavity extending between the upper and lower surfaces of the housing substantially along a z axis, each contact being loosely retained within its respective cavity such that an entirety of the contact in a compressed state has at least some freedom of movement along the x and y axes.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: July 7, 2009
    Assignee: Integrated System Technologies, LLC
    Inventor: Michael N. Perugini
  • Patent number: 7552532
    Abstract: A method is provided to produce a hermetic encapsulation for an electronic component, which may be an optical and at least partially light-permeable component or a surface wave component, comprises attaching and electrically contacting a component based on a chip to a carrier comprising electrical connection surfaces, such that a front of the chip bearing component structures facing the carrier is arranged to clear it, covering a back of the chip with a film made of synthetic material, such that edges of the film overlap the chip; tightly bonding the film and carrier in an entire edge region around the chip; structuring the film such that the film is removed around the edge region in a continuous strip parallel to the edge region; and applying a hermetically sealing layer over the film, such that this layer hermetically terminates with the carrier in a contact region outside of the edge region.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: June 30, 2009
    Assignee: EPCOS AG
    Inventors: Alois Stelzl, Hans Krueger, Gregor Feiertag, Ernst Christl
  • Publication number: 20090158584
    Abstract: A termination for a multi-conductor cable is made by providing a metal structure that includes a plurality of parallel but spaced apart fingers that are joined together by a connecting member adjacent at least one end of each finger. Each of the conductors in the cable is connected to a respective one of the fingers at a location that is spaced from the connecting member. The cable and the fingers are then over-molded with an insulating material where the conductors are connected to the fingers. This over-molding leaves a portion of the length of each finger exposed. The connecting member is then severed and removed.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Inventor: Christopher D. Prest
  • Publication number: 20090151159
    Abstract: The present invention relates to a method for arranging a plurality of connecting elements corresponding to a plurality of electronic components which is required to be subject to an electric test for inspecting a fault. The method for arranging a plurality of connecting elements on electronic substrates such that the connecting elements may simultaneously contact with a plurality of electronic components comprises the steps of fabricating each connecting element to have the first extending region at one end extended in a certain direction with a regular width and the second extending region at the other end extended in a certain direction with a regular width; and coupling the first extending region of each connecting element to a fixing post formed in a pre-determined region of the electronic substrate in order to be parallel with the second extending region of each connecting element, wherein each of the second extending region extends at the same length.
    Type: Application
    Filed: April 16, 2008
    Publication date: June 18, 2009
    Applicant: PHICOM Corporation
    Inventor: Oug-Ki LEE
  • Publication number: 20090151156
    Abstract: A method of manufacturing a circuit board assembly for a controller. The method includes providing first and second printed circuit boards wherein the first printed circuit board has a plurality of copper pads containing slots therein that correspond to a plurality of power tabs in the second printed circuit board. The power tabs are then slid into the slots and the tabs are flooded with copper. At this time the power tabs are soldered within the slots to provide an electrical connection between the first and second printed circuit boards that allows for the transfer of current between the boards of more than three amps.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: SAUER-DANFOSS INC.
    Inventors: Xiao YAN, Thomas J. BERGHERR
  • Publication number: 20090151158
    Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.
    Type: Application
    Filed: February 13, 2009
    Publication date: June 18, 2009
    Inventors: Deepak K. Pai, Ronald R. Denny
  • Patent number: 7543372
    Abstract: Disclosed is a method for forming electrical interconnections between railroad track components and signal conductors/lines. In one arrangement, an electrically conductive adhesive is utilized to electrically interconnect a signal conductor to a railroad track component. In another arrangement, a clamp is utilized in conjunction with the electrically conductive adhesive that forms the electrical interconnection. The clamp maintains the signal conductor in direct contact with the surface of the railroad track component while the electrically conductive adhesive cures. In these arrangements, the use of the electrically conductive adhesive allows for making an electrical connection with a railroad component without penetrating the structure of that component. In a further arrangement, a hollow tubular connector is utilized to electrically connect two signal conductors associated with railroad track components.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: June 9, 2009
    Assignee: Fastrax Industries, Inc.
    Inventor: David L. Reichle
  • Publication number: 20090133900
    Abstract: Circuit board having conductor wiring and connection terminal; anisotropic conductive resin layer provided on one surface of circuit board; and plurality of electronic components respectively provided with electrode terminals in positions facing the connection terminal are included. The anisotropic conductive resin layer includes at least one kind of conductive particles selected from coiled conductive particles, fiber fluff conductive particles and conductive particles provided with a plurality of conductive protrusions, and resin binder; electrically couples electrode terminals of plurality of electronic components to connection terminals to each other with conductive particles; mechanically fixes electronic components and circuit board to each other; and protects conductor wiring.
    Type: Application
    Filed: April 14, 2006
    Publication date: May 28, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kazuhiro Nishikawa, Hidenori Miyakawa, Norihito Tsukahara, Shigeaki Sakatani
  • Patent number: 7538413
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated circuit, and a through interconnect in physical and electrical contact with the substrate contact configured to provide a signal path to a back side of the semiconductor substrate. The through interconnect includes an opening in the semiconductor substrate aligned with the substrate contact, and a projection on an interposer substrate (or alternately on a second semiconductor substrate) configured for mating physical engagement with the opening in the semiconductor substrate. The projection can also include a conductive via configured for electrical contact with a backside of the substrate contact and with a terminal contact for the component.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree
  • Patent number: 7533460
    Abstract: Systems and methods for operatively connecting processor banks in large computer systems are disclosed herein. In one embodiment, a computer system includes a first bank of processors, a second bank of processors spaced apart from the first bank of processors, and a connector assembly configured to operatively connect at least a portion of the first bank of processors to at least a portion of the second bank of processors. The connector assembly can include a first connector unit having a plurality of first connector sets and a second connector unit having a plurality of corresponding second connector sets. At least one of the first and second connector units is movable relative to the other one of the first and second connector units to at least approximately concurrently engage the plurality of first connector sets with the plurality of corresponding second connector sets.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: May 19, 2009
    Assignee: Cray Inc.
    Inventors: Wade J. Doll, Douglas P. Kelley
  • Patent number: 7534148
    Abstract: A terminal block for use in an uninterruptible power supply comprises a first portion that includes a plurality of stalls, each of the plurality of stalls having an aperture, and at least one socket positioned in the aperture, the at least one socket arranged to accept a wire from internal portions of the uninterruptible power supply, and a second portion removably connectable to the first portion, the second portion including a plurality of stalls, a plurality of electrical ports, an electrical port positioned in each of the plurality of stalls, and at least one connector pin positioned within one of the plurality of stalls to connect to the at least one socket through the aperture.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: May 19, 2009
    Assignee: American Power Conversion Corporation
    Inventors: David Schuttler, John Stranberg, Michael Falcinelli, Srdan Mutabdzija, James Edward Briggs
  • Patent number: 7530164
    Abstract: A method for connecting electronic components, such as, an integrated circuit die and a package substrate, is described. According to one aspect of the invention, a contact pad protective material is applied on one or more of the contact pads on an integrated circuit die. The underfill material is applied to the surface of the die not covered by the contact pad protective material and the underfill material is partially cured in a curing oven. The contact pad material is removed leaving openings over the respective surface of the contact pad. A one or more contacts on a package substrate is inserted into the openings, electronically connecting the contacts to the contact pads.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Paul Koning, Terry Sterrett