By Metal Fusion Bonding Patents (Class 29/843)
  • Patent number: 10340620
    Abstract: An object is to reduce the size of a multi-contact connector having a wiping function. A multi-contact connector includes a front terminal and a rear terminal. The front terminal and the rear terminal are independently housed in one terminal accommodating groove in a housing in such a manner as to separate from each other. Unlike terminals of a multi-contact connector according to the related art, each terminal has no junction where it divides into a front contact and a rear contact. The housing requires no space for accommodating such a junction, and this reduces the size of the multi-contact connector.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 2, 2019
    Assignee: IRISO ELECTRONICS CO., LTD.
    Inventor: Yoshiyuki Ogura
  • Patent number: 10193256
    Abstract: A power supply board bridge connector includes an insulating cover to cover an insulating base which is formed with at least one receiving groove. A bottom of the insulating base is formed with through holes. At least two pins provided beneath the insulating base are mated with insertion holes of two left and right power supply boards so that the insulating base bridges over the two power supply boards. The metallic elastic plate is placed in the receiving groove. The metallic elastic plate has two left and right elastic contacts passing through the through holes at the bottom of the receiving groove to be electrically connected to the left and right power supply boards. The structure is simple, the connection is convenient, firm and stable, and the connection efficiency is high.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 29, 2019
    Assignee: XIAMEN GHGM INDUSTRIAL TRADE CO., LTD.
    Inventor: Bingshui Chen
  • Patent number: 10116072
    Abstract: A printed circuit board assembly having a printed circuit board with at least one footprint for attaching a plug connector, wherein the footprint has three or more coupling points for coupling electrical contacts of the plug connector, and a plug connector attached on the footprint, the plug connector has exactly two signal conductors for transmitting a differential signal, wherein the first signal conductor has a first electrical contact coupled at a first coupling point and the second signal conductor has a second electrical contact coupled at a second coupling point, wherein the second coupling point is not one of the coupling points which is directly adjacent to the first coupling point of the footprint.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 30, 2018
    Assignee: Rosenberger Hochfrequenztechnik GmbH & Co. KG
    Inventors: Martin Zebhauser, Christian Schmidt
  • Patent number: 9935038
    Abstract: Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tsung-Ding Wang, Hung-Jen Lin, Jiun Yi Wu, Mirng-Ji Lii, Chien-Hsun Lee
  • Patent number: 9860975
    Abstract: A printed circuit board (PCB) having a thermal relief pad around at least one via. The thermal relief pad includes at least four thermal cut-outs and at least four conductive bands. The at least four conductive bands are formed between the at least four thermal cut-outs such that adjacent conductive pads are orthogonal to each other. Each pair of mutually opposite conductive bands have substantially equal lengths and each pair of adjacent conductive bands have unequal lengths.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: January 2, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mark Vinod Kapoor, David W. Engler
  • Patent number: 9722336
    Abstract: A circuit board has a socket with at least one plated through-hole. A connector includes a housing that has first and second connector interfaces with, respectively, at least first and second connector contacts. The first connector interface opens into an interior of the housing such that there is a vapor path through the first connector interface and the interior of the housing to the second connector contact at the second connector interface. A resilient seal is located at the first connector interface. The first connector contact extends through the resilient seal and into the plated through-hole. The resilient seal intimately seals around the first connector contact and provides a barrier at the first connector interface into the vapor path.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 1, 2017
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, John A. Dickey, Christian Miller, Kevin Case Fritz
  • Patent number: 9681537
    Abstract: The invention relates to a process for manufacturing a power circuit board in which, on the one hand, a printed circuit board including an insulating substrate and a conductive track on one of the sides of the substrate, and on the other hand, a bus bar element, are provided. The bus bar element is welded to the conductive track using a laser. In order to make it possible to produce the weld by laser welding, even with a relatively thick bus bar, the welding is carried out in a zone that is thinner relative to the maximum thickness of the bus bar. Thus, a printed circuit board is obtained with a bus bar having a thick zone for conducting high currents and a thinner zone in order to allow the bus bar to be welded to the conductive track by laser welding.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: June 13, 2017
    Assignee: Delphi France SAS
    Inventors: Jerome Petitgas, Rene Slezak
  • Patent number: 9570825
    Abstract: A substrate terminal includes at least one substrate connection portion that is inserted into a hole portion in a substrate from one surface side of the substrate and is soldered together with the hole portion, a terminal connection portion into which an opposite-side terminal is inserted in a direction same as an insertion direction of the substrate connection portion into the hole portion and that is connected to the opposite-side terminal, an intermediate portion that connects the substrate connection portion and the terminal connection portion, and at least one substrate abutting portion that is made to project in a direction orthogonal to the insertion direction and is made to abut against the one surface of the substrate with the substrate connection portion and the hole portion soldered. The substrate abutting portion is formed on a base member by bending processing.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: February 14, 2017
    Assignee: YAZAKI CORPORATION
    Inventors: Shinya Ozaki, Yoshihito Imaizumi
  • Patent number: 9566747
    Abstract: A lead with segmented electrodes can be made using one or two mold methods. In one method, segmented electrodes are individually disposed on pins on an interior surface within a mold. Each of the segmented electrodes has at least one opening formed in the exterior surface of the segmented electrode. The lead body is then molded between the electrodes. In a two mold method, segmented electrodes are inserted into electrode slots of a first mold and an interior portion of a lead body is formed. The resulting intermediate arrangement is placed into a second mold to form an exterior portion of the lead body. In another two mold method, a sacrificial ring is formed around the segmented electrodes in a first mold and the resulting intermediate structure is inserted in a second mold to form the lead body. The sacrificial ring is then removed.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: February 14, 2017
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Daniel James Romero, Joshua Dale Howard
  • Patent number: 9456491
    Abstract: A printed circuit board includes a busbar applied to a surface of the printed circuit board. The busbar is configured as a sequence of sheet metal conductor pieces which are connected to each other in an electrically conducting manner. The respective ends of the conductor pieces may have a rounded portion and a corresponding cutout, or a point and a corresponding indentation. An electrical controller, a motor vehicle and a printed circuit board configuration having at least one printed circuit board are also provided.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: September 27, 2016
    Assignee: Continental Automotive GmbH
    Inventors: Stefan Peck, Jan Keller
  • Patent number: 9419354
    Abstract: A contact includes a body section, a tail section arranged at a lower portion of the body section, a peg extending from the tail section such that the peg projects from a front surface of the contact, and a fusible member attached to the contact such that the peg protrudes into the fusible member. A lower portion of the fusible member is offset from a main portion of the fusible member.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 16, 2016
    Assignee: SAMTEC, INC.
    Inventors: John Allen Mongold, Donald Christopher Knowlden, William Chieng Ouyang
  • Patent number: 9397026
    Abstract: A semiconductor device comprises a semiconductor chip mounted on an island, and a plurality of leads spaced form the island and connected by wires to the semiconductor chip. An insulating film encapsulates the island, the semiconductor chip, the wires and the leads, and the insulating resin has a concave portion that is in contact with the leads. Each lead has a bottom surface exposed from the insulating resin, and the concave portion of the insulating resin exposes side surfaces which surround the bottom surface of each of the leads located under a bottom surface of the insulating resin. When the semiconductor device is soldered to a circuit board, the concave portion prevents contact between the solder and the insulating resin and improves self-alignment of the semiconductor device on the circuit board.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: July 19, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Tomoyuki Yoshino
  • Patent number: 9293839
    Abstract: A method for manufacturing a card member includes: preparing a substrate having a card edge section with card edge terminals to be connected to an opposing connector; preparing a fist mold and a second mold that have molding spaces for molding a resin molded section having a fitting section to be fitted with the opposing connector formed around the substrate; placing the substrate inside the molding spaces between the first mold and the second mold in such a way that the joining portion of the first mold and the second mold are disposed so as not to be overlapped with the portion where the fitting section is to be formed; injecting a synthetic resin material into the molding space to integrally form the resin molded section around the substrate. The method can provide a card member having an excellent watertightness.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: March 22, 2016
    Assignee: J.S.T. MFG. CO., LTD.
    Inventor: Akira Nagamine
  • Patent number: 9204553
    Abstract: A method is provided for producing a printed circuit board. The method includes the step of providing an insulating substrate having a layer of aluminum material applied to the substrate. A portion of the layer of aluminum material is removed for defining a circuit trace. A layer of conductive material is applied to the layer of aluminum material.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: December 1, 2015
    Assignee: Lear Corporation
    Inventors: Jose Antonio Cubero Pitel, Andreu Fores Montserrat, Maria Leonor Torrijos Ezquerra
  • Patent number: 9172226
    Abstract: One aspect of the invention relates to a multi-core cable in which a cable sheath covers plural electronic wires in each of which a central conductor is covered with a covering. In the multi-core cable, the electronic wires are exposed from a longitudinal end of the cable sheath, and distal ends of exposed portions of the plural electronic wires are parallel aligned, and the exposed portions of the plural electronic wires are fixed by a resin in a place within a range from the end of the cable sheath to a parallel aligned place.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: October 27, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masato Tanaka, Yoshimasa Watanabe
  • Patent number: 9142489
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongwon Hong, Hei Seung Kim, Kyoung Hee Nam, Jongmyeong Lee, Gilheyun Choi
  • Patent number: 9093506
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: July 28, 2015
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Hong Shen
  • Patent number: 9082644
    Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Peter Ossimitz, Matthias von Daak, Gottfried Beer
  • Patent number: 9021690
    Abstract: A method of manufacturing a printed circuit board having a buried solder bump, including: preparing a carrier on which a circuit layer, a solder bump, and a circuit pattern formed on the solder bump are formed; pressing the carrier into an insulating layer so that the circuit layer, the solder bump and the circuit pattern are buried in the insulating layer; and removing the carrier.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 5, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Myung Sam Kang
  • Patent number: 9013878
    Abstract: An electronic system includes an insulating structural element with a coupling surface configured for coupling the electronic system with at least one further electronic system. The electronic system further includes at least one conducting contact element at least partially exposed on the coupling surface. Each conducting contact element has a soldering surface supporting reflow soldering of the conducting contact element with a corresponding further contact element of the further electronic system. In addition, each conducting contact element has at least one lateral surface protruding from the insulating structural element. The soldering surface of the conducting contact element includes at least one channel having an opened end at the protruding lateral surface, the channel configured to facilitate dispersion of waste gas produced during reflow soldering.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Sebastiano Dimauro, Sebastiano Russo, Rosalba Cacciola, Cristiano Gianluca Stella
  • Publication number: 20150092364
    Abstract: A method comprises mounting a grounding clip to a planar flexible printed circuit transmission line; clamping the grounding clip to an inner wall of a chassis of an electronic device; and operating a laser beam to weld the grounding clip to the chassis to route the flexible printed circuit transmission line along the inner wall. Welding the grounding clip to the chassis causes the grounding clip to remain in contact with the planar flexible printed circuit transmission line to ground the planar flexible printed circuit transmission line to the chassis.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Inventors: Romeo Dumpit, Rolf G. Laido, Mikko J. Timperi, Vincent Phan, Toni Kyroenlampi, Jani Haapamaki, Tim McGaffigan
  • Publication number: 20150083478
    Abstract: The electric part to be soldered to a metal pad mounted on a printed circuit board, includes a first surface facing the metal pad, a second surface extending from the first surface in a direction away from the metal pad, and a third surface outwardly extending from the second surface, the second surface and the third surface defining a space in which solder is stored.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 26, 2015
    Inventors: Takayoshi ENDO, Kenya ANDO
  • Patent number: 8987875
    Abstract: An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The material and thicknesses of the substrates and lead frames are selected so stress experienced by the electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 24, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Carl W. Berlin, Gary L. Eesley
  • Patent number: 8971049
    Abstract: A portable electronic device, a peripheral expansion module and methods for assembling a peripheral expansion module onto a portable electronic device are provided herein. The portable electronic device may comprise a main housing unit having a front cover and a back cover which, when coupled together, enclose internal components of the portable electronic device. The peripheral expansion module, comprising one or more peripheral devices coupled within or on a peripheral module housing, may be securely integrated with the portable electronic device. A majority of the peripheral expansion module may be positioned outside of the main housing unit along one side of the portable electronic device. In some embodiments, the peripheral expansion module includes a pair of rails, which extend out from within an interior of the module housing for attachment via one or more mechanical fasteners to an interior surface of the main housing unit of the portable electronic device.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 3, 2015
    Assignee: Motion Computing, Inc.
    Inventors: Bradford Edward Vier, Christopher Lorenzo Dunn
  • Patent number: 8970242
    Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: March 3, 2015
    Assignee: Rohm Co, Ltd.
    Inventors: Goro Nakatani, Masahiro Sakuragi, Koichi Niino
  • Patent number: 8955214
    Abstract: A method for securing a signal propagating line to a downhole component includes configuring the downhole component in a final form prior to securing the line thereto; positioning the line at an outside dimension of the component; and fusing the line to the component with a heat based fusion method and apparatus therefore.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 17, 2015
    Assignee: Baker Hughes Incorporated
    Inventors: Vinay Varma, Stephen L. Crow, Martin P. Coronado
  • Patent number: 8955218
    Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: February 17, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Shih-Lian Cheng
  • Publication number: 20150028196
    Abstract: Ion filter for FAIMS fabricated using the LIGA technique. The ion filter is manufactured using a metal layer to form the ion channels and an insulating support layer to hold the structure rigidly together after separation of the metal layer into two electrodes.
    Type: Application
    Filed: January 3, 2013
    Publication date: January 29, 2015
    Inventors: Danielle Toutoungi, Matthew Hart, John Somerville, Jon Pearson, Max Allsworth, Richard Orrell, Antoni Negri, Jeremy Spinks, Martin Holden, Andrew H. Koehl, Alistair Taylor
  • Patent number: 8931167
    Abstract: An electrical connector adapted to receive a mating plug utilizes low-profile jack terminal contacts that can flex in their PCB-anchored base portions, which are substantially parallel to the PCB. Any bend in the distal connecting portion or in the intermediate transition portion of each terminal contact is gradual and forms an obtuse angle, thus minimizing stress concentrations. The contacts preferably are arranged in two oppositely facing and interdigitating rows of four contacts each. In one embodiment, the terminal contacts are anchored to the PCB by a contact cradle that constrains the base portion of each terminal contact at two spaced anchoring locations, allowing the base portion to flex therebetween. In another embodiment, the base portions of the terminal contacts are embedded in at least one elastomeric member, which is fitted to the PCB.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: January 13, 2015
    Inventors: Shadi A. Abughazaleh, Joseph E. Dupuis, Christopher W. Gribble, Naved S. Khan, Douglas P. O'Connor
  • Publication number: 20140371530
    Abstract: The invention relates to an electrical connection piece for a video endoscope having a hermetically closed video unit in a shaft of the endoscope, a video endoscope, and a method for producing an electrical connection in a video endoscope. The electrical connection piece according to the invention includes an at least partially flexible printed circuit board having conductive tracks, wherein the printed circuit board has a base surface with openings for contact pins of a hermetic feedthrough, and a flexible first arm and a flexible second arm that branch off in different, in particular opposite, directions from the base surface, wherein the first arm and the second arm each have a flat end surface at the respective ends facing away from the base surface, wherein the conductive tracks extend between the openings on the base surface and electrical contacting surfaces in the end surfaces.
    Type: Application
    Filed: August 12, 2014
    Publication date: December 18, 2014
    Applicant: OLYMPUS WINTER & IBE GMBH
    Inventors: Martin WIETERS, Sebastian JUNGBAUER, Alrun THUEMAN, Nils TORKUHL, Enno EHLERS
  • Patent number: 8875391
    Abstract: A method of making a stimulation lead includes attaching multiple segmented electrodes to a carrier. Each of the segmented electrodes has a curved form extending over an arc in the range of 10 to 345 degrees. The method further includes attaching conductors to the segmented electrodes; forming the carrier into a cylinder with segmented electrodes disposed within the cylinder; molding a lead body around the segmented electrodes disposed on the carrier; and removing at least a portion of the carrier to separate the segmented electrodes.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: November 4, 2014
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Anne Margaret Pianca, William George Orinski
  • Publication number: 20140318850
    Abstract: A printed circuit board on which a component having a plurality of terminals is to be mounted by using a reflow soldering process, includes wiring patterns that are arranged in correspondence with the plurality of terminals and have a size which is smaller in wiring patterns for terminals near the central portion of the component than in wiring patterns for terminals near each end portion of the component.
    Type: Application
    Filed: February 13, 2013
    Publication date: October 30, 2014
    Inventor: Junnosuke Yokoyama
  • Publication number: 20140317919
    Abstract: Embodiments of the invention provide a method of manufacturing a printed circuit board. The method includes the steps of mounting a strip substrate on a fixing member, and separating the strip substrate into unit substrates by performing a singulation process. The method further includes the steps of attaching solder balls onto the unit substrates using a mask disposed on the unit substrates, and fixing the solder balls on the unit substrates by performing a reflow process.
    Type: Application
    Filed: July 3, 2014
    Publication date: October 30, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Su KIM, Seog Moon CHOI
  • Patent number: 8857021
    Abstract: An ink jet print head can be formed using a laser to melt a plating layer interposed between a piezoelectric actuator and a circuit layer bump. The plating layer can be formed on the circuit layer bump, the piezoelectric actuator, or both, and a laser beam output by the laser is used to melt the plating layer to provide a laser weld. In another embodiment, the circuit layer bump or the trace itself functions as the plating layer, which is melted using a laser to provide the laser weld.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Xerox Corporation
    Inventors: Bradley James Gerner, Peter J. Nystrom, Bryan R. Dolan
  • Publication number: 20140299368
    Abstract: The invention relates to a contact pin, comprising an angular end section, which is in particular designed for connecting to a wire or plug, wherein the angular end section has an angular cross-section. According to the invention, the contact pin has a round end section that is opposite the angular end section and that is designed for soldering to a circuit board. The round end section has a cross-section that is round at least in some sections of the circumference.
    Type: Application
    Filed: November 20, 2012
    Publication date: October 9, 2014
    Inventors: Joachim Braunger, Ulrich Becker, Richard Gueckel, Markus Kroeckel
  • Patent number: 8850699
    Abstract: A land grid array (LGA) and a method of forming the LGA are disclosed. The method comprises plating a printed circuit board to form a grid array of copper pads, and soldering a discrete pad over each of the plated copper pads in the grid array. The discrete pad is a solid object that can be handled and positioned independent of other discrete pads. Optionally, the method may further comprise measuring variations in flatness of the printed circuit board as a function of location in the grid array, and selecting individual discrete pads that each have a thickness selected for use at a particular location in the grid array so that the discrete pads provide a locus of exposed surfaces having greater flatness than the printed circuit board.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Larry G. Pymento, Tony C. Sass, Paul A. Wormsbecher
  • Publication number: 20140287604
    Abstract: A terminal comprises an upper arm having a top surface for a mating area; a lower arm paralleled with the upper arm and having a bottom surface soldering area; and a connecting arm connected with the upper arm and the lower arm.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 25, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: PO-YUAN LIN, LI-DONG TANG, CHIH-HAO LEE
  • Patent number: 8835772
    Abstract: In order to lower the substantial heating temperature of a thermosetting adhesive and to realize favorable connection reliability during connecting an electrical element to a circuit board by anisotropic conductive connection with using solder particles, a product in which solder particles having a melting temperature Ts are dispersed in an insulating acrylic-based thermosetting resin having a minimum melt viscosity temperature Tv is used as an anisotropic conductive adhesive in producing a connection structure by connecting the circuit board and the electrical element to each other by anisotropic conductive connection.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 16, 2014
    Assignee: Dexerials Corporation
    Inventor: Satoshi Igarashi
  • Patent number: 8837141
    Abstract: An electronic module comprises: a multilayer circuit board having a bifurcated area along one edge and a plurality of electronic components mounted on at least one surface; a plurality of electrode pads functionally connected to the electronic components and positioned on the inner surfaces of the bifurcated area so that when the two legs of the bifurcated area are spread apart by about 180° the electrode pads align with respective contacts on a motherboard, and are connectable thereto, so that a secure connection may be created between the circuit board and the motherboard; and, two metal, heat spreading covers lockably enclosing the circuit board, one on either side, the covers further providing mating surfaces upon which a mechanical clamping device can engage and secure the module to a motherboard.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: September 16, 2014
    Assignee: Microelectronics Assembly Technologies
    Inventors: James E. Clayton, Zakaryae Fathi
  • Patent number: 8806731
    Abstract: There is provided a method of repairing a probe board, the method including: preparing a plurality of first via electrodes filled with a first filling material in a board body formed as a ceramic sintered body; forming a via hole for an open via electrode among the plurality of first via electrodes; filling the via hole with a second filling material having a lower sintering temperature than that of the first filling material; and forming a second via electrode by sintering the second filling material. The open via repair according to the present invention improves the manufacturing yield of the board and reduces the manufacturing costs thereof.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 19, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Whun Chang, Dae Hyeong Lee, Ki Pyo Hong
  • Publication number: 20140223733
    Abstract: A new method for making and manufacturing the User-Friendly USB Male connectors which is faster, lower cost, more energy efficient, waterproof and reliable, with no expensive tooling and molding required, having better quality and being easily adaptable for automated assembly.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Inventor: Joseph Lai
  • Patent number: 8800140
    Abstract: Some embodiments of the invention comprise a customizable multichannel microelectrode array with a modular planar microfabricated electrode array attached to a carrier and a high density of recording and/or stimulation electrode sites disposed thereon. Novel methods of making and using same are also disclosed.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: August 12, 2014
    Assignee: NeuroNexus Technologies, Inc.
    Inventors: Jamille F. Hetke, Daryl R. Kipke, David S. Pellinen, David J. Anderson
  • Publication number: 20140176124
    Abstract: A current sensor includes: a housing that holds a busbar to which a current is applied and a core arranged around the busbar; a circuit board fixed to the housing in the state of being arranged to face the housing; and a detection element for detecting the current; wherein the detection element has an element main body held in the housing and plural connection terminals fixed in through-holes in the circuit board, and a plate-like member provided with guide holes in which the connection terminals are inserted and which have a diameter reduced from the side of the housing toward the side of the circuit board is provided on a surface facing the housing, of two surfaces of the circuit board.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 26, 2014
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Ken OKUMURA, Shigeki NIIMI, Kenichi TAGUCHI, Akira KAMIYA, Takashi KUROZUMI, Kimihiro TAMURA, Katsuki KATAOKA
  • Patent number: 8713792
    Abstract: A printed wiring board includes a Cu wiring pattern formed on a substrate. A first metal layer is formed on the Cu wiring pattern. A second metal layer is formed on the first metal layer. The first metal layer has a less reactivity with Cu than the second metal layer. The first metal layer and the second metal layer together cause an eutectic reaction.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Seiki Sakuyama
  • Publication number: 20140111914
    Abstract: The present application describes various embodiments of systems and methods for providing internal and external components for portable computing devices having a thin profile. More particularly, the present application describes internal components configured to fit within a relatively thin outer enclosure, wherein the internal components comprise at least one external interface, such as, for example, a track pad interface.
    Type: Application
    Filed: April 2, 2013
    Publication date: April 24, 2014
    Applicant: APPLE INC.
    Inventors: William F. Leggett, David M. Rockford, Gavin J. Reid, Matthew P. Casebolt, Changsoo Jang
  • Patent number: 8701281
    Abstract: Surface-active dopants are added to a portion of a circuit package before a reflow process to promote wetting and reduce the formation of solder bump bridges. The circuit package has a solder element that electrically connects the circuit package to a substrate. A reflow process is performed to attach the solder element to a pad on the circuit package. During the reflow process, the surface-active dopants diffuse to the surface of the solder element and form an oxide passivation layer on the surface of the solder element.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Ashay A. Dani, Mukul P. Renavikar
  • Publication number: 20140102772
    Abstract: A packaging carrier includes an interposer, a dielectric layer and a built-up structure. The interposer has a first surface and a second surface opposite to each other, and a plurality of first pads and second pads located on the first surface and the second surface, respectively. The dielectric layer has a third surface and a fourth surface opposite to each other. The interposer is embedded in the dielectric layer. The second surface of the interposer is not covered by the fourth surface of the dielectric layer, and has a height difference with the fourth surface. The built-up structure is disposed on the third surface of the dielectric layer and electrically connected to the first pads of the interposer.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 17, 2014
    Applicant: Unimicron Technology Corp.
    Inventors: Ming-Chih Chen, Dyi-Chung Hu
  • Publication number: 20140106593
    Abstract: An electrical connector assembly includes an insulating housing having a number of housing segments, a number of contacts received in the housing segments, a number of caps covering on the housing segments respectively and a number of clips assembled on the caps. Each of the caps includes a retaining mechanism defining an arm for operating by a user and a latch engaging the housing segment. Each of the clips is assembled on the arms of at least two caps so as to operate two caps together.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 17, 2014
    Applicant: Hon Hai Precision Industry Co., Ltd.
    Inventor: SHUO-HSIU HSU
  • Patent number: 8692281
    Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: April 8, 2014
    Assignee: DiCon Fiberoptics Inc.
    Inventors: Wen-Herng Su, Junying Lu, Ho-Shang Lee
  • Publication number: 20140090880
    Abstract: An electrical connecting element, a method of fabricating the same, and an electrical connecting structure comprising the same are disclosed. The method of fabricating the electrical connecting structure having twinned copper of the present invention comprises steps of: (A) providing a first substrate; (B) forming a nano-twinned copper layer on part of a surface of the first substrate; (C) forming a solder on the nano-twinned copper layer of the first substrate; and (D) reflowing the nano-twinned Cu layer and solder to produce a solder joint, wherein at least part of the solder reacts with the nano-twinned copper layer to produce an intermetallic compound (IMC) layer which comprises a Cu3Sn layer, This invention reduces the voids formation in the interface between the intermetallic compound and the solder, and then enhances the reliability of solder joints.
    Type: Application
    Filed: August 22, 2013
    Publication date: April 3, 2014
    Applicant: National Chiao Tung University
    Inventors: Chih CHEN, Wei-Lan CHIU