By Metal Fusion Bonding Patents (Class 29/843)
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Patent number: 7578057Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.Type: GrantFiled: June 27, 2006Date of Patent: August 25, 2009Assignee: FormFactor, Inc.Inventors: Mohammad Eslamy, David V. Pedersen, Harry D. Cobb
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Patent number: 7578056Abstract: A method for encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer to the surface of the flip chip except for the distal end of the conductive projections on the flip chip electrically conductive pads. The coated flip chip is exposed to ultraviolet light or heat (e.g., IR radiation) so that the coating is at least partially cured.Type: GrantFiled: December 18, 2006Date of Patent: August 25, 2009Assignee: Micron Technology, Inc.Inventors: Farrah J. Johnson, Tongbi Jiang
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Publication number: 20090205854Abstract: A printed circuit board for use in a package and to a method of manufacturing the printed circuit board. The method of manufacturing the printed circuit board can include: providing a substrate, on one side of which at least one solder pad and at least one guide pad are formed; forming a solder resist layer over the one side of the substrate; uncovering at least one portion of the solder resist layer such that the guide pad is exposed; applying a surface treatment on the exposed guide pad; uncovering at least one portion of the solder resist layer such that the solder pad is exposed; and forming a solder bump on the exposed solder pad. With this method, the amount of surface treatment applied can be minimized, for reduced costs, and the occurrence of undiffused layers can be avoided, for improved reliability in the final product.Type: ApplicationFiled: July 16, 2008Publication date: August 20, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dong-Gyu Lee, Jin-Won Choi, Ki-Young Yoo, Tae-Joon Chung
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Publication number: 20090203234Abstract: A printed circuit board arrangement and method includes a planar generally-rectangular vertically-arranged printed circuit board having front and rear surfaces terminating in a peripheral edge, at least one of the front and rear surfaces having a conductive printed circuit thereon. The printed circuit board has a vertical side edge portion containing a recess, and arranged adjacent the recess is a fixed contact connected with a conductor portion of the printed circuit. A relatively narrow conductor housing arranged outside the peripheral edge of the printed circuit board is mounted in the recess with a movable contact carried by the housing in electrical engagement with the fixed contact. The connector housing is supported by a rear wall mounted on the rear surface of the printed circuit board, and by a resilient clip on the connector housing that engages the printed circuit board adjacent the recess.Type: ApplicationFiled: February 5, 2009Publication date: August 13, 2009Inventors: Christian Heggemann, Jens Oesterhaus, Matthias Boensch, Matthias Niggemann, Michael Lenschen, Stephan Fehling, Torsten Diekmann
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Patent number: 7562428Abstract: A manufacturing method that includes the steps of forming an actuator unit, disposing a metallic bond and a thermosetting resin; pressing the land and the terminal; and heating the metallic bond and the thermosetting resin so that the land and the terminal are electrically connected to each other with the metallic bond being disposed in at least one of a region between the land and the terminal and a region extending over the land and the terminal along the peripheries of the land and the terminal, and a protrusion made of the thermosetting resin is formed at least in the connecting portion between the main electrode portion and the land.Type: GrantFiled: September 23, 2003Date of Patent: July 21, 2009Assignee: Brother Kogyo Kabushiki KaishaInventor: Yuji Shinkai
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Publication number: 20090159318Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method may include forming at least one first bump over a first metal layer by selectively printing an alloy paste, stacking an insulation layer over the first metal layer such that the first bump penetrates the insulation layer, and stacking a second metal layer over the insulation layer. Embodiments of the invention can shorten the manufacturing process and lower manufacturing costs, while effectively implementing signal transfers.Type: ApplicationFiled: June 24, 2008Publication date: June 25, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Nobuyuki Ikeguchi, Eung-Suek Lee
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Publication number: 20090151160Abstract: A method of manufacturing a printed circuit board having solder balls. The method may include: stacking a second carrier, in which at least one hole is formed, over one side of a first carrier; forming at least one solder bump by filling the hole with a conductive material; forming a circuit pattern layer, which is electrically connected with the solder bump, on the second carrier; and exposing the solder bump by removing the first carrier and the second carrier. Using this method, uniform hemispherical solder balls with fine pitch can be formed as a part of the manufacturing process, without having to attach the solder balls separately. Carriers may be used to serve as supports during the manufacturing process, whereby deformations can be prevented in the board.Type: ApplicationFiled: June 19, 2008Publication date: June 18, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Shuhichi Okabe, Jin-Yong An, Seok-Kyu Lee, Soon-Oh Jung, Jong-Kuk Hong, Hae-Nam Seo
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Patent number: 7546682Abstract: A method for repairing a circuit board having defective pre-soldering bumps is proposed. Firstly, the circuit board having a plurality of pre-soldering bumps on a surface thereof is provided, wherein at least one of the pre-soldering bumps has a defect. Then, a micro-electroplating process or a micro-electrolyzing process is performed by a micro-electrode nearby the defective pre-soldering bump, so as to repair the defective pre-soldering bump. Therefore, the present invention is able to enhance the process yield and reduce the production cost.Type: GrantFiled: November 21, 2006Date of Patent: June 16, 2009Assignee: Phoenix Precision Technology CorporationInventors: Shih-Ping Hsu, Chao Wen Shih
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Patent number: 7543372Abstract: Disclosed is a method for forming electrical interconnections between railroad track components and signal conductors/lines. In one arrangement, an electrically conductive adhesive is utilized to electrically interconnect a signal conductor to a railroad track component. In another arrangement, a clamp is utilized in conjunction with the electrically conductive adhesive that forms the electrical interconnection. The clamp maintains the signal conductor in direct contact with the surface of the railroad track component while the electrically conductive adhesive cures. In these arrangements, the use of the electrically conductive adhesive allows for making an electrical connection with a railroad component without penetrating the structure of that component. In a further arrangement, a hollow tubular connector is utilized to electrically connect two signal conductors associated with railroad track components.Type: GrantFiled: July 21, 2005Date of Patent: June 9, 2009Assignee: Fastrax Industries, Inc.Inventor: David L. Reichle
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Patent number: 7536762Abstract: A method for manufacturing a board assembly comprises the steps of: tin-plating a first terminal and a copper-made second terminal that are formed on a circuit board; mounting an electronic component on the circuit board by means of gold-tin eutectic bonding between a gold electrode of the electronic component and the tin-plated first terminal; forming a copper-tin alloy on a surface of the second terminal by heating the circuit board after the mounting step; and bonding the second terminal having the copper-tin alloy formed on its surface to a terminal of another board by means of a thermosetting conductive adhesive.Type: GrantFiled: January 30, 2006Date of Patent: May 26, 2009Assignee: Brother Kogyo Kabushiki KaishaInventors: Koji Imai, Yuji Shinkai
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Publication number: 20090095519Abstract: An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.Type: ApplicationFiled: October 16, 2007Publication date: April 16, 2009Inventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Publication number: 20090077798Abstract: A method for forming a conductive post include: a) forming a liquid repellent portion having a thickness of 100 nm or less by disposing a liquid repellent material in a conductive post forming region on a conductive layer; b) forming an insulation layer having an opening in a region overlapping with the conductive post forming region by disposing a liquid including an insulation layer forming material on the conductive layer having the liquid repellent portion formed thereon and polymerizing the insulation layer forming material; c) disposing metal particulates in the opening; and d) heating the metal particulates at a fusing temperature of the metal particulates or higher so as to fusion bond the metal particulates to each other in order to form the conductive post, and to fusion bond the metal particulates and the conductive layer in order to couple the conductive post with the conductive layer.Type: ApplicationFiled: September 9, 2008Publication date: March 26, 2009Applicant: Seiko Epson CorporationInventors: Toshimitsu HIRAI, Tsuyoshi SHINTATE, Jun YAMADA
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Publication number: 20090049688Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.Type: ApplicationFiled: May 27, 2008Publication date: February 26, 2009Applicant: International Business Machines CorporationInventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
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Patent number: 7493680Abstract: To provide an airtight terminal and a piezoelectric vibrator having a strong rigidity of a lead despite a small-sized constitution, and provide a method of fabricating an airtight terminal constituting a lead penetrating inside of a stem by one piece and a piezoelectric vibrator with an excellent yield. A stem 11 filled with a filling member 13 is penetrated only with one piece of a lead 12 formed from a lead frame. As an electric terminal, a conductive lead 16 connected to the stem 11 is provided other than the lead 12. The lead 12 and the conductive lead 16 of an airtight terminal 10 constituted by the stem 11, the lead 12, the filling member 13, the conductive lead 16 are connected to a piezoelectric vibrating piece 20, further, the stem 11 is capped to a case 30 to thereby constitute a piezoelectric vibrator 1.Type: GrantFiled: October 24, 2006Date of Patent: February 24, 2009Assignee: Seiko Instruments Inc.Inventors: Hiroaki Uetake, Yuki Hoshi
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Publication number: 20090042452Abstract: A connector connection structure includes: a case having a side surface and a top surface, respectively extending in directions crossing each other at a first angle, and an opening; a connector terminal portion inserted into the case from the opening; a shield plate closing the opening; a bolt fastening the case and the shield plate; and a terminal block arranged in the case and connected to the connector terminal portion. The shield plate has a first portion extending along the side surface and closing the opening, a second portion extending along the top surface, and a bent portion positioned between the first portion and the second portion and bent at a second angle being smaller than the first angle. The bolt fastens the case and the second portion of the shield plate.Type: ApplicationFiled: August 8, 2008Publication date: February 12, 2009Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, YAZAKI CORPORATIONInventors: Jun Asada, Eiji Aoki, Tomokazu Yamane, Takeaki Kaneko, Hajime Kato
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Patent number: 7484293Abstract: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12.Type: GrantFiled: December 7, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Yoshiyuki Yamaji, Hirokazu Noma, Hiroyuki Mori
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Publication number: 20090029573Abstract: A contact device is provided, the device having at least a first contact region for electrical connection to an electric line and at least a second contact region for electrical connection to a flexible printed circuit board other contact medium which may damaged by repeated soldering. The first contact region and the second contact region are electrically connected. Between the first contact region and the second contact region, a third region is provided which has a lower thermal conductivity per unit length than the first contact region and/or the second contact region.Type: ApplicationFiled: August 8, 2008Publication date: January 29, 2009Applicant: Knorr-Bremse Systeme fuer Nutzfahrzeuge GmbHInventors: Herbert KLINGER, Martin PETRZIK, Michael HAUG, Friedbert ROETHER, Markus DEEG
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Publication number: 20090020323Abstract: A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.Type: ApplicationFiled: July 18, 2008Publication date: January 22, 2009Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Te Chen, Ke-Chuan Yang, Hung-Ming Chang
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Publication number: 20090020325Abstract: A solderable contact for use with an electrical component includes a pad metallization on a substrate, and an under bump metallization over at least part of the pad metallization. The under bump metallization is in an area for receiving solder. The pad metallization is structured to reveal parts of the substrate surface. The under bump metallization is in direct contact with the parts of the substrate.Type: ApplicationFiled: February 9, 2006Publication date: January 22, 2009Inventors: Robert Hammedinger, Konrad Kastner, Martin Maier, Michael Obesser
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Publication number: 20090008136Abstract: A multilayered printed circuit board and a method of fabricating the printed circuit board are disclosed. The method of fabricating the multilayered printed circuit board can include: providing a core substrate, which has an outer circuit, and which has a thermal expansion coefficient of 10 to 20 ppm/° C. at ?60 to 150° C.; stacking a stress-relieving insulation layer, which has a thermal expansion coefficient of ?20 to 6 ppm/° C., on either side of the core substrate; and forming a metal layer on the insulation layer and forming at least one pad and electrically connecting the pad with the outer circuit. This method can provide high reliability, as the stress-relieving insulation layers can prevent bending and warpage, etc., in the board overall.Type: ApplicationFiled: June 25, 2008Publication date: January 8, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Nobuyuki Ikeguchi, Keungjin Sohn, Joon-Sik Shin
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Publication number: 20090007425Abstract: Provided is a method for manufacturing a multilayer wiring board, by which interlayer connection is efficiently performed and a non-penetrating hole having a hollow structure or a through hole can be formed at the same time without damaging a plated portion on the inner wall of the through hole. A first printed board (1) is provided with a wiring, which has a wiring section and a bump mounting pad (14), and a substrate section. The method is provided with a step of forming a solder bump (3) on at least a bump mounting pad on the first printed board or a pad section of a second printed board (2) having the pad section (15) by using a solder paste, and a step of bonding the first printed board and the second printed board in layers by having an insulating adhesive (4) between the first printed board and the second printed board and electrically connecting the first printed board with the second printed board.Type: ApplicationFiled: February 7, 2007Publication date: January 8, 2009Inventors: Eiichi Shinada, Masahiro Katou, Noriaki Watanabe
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Patent number: 7472477Abstract: The illustrative embodiments provide a method for manufacturing a socket and attaching the socket to a printed circuit board. Surface mounted contacts for a bottom surface of a socket are provided. The surface mounted contacts are a plurality of conductive metal pads that directly attach to surface connections on a printed circuit board. An elongated housing is formed comprising at least two members that are coupled together and disposed to form an aperture in between the at least two members. At least one dimension of the at least two members is selected to compensate for a difference between coefficients of thermal expansion between the socket and the printed circuit board. The at least two members and the surface mounted contacts are aligned with the printed circuit board using a clip. In response to completing a solder reflow process, the clip is removed and a module is inserted into the aperture.Type: GrantFiled: October 12, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Brian Samuel Beaman, Joseph Kuczynski, Theron Lee Lewis, Amanda Elisa Ennis Mikhail, Arvind Kumar Sinha
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Publication number: 20080307643Abstract: An improved process for assembling a plurality of power packages and a thermal heat sink to a printed circuit board involves securing the power packages to the heat sink before soldering the electrical leads of the power packages to the printed circuit board. The improved process allows the electrical leads of the power packages to move freely in lead holes in the printed circuit board as intimate planar surface to planar surface contact between the heat sink and the power packages is achieved, thereby eliminating or at least substantially reducing lead bending that occurs in conventional processes wherein attachment of the heat sink to the power packages occurs after the leads of the power packages have been soldered to the printed circuit board.Type: ApplicationFiled: June 15, 2007Publication date: December 18, 2008Inventor: Wayne A. Sozansky
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Patent number: 7464459Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms a magnetic core member. The magnetic core member, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, followed by the formation of an overlying cantilevered magnetic flexible member. Switch electrodes, which are separated by a switch gap, can be formed on the magnetic core member and the magnetic flexible member, and closed and opened in response to the electromagnetic field that arises in response to a current in the coil.Type: GrantFiled: May 25, 2007Date of Patent: December 16, 2008Assignee: National Semiconductor CorporationInventors: Trevor Niblock, Peter Johnson
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Publication number: 20080301935Abstract: A substrate manufacturing apparatus 100 has a substrate delivery path 120 through which a multi-unit substrate 110 is delivered and a mask delivery path 140 through which an individual mask 130 is delivered. The substrate delivery path 120 has a pad detecting device 160 for detecting a position of a pad 112 formed on a surface of the substrate 110. The mask delivery path 140 has a mask hole detecting device 220 for detecting a position of a conductive ball inserting hole 132 of the individual mask 130. A moving position of an adsorbing head 212 is adjusted in such a manner that the position of the conductive ball inserting hole 132 is coincident with that of the pad 112 of the substrate 110 based on pad position information of the pad detecting device 160 and mask hole position information of the mask hole detecting device 220.Type: ApplicationFiled: May 23, 2008Publication date: December 11, 2008Applicant: SHINKO ELECTRIC INDUSTRIES, CO., LTD.Inventors: Kiyoaki IIDA, Kazuo Tanaka, Hideaki Sakaguchi, Mitsutoshi Higashi
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Publication number: 20080302560Abstract: A method of manufacturing a printed wiring board with solder bumps includes forming a solder-resist layer having small and large apertures exposing a respective conductive pad of the printed wiring board, loading a solder ball in each of the small and large apertures using a mask with aperture areas corresponding to the apertures of the solder-resist layer, forming a first bump having a first height, from the solder ball in the small aperture, and a second bump having a second height, from the solder ball in the large aperture, the first height being greater than the second height, and pressing a top of the first bump such that the first height becomes substantially the same as the second height. A multilayer printed wiring board includes a solder-resist layer with apertures of differing sizes and solder bumps having substantially equal volumes but a difference in height no greater than 10 ?m.Type: ApplicationFiled: May 13, 2008Publication date: December 11, 2008Applicant: IBIDEN CO., LTDInventors: Katsuhiko Tanno, Youichirou Kawamura
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Patent number: 7462939Abstract: In one aspect, the present invention provides interposers that can mechanically, electrically, and thermally interconnect first and second microelectronic components. An interposer in accordance with the present invention includes a substrate, preferably flexible, having first and second oppositely facing surfaces. Such interposers also include an array of links traversing from the first surface of the substrate to the second surface of the substrate. In accordance with the present invention, each link preferably comprises a buried portion positioned between the first and second surfaces of the substrate. In other aspects of the present invention, microelectronic assemblies having first and second microelectronic components interconnected by an interposer and methods of interconnecting such components are provided.Type: GrantFiled: October 20, 2005Date of Patent: December 9, 2008Assignee: Honeywell International Inc.Inventor: Lance L. Sundstrom
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Publication number: 20080295328Abstract: In a method of manufacturing an electronic component package, first, a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages are formed by plating on a top surface of a substrate to thereby fabricate a wafer. The wafer includes a plurality of pre-base portions that will be separated from one another later to become bases of the respective electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chip are connected to the external connecting terminals. Next, the electronic component chip is sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Applicants: HEADWAY TECHNOLOGIES, INC., SAE MAGNETICS (H.K.) LTD.Inventors: Yoshitaka Sasaki, Tatsushi Shimizu
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Patent number: 7434310Abstract: A process for reforming a plastic packaged integrated circuit die (100) includes grinding away (305) a bottom side (210) of a plastic package (205) and portions of a set of leads (110) that are in the plane of the grinding until a bottom surface (240) of an inner portion (230) of the set of leads is exposed at a peripheral region (235) of the inner portion, cutting (310) approximately perpendicularly to the top and bottom sides to remove portions of the plastic package and the set of leads that are outside the inner portion of the set of leads, and adapting (320) the bottom surfaces of the inner portion of the set of leads for reliable electrical connections.Type: GrantFiled: June 5, 2006Date of Patent: October 14, 2008Assignee: Motorola, Inc.Inventors: Timothy B. Dean, Bruce C. Deemer, Daniel T. Rooney
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Publication number: 20080220667Abstract: A terminal for a sealed accumulator comprises a single-piece body made of aluminium with at least one tinned zone for soldering to an electronic card and at least one non-tinned zone for connection to a current output terminal of the accumulator. The electrical terminal has a limited space requirement; welds well onto an accumulator container made of aluminium and allows easy assembly with an electronic card by soldering without risk of migration of tin which could cause a short circuit.Type: ApplicationFiled: March 4, 2008Publication date: September 11, 2008Applicant: SAFT GROUPE SAInventor: Nicolas VIGIER
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Patent number: 7421778Abstract: According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a first substrate having an integrated circuit formed therein and a second substrate. The first and second substrates are interconnected by a plurality of bi-material interconnects that are electrically connected to the integrated circuit and have a first component comprising a conductive first material with a first coefficient of thermal expansion and a second component comprising a second material with a second coefficient of thermal expansion. The first and second components are connected and shaped such that when the temperature of the bi-material interconnects changes the interconnects each bend towards the first or second component. When the temperature of the second substrate increases, the second substrate expands away from a central portion thereof. The bi-material interconnects are arranged such that the bi-material interconnects bend away from the central portion of the second substrate.Type: GrantFiled: March 22, 2006Date of Patent: September 9, 2008Assignee: Intel CorporationInventors: Jason A. Garcia, John J. Beatty
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Patent number: 7421780Abstract: Methods for fabricating thermal management systems for micro-component devices are described herein. The methods may include initially overlaying a target substrate with a blank that is in sheet form, and stamping a microchannel structure having a plurality of outer walls enclosing a predefined area from the blank. The microchannel structure may then be bonded to a heat dissipating side opposite from a micro-component device facing side of a first substrate, the micro-component device facing side of the first substrate being adapted to thermally engage with the micro-component device. The microchannel structure may then be bonded to a second substrate opposite the first substrate, resulting in a closed volume microchannel being defined. Finally, the defined microchannel may then be substantially filled with a fluid thermal interface material.Type: GrantFiled: January 6, 2006Date of Patent: September 9, 2008Assignee: Intel CorporationInventors: Sabina Houle, James C. Matayabas, Jr.
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Publication number: 20080205027Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.Type: ApplicationFiled: February 21, 2008Publication date: August 28, 2008Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Philippe Coronel, Perceval Coudrain, Pascale Mazoyer
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Publication number: 20080205013Abstract: A solder layer and an electronic device bonding substrate having high bonding strength of a device and low bonding failure even by a simplified bonding method of a device to a substrate and a method for manufacturing the same are provided. A device bonding substrate 1 including a substrate 2 and a lead free solder layer 5 formed on said substrate has a solder layer 5 consisting of a plurality of layers having mutually different phases, and oxygen concentration on the upper surface of the solder layer is lower than 30 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer 5. Carbon concentration on the upper surface of the solder layer 5 may be lower than 10 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer.Type: ApplicationFiled: February 27, 2008Publication date: August 28, 2008Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.Inventors: Yoshikazu OSHIKA, Munenori HASHIMOTO, Masayuki NAKANO
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Patent number: 7412767Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.Type: GrantFiled: January 3, 2005Date of Patent: August 19, 2008Assignee: Microfabrica, Inc.Inventors: Kieun Kim, Adam L. Cohen, Willa M. Larsen, Richard T. Chen, Ananda H. Kumar, Ezekiel J. J. Kruglick, Vacit Arat, Gang Zhang, Michael S. Lockard
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Publication number: 20080189942Abstract: A method for manufacturing a bump of a probe card is disclosed. In accordance with the present invention, the bump has a high aspect ratio, a high elasticity, a high durability suitable for testing a high speed device. The bump is formed using a sacrificial substrate as a mold to have a shape of ? or II for elasticity and durability.Type: ApplicationFiled: June 8, 2007Publication date: August 14, 2008Applicant: UniTest, Inc.Inventors: Bong Hwan KIM, Jong Bok Kim
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Patent number: 7409762Abstract: A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate, shaped openings in the substrate, or shaped portions of the substrate. The spring segments are configured to flex to exert spring forces on the component contacts, and to compensate for variations in the size or planarity of the component contacts. The interconnect can be configured to test wafer sized components, or to test die sized components.Type: GrantFiled: April 3, 2006Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventor: Kyle K. Kirby
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Patent number: 7401393Abstract: The present invention provides a method for removing solder adhering to an LSI. In this method, a plate-shaped first member for causing molten solder to adhere thereto is mounted on top of a heater. An LSI is placed on top of the first member with the surface on which solder is attached facing downward. A second member for adding a load to the LSI is placed on top of the LSI. The heater is heated up to heat the first member and the LSI, and to melt the solder. The molten solder is transferred to the first member. A suction mechanism is positioned at a location a predetermined distance away from the top surface of the second member. The second member and the LSI are attracted by the suction mechanism, and the LSI is pulled away from the first member. The solder is thereby removed from the LSI.Type: GrantFiled: May 17, 2004Date of Patent: July 22, 2008Assignee: Hitachi, Ltd.Inventors: Motoko Kimura, Takeshi Miitsu, Takeshi Takahashi, Kaoru Katayama, Shiro Yamashita
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Publication number: 20080163476Abstract: The disclosure relates to a method for producing a contact piece, for use in a vacuum interrupter chamber, especially in a low, medium or high voltage vacuum interrupter chamber, and to a contact piece for a medium voltage vacuum interrupter chamber. The aim of the disclosure is to improve multi-layer contact systems in such a manner that even larger layer thicknesses can be used to improve the electrical properties. For this purpose, the contact piece is comprised of at least two layers with a solder film inserted thereinbetween, the layers being welded together in a vacuum furnace in a desired relative position to each other. The two-layer structure can also be achieved by a powder layering process. For this purpose, the powder layers are compressed in a compression mold and then sintered in the furnace to give the finished contact piece blank.Type: ApplicationFiled: January 24, 2006Publication date: July 10, 2008Applicant: ABB Technology AGInventors: Dietmar Gentsch, Gunter Pilsinger
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Publication number: 20080149380Abstract: A material board for producing a hybrid circuit board includes a plurality of hybrid circuit board sections 1 on each of which an electronic component 2 is mounted and a metallic terminal plate 3 for external connection is bonded so as to project from the hybrid circuit board section. A frame portion 6 is defined between the hybrid circuit board sections, and the hybrid circuit board sections are integrally connected to the frame portion via a thin strip 8 provided at an intermediate portion of grooves 7 each surrounding a respective one of the hybrid circuit board sections entirely. In bonding the terminal plate 3 to the hybrid circuit board by soldering, the terminal plate is temporarily bonded to the frame portion 6 with an adhesive 9. The adhesive is prevented from spreading toward the end of the terminal plate.Type: ApplicationFiled: August 9, 2005Publication date: June 26, 2008Applicant: ROHM CO., LTD.Inventor: Seitaro Mizuhara
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Patent number: 7386936Abstract: The present invention relates to a method for manufacturing an electrically conductive pattern by printing a layer comprising metal oxide on a carrier substrate (2) and reducing the metal oxide to metal. The reduced layer is transferred to an application substrate (7). The present invention also relates to the use of the method.Type: GrantFiled: September 1, 2005Date of Patent: June 17, 2008Assignee: Intune Circuits OyInventors: Lauri Huhtasalo, Samuli Strömberg, Marko Hanhikorpi, Olli Hyvärinen, Pekka Taskinen, Tuija Suortti
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Patent number: 7380338Abstract: A circuit board includes a substrate, an insulating layer, at least one protrusion, and a first circuit layer. The insulating layer is disposed on the substrate and has at least one protrusion-positioning region. At least a part of the protrusion is disposed on the protrusion-positioning region. The first circuit layer is disposed on the insulating layer and has at least one trace line extending onto the protrusion.Type: GrantFiled: June 22, 2005Date of Patent: June 3, 2008Assignee: Gigno Technology Co., Ltd.Inventor: Yu-Tuan Lee
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Publication number: 20080120832Abstract: This invention provides a solder ball loading apparatus which enables fine solder balls to be loaded on pads while void is blocked from being caught into bump upon reflow. Inactive gas is supplied and the inactive gas is sucked from a loading cylinder located above a ball arrangement mask so as to gather solder balls. The gathered solder balls are rolled on the ball arrangement mask by moving the loading cylinder horizontally and the solder balls are dropped onto connecting pads on a multilayer printed wiring board through openings in the ball arrangement mask. Oxidation of the solder balls and mixture of voids upon reflow are prevented by loading the solder balls in the atmosphere of inactive gas.Type: ApplicationFiled: January 31, 2008Publication date: May 29, 2008Applicant: IBIDEN CO., LTDInventors: Yoichiro KAWAMURA, Katsuhiko Tanno
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Patent number: 7367116Abstract: To provide an interlayer-connected, multi-layer flexible printed circuit board having high bonding reliability and most suitable for micropatterning the circuit layers in the device; and to provide a high-productivity method for fabricating the device. A multi-layer flexible printed circuit board, wherein a conductor is filled in the through-holes formed in the insulating layer in the direction of the thickness thereof so as to electrically interconnect the circuit layers formed on both faces of the insulating layer, and wherein the conductor contains inside it, a copper-core solder ball having a copper ball as a core thereof.Type: GrantFiled: July 15, 2004Date of Patent: May 6, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyokazu Yoshino, Kouji Nakashima
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Publication number: 20080101045Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.Type: ApplicationFiled: October 19, 2007Publication date: May 1, 2008Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hoe-Ku Jung, Je-Gwang Yoo, Myung-Sam Kang, Ji-Eun Kim, Jeong-Woo Park, Jung-Hyun Park
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Publication number: 20080099235Abstract: According to one embodiment, there is provided a printed-wiring board on which an electrode for a semiconductor device bonding in a flip-chip-mounting manner is formed by an exposed part of a wiring pattern defined by a solder resist coating film, wherein the electrode includes an expanded section spreading in a line width direction of the wiring pattern to form the electrode.Type: ApplicationFiled: October 30, 2007Publication date: May 1, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Syuji Hiramoto, Makoto Aoki
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Patent number: 7362562Abstract: The invention relates to a method of producing an electronic unit of a radio system automatically, an electronic unit of a radio system and an electronic component. The method of producing an electronic unit of a radio system automatically comprises mounting (802) the electronic component automatically in a hole provided for the electronic component in the circuit board using alignment means of the electronic component and alignment means of the circuit board, which align electric connecting means of the electronic component against electric connecting means on the circuit board; soldering (804) the electric connecting means of the electronic component automatically to the electric connecting means of the circuit board; and attaching (806) the electronic component automatically to the mechanical part so that the electronic component is in contact with the mechanical part, in which case the electronic component is cooled via the mechanical part.Type: GrantFiled: June 18, 2003Date of Patent: April 22, 2008Assignee: Nokia CorporationInventors: Pasi Lehtonen, Kimmo Huhtala
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Patent number: 7350293Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.Type: GrantFiled: March 22, 2006Date of Patent: April 1, 2008Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Patent number: 7340826Abstract: A configuration and also a method for the configuration in which, the configuration has at least one electronic device with associated contact connections and at least one printed circuit board with external contacts. The printed circuit board is electrically coupled to the electronic device. At least the metallic surfaces of the configuration are covered by a plasma-polymerized polymer layer.Type: GrantFiled: December 9, 2004Date of Patent: March 11, 2008Assignee: Infineon Technologies AGInventors: Harry Hedler, Jörg Zapf
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Patent number: 7335571Abstract: A method for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial are also described.Type: GrantFiled: August 12, 2004Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Brad D. Rumsey, Matt E. Schwab