Abstract: A wiring board according to the present invention includes a wiring part formed of one or more layers, a first terminal area disposed on one side of the wiring part in a projecting manner, and a second terminal area disposed on the other side of the wiring part. A resist having an opening for a first terminal area is formed on a surface of a composite made of a plurality of metal layers. A part of a first metal layer of the composite is etched through the opening for a first terminal area to form a hole. The hole is subjected to an electroless plating through the opening of the resist. Thus, the hole is filled with an electroplated layer to form a first terminal area. Then, the resist is removed from the composite, and a wiring layer is formed thereon. Subsequently, a solder resist having an opening for a second terminal area is disposed on the wiring layer. The opening of a second terminal area of the solder resist is subjected to an electroplating so as to form a second terminal area.

Abstract: A method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment, the method includes forming a first (interconnection) structure coupled to a substrate to define a shape suitable as an interconnection in an integrated circuit environment and then coupling, such as by coating, a second (interconnection) structure to the first (interconnection) structure to form an interconnection element. Collectively, the first (interconnection) structure and the second (interconnection) structure have a spring constant greater than a spring constant of the first (interconnection) structure.

Abstract: Methods and apparatus are provided for removing plating from a device. The method and apparatus may be used for preparing an electrical connector for connecting at least one wire or other terminus thereto where the electrical connector has at least one electrical contact with a metal coating thereon. The method includes the steps of applying molten solder to the electrical contact whereby the coating dissolves into the molten solder to thereby create a molten coating-solder mixture and rotating the electrical connector whereby the molten coating-solder mixture is removed from the electrical contact.

Abstract: A potassium niobate deposited body includes a substrate, an electrode layer formed above the substrate, and a potassium niobate layer formed above the electrode layer. The potassium niobate layer can include a domain that epitaxially grows in a (110) or (001) orientation, when a lattice constant of orthorhombic potassium niobate is 21/2 c<a<b, and a b-axis is a polarization axis.

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract: A ceramic circuit structure comprising a plurality of ceramic layers and at least one electronic component embedded within the plurality of ceramic layers. Within a first one of the ceramic layers is a via that passes through the ceramic layer. A contact pad is formed on a surface of the ceramic layer. A barrier cap is formed between the via and the contact pad. A dielectric ring covers a peripheral portion of the contact pad and an adjacent portion of the dielectric material layer surface immediately surrounding the contact pad, such that any solder that is applied to the contact does not contact the peripheral portion of the contact pad or the ceramic material.

Abstract: A manufacturing method of a magnetic head device includes a preheating step of irradiating a laser beam to terminal pads of a magnetic head slider and to connection pads of a lead conductor member that is to be electrically connected to the magnetic head slider, a supply step of supplying conductive metal material for connecting the terminal pads and the connection pads during or after the preheating step, and a heating step of performing molten-metal connections between the terminal pads and the connection pads by irradiating a laser beam to the conductive metal material.

Abstract: A method of forming solder connection portions on first electrode pads and on second electrode pads, comprises a first step of arranging solder balls on the first electrode pads by arranging a first mask on a base mask; a second step of arranging solder balls on the second electrode pads by arranging a second mask on the base mask; and a third step of melting the solder balls. The base mask has first opening portions corresponding to the first electrode pads and second opening portions corresponding to the second electrode pads and having a size different from that of the first opening portions. The first mask has opening portions corresponding to the first opening portions and covering the second opening portions. The second mask has opening portions corresponding to the second opening portions and covers the first opening portions.

Abstract: A terminal board having a plurality of terminals on which ball electrodes are formed can be prepared efficiently and economically without having any short-circuiting between terminals when its terminals formed in very close proximity to one another, as on an interposer (1), have their heads made uniform in height by causing the terminals (4) to project from a surface of a board (2) coated with a resist film, and applying a cutting tool (19) to the surface of the board (2) having the terminals project therefrom to carry out lathe turning for the heads of the terminals (4), while having the terminal board held by a rotatable chuck table (17) and rotating the chuck table (17).

Abstract: A method for repair soldering of multi-pole miniature plug connectors on printed circuit boards, having signal contact pins in the SMT design and shroud pins in the THR design. The plug connectors have shrouds whose shroud pins project out on the back of the printed circuit board. Preforms are glued onto the SMD signal contact pins, and the repair plug connectors are set into THR holes of the board with their shroud pins. The signal contact pins are soldered using SMT technology. Subsequently, the shroud pins are soldered from the back of the board. The solder connects with the solder eyes of the solder holes on the back of the board, as well as flows into the ring gap between the metallized inside walls of the solder holes and the shroud pins in the circuit board, and produces a material-lock connection. Finally, the shroud pins that project out are shortened.

Abstract: A method and apparatus for connecting a plurality of coaxial cables to a printed circuit board in a compact connector. The apparatus is generally comprised of a flexible carrier, means for attaching the cable to the flexible carrier, a conductive base plate and a rigid beam providing pressure such that the electrical contact between the coaxial cable and the printed circuit board is maintained. The method generally comprises the steps of stripping the coaxial cables, bonding the coaxial cable to a flexible carrier, positioning the coaxial cables over traces of a printed circuit board providing pressure such that electrical contact is maintained between the cables and the printed circuit board.

Abstract: The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided liquid crystalline polymer LCP where both the high and low temperature LCP are drilled to form a z-axis connection. The single sided conductive layer is a bus layer to form z axis conductive stud within the high and low temperature LCP, followed by a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis connection. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer.

Abstract: A method for production of a semiconductor package which enables uniform conduction processing for all through holes covered by the conduction processing without being limited to any specific structure, is free from surface relief shapes and internal voids, and enables conduction processing simply, in a short time, at a low cost utilizing existing facilities, wherein the conduction processing of the through holes includes a step of press fitting a conductor into the through holes by a ball bonder and a step of flattening the exposed heads of the press-fit conductors by coining.

Abstract: A method for forming bonding pads on a printed circuit board (PCB) with circuit patterns is provided. A plurality of copper patterns are formed on the PCB which are electrically connected to the circuit patterns, and a filler is filled between the copper patterns such that an upper surface of the copper pattern is exposed. A plating layer is then applied to the exposed upper surface of the copper patterns. Protrusion of the plating layer at a lower portion of a copper pattern is prevented, thus reducing an interval between the wire bonding pad(s) and potentially increasing the number of bonding pads which may be effectively formed on a given PCB.

Abstract: A piezoelectric resonator is assembled so that a gap is formed between a resonator element and a plug using a connecting layer formed with a conductive resin, with flattened leads having leading end portions opening in a U-shape. This piezoelectric resonator permits absorption of an impact by elasticity of the leading end portions. Further, operability can be increased by forming a temporary fixing layer using a UV-setting type resin between the leading end portions and the resonator element, or coating a silver past on one of the leading end portions and the resonator element prior to forming a connecting layer. It is thus possible to mass-produce a piezoelectric resonator unit high in impact resistance and reliability with only slight variations of frequency when exposed to high temperatures.

Abstract: A method of manufacturing an ink jet printing head includes: forming a first laminated structure by laminating at least two metal plates having a hole formed thereon and fixing the metal plates to one another by metal-metal junction, and by laminating a plurality of thin plate members having a hole formed thereon, the thin plate members including the metal plates, and fixing the thin plate members to one another; forming a second laminated structure that includes at least a part of a common ink chamber, by laminating a plurality of thin plate members having a hole formed thereon and fixing the thin plate members to one another; and fixing the first laminated structure and the second laminated structure to each other while laminating the first laminated structure and the second laminated structure on each other.

Abstract: Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.

Abstract: Equipment for bonding a flexible printed circuit board made of thermoplastic resin on a printed circuit board includes a heater and a jig. The heater head presses and heats the flexible printed circuit board. The jig prevents the thermoplastic resin from flowing out when the flexible printed circuit is bonded on the printed circuit board. The jig is to be disposed between the flexible printed circuit board and the heater head. The jig includes a thin plate having a base plate and a wing plate. The base plate is parallel to a top surface of the heater head to be sandwiched between the flexible printed circuit board and the heater head. The wing plate is disposed on both sides of the base plate to bend from the base plate.

Abstract: A method and apparatus for holding a screw captive to a printed circuit board (PCB), with a channel formed through the apparatus and a mounting hole formed through the PCB being in alignment to allow a screw to pass therethrough.

Abstract: Provided is a method of manufacturing an electronic part having a plurality of wiring patterns and an insulating layer interposed between the wiring patterns and serving to establish electrical connection between the wiring patterns through an interlayer connecting portion penetrating the insulating layer. In the method, a first step of forming a wiring pattern and a columnar conductor and a second step of forming a layer having a uniform thickness by bonding an insulating sheet from above and pressing the insulating sheet to the height of the columnar conductor with the columnar conductor as a stopper so as to conform the thickness of the insulating sheet to the height of the columnar conductor are repeated.

Abstract: Contact structures exhibiting resilience or compliance are formed. The contact structures may be formed on a sacrificial substrate. The contact structures are attached to an array of electrical connections on a substrate to form a contact assembly. The electrical connections on the substrate may be metallic pads.

Abstract: A method for fabricating electrical connections of a circuit board is provided. The circuit board has a plurality of electrical connection pads thereon. A protective layer is applied on the circuit board and has a plurality of openings for exposing the electrical connection pads. A conductive layer is formed on the protective layer and the electrical connection pads. A resist layer is applied on the conductive layer and has a set of openings for exposing a portion of the conductive layer covering some of the electrical connection pads. A first metal layer is electroplated in the openings of the resist layer. Another set of openings are formed through the resist layer corresponding to the rest of the electrical connection pads. A second metal layer is electroplated on the first metal layer and above the rest of the electrical connection pads to form different electrical connections on the circuit board.

Abstract: A high reliability radiation shielding integrated circuit device comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose tolerance of the circuit die. An integrated circuit device for use in high reliability applications. The integrated circuit device is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates.

Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).

Abstract: A method of making an electrical connector includes the steps of: providing a connector body (2) having an insert (5) defining a recessed area (54a) at one side and a number of channels (54b) at an opposite side; assembling a ground bus (4) to the recessed area of the insert, the ground bus including a carrier strip (46) with a number of fingers (460) extending therefrom; assembling a number of signal contacts (3) to the channels of the insert, each signal contact including a board mounting portion (32); and displacing the carrier strip such that each finger extends into space (320) between the mounting portions of two adjacent signal contacts.

Abstract: An electronic component with bump electrodes includes a surface-protecting insulating film of adequate thickness and bump elements of adequate height, and allows the occurrence of open defects in the manufacturing process to be appropriately reduced. An electronic component with bump electrodes (X1) includes a substrate (11), electrode pads (12) provided on the substrate (11), an insulating film (13) that has openings (13a) in correspondence with the electrode pads (12) and is laminated and formed on the substrate (11), electroconductive connecting elements (14) provided on the electrode pads (12) in the openings (13a), and bump elements (15) that are in direct contact with the electroconductive connecting elements (14) and project from the openings (13a).

Abstract: By forming a terminal at a tip of a lead part of a lead frame, and by fixing this terminal and a connecting pad which was formed on an upper surface of a first printed circuit board, the lead frame is attached to the first printed circuit board. By cutting off a frame part and a tie bar part from the lead frame which was attached to the first printed circuit board, the lead part is separated, and forming is applied to the lead part so as for its tip to be extended over the first printed board. After the lead part which is expanded upward is inserted into a through-hole which was opened in a second printed circuit board, by soldering the lead part and the through-hole, the first printed circuit board and the second printed circuit board are electrically connected.

Abstract: An electrical connector includes a connector body, a plurality of cores and a plurality of electrically conductive contacts disposed in the cores of the connector body. Each of the contacts includes a fusible member attached thereto. Each of the fusible members includes an intermediate portion and two support members disposed on opposite sides of the intermediate portion. The support members are arranged to hang down below a tail portion of the contacts.

Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.

Abstract: A known good die is economically fabricated. A tested integrated circuit is provided which includes a die having a bonding location on an upper surface and a lead. An upper portion of the integrated circuit package is removed or ground away to expose the bonding location. The lead is removed leaving the die and exposed bonding location to provide a known good die. The backside portion of the integrated circuit package is removed or ground away to expose the backside of the die. A contact pad is disposed on the bonding location. The bonding wire and exterior lead are also removed or ground away. The upper portion of the bonding ball is removed to provide a flattened bonding location. Preferably, the tested integrated circuit package provided is a thin small outline integrated circuit package (TSOP), and advantageously may be a packaged flash memory integrated circuit.

Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.

Abstract: A method for heat-treating a plurality of microelectronic structures attached to a non-metallic substrate is disclosed. The method comprises the steps of: (a) placing the non-metallic substrate and the plurality of microelectronic structures in an oscillating electromagnetic field, whereby the plurality of microelectronic structures are heated by the oscillating electromagnetic field and the non-metallic substrate is essentially not heated by the oscillating electromagnetic field; (b) maintaining the non-metallic substrate and the plurality of microelectronic structures in the oscillating electromagnetic field until each of the plurality of microelectronic structures obtains a defined heat-treatment temperature substantially greater than an ambient temperature; (c) removing the non-metallic substrate and the plurality of microelectronic structures from the oscillating electromagnetic field; and (d) cooling the plurality of microelectronic structures to the ambient temperature.

Abstract: Electrical connectors capable of being mounted on circuit substrates by BGA techniques are disclosed. Also, disclosed is a method of manufacturing such connectors. There is at least one recess on the exterior side of the connector elements. A conductive contact extends from adjacent the interior side into the recess on the exterior side of the housing. A controlled volume of solder paste is introduced into the recess. A fusible conductive element, in the form of solder balls is positioned in the recess. The connector is subjected to a reflow process to fuse the solder ball to the portions of the contact extending into said recess. Contacts are secured in the insulative housing of the connector by deformable sections that minimize stress imposed on the central portions of the contacts to promote uniformity of solder volume.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: An electrical connector includes a connector body, a plurality of cores and a plurality of electrically conductive contacts disposed in the cores of the connector body. Each of the contacts includes a fusible member attached thereto. Each of the fusible members includes an intermediate portion and two support members disposed on opposite sides of the intermediate portion. The support members are arranged to hang down below a tail portion of the contacts.

Abstract: A technique for manufacturing a circuit board involves obtaining a plane-shaped structure having layers of circuit board material integrated together, and carving a hole within the plane-shaped structure (e.g., using a single countersinking drill bit). The carved hole includes an inner portion having a substantially uniform inner portion diameter and a connecting portion disposed between the inner portion and an outer surface of the plane-shaped structure. At least part of the connecting portion has a diameter which is larger than the substantially uniform inner portion diameter of the inner portion to improve access to the inner portion. The technique further involves performing a plating process on the plane-shaped structure to provide plating over the hole carved within the plane-shaped structure. The provided plating forms a countersunk via which provides an electrical pathway from the outer surface of the plane-shaped structure to an internal circuit board trace.

Abstract: A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad structure are provided. Each of the bond pads comprise stacked metal layers, at least one lower metal layer and an upper metal layer. When the two pads are connected by a conductive material, they function as a single pad. The lower metal layer of one of the bond pads forms an extension that extends beneath the upper metal layer of the other of the bond pad. The lower metal extension functions to block the etching of a dielectric layer that is put down over the upper metal layers and the underlying substrate, for example, during a passivation etch to form the bond pad opening, to protect the substrate from damage.

Abstract: A matrix type ultrasonic probe is disclosed, which has a backing material, and a plurality of piezoelectric elements having upper and lower face electrodes, respectively, and arrayed in two-dimensional directions on the backing material. The ultrasonic probe further has first mounts provided for every piezoelectric element and fixedly secured to the backing material, signal lines provided for every piezoelectric element and embedded in the backing material to be exposed on the surface of the respective first mounts, and second mounts provided for every piezoelectric element to be fixedly secured to the lower face of the piezoelectric element and formed therein with through-holes. The first and second mounts are fixedly secured to one another by means of conductive adhesive, and the signal lines and the lower face electrodes are electrically connected to one another by means of the conductive adhesive.

Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Abstract: Solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste material. The solder paste material is then formed into precisely controlled ball shapes and geometries.

Abstract: A method of fabricating and using an interconnection element that includes a first element material adapted to be coupled to a substrate and a second element material comprising a material having a transformable property such that upon transformation, a shape of the interconnection is deformed. An example is a material that has a transformable property such that a volume of the first and/or second element material may undergo a thermal transformation from one volume to a different volume (such as a smaller volume) resulting in the deformation of the interconnection element.

Abstract: A method and device for making multiple connections between electrical conductors surrounded by external insulators in overlapping flexible cables by ultrasonic welding. Overlapping conductors to be connected are arranged on a surface of a carrier disposed between a sonotrode and an electrode, the sonotrode and electrode are sequentially aligned the with overlapping points to be welded, and the conductors are ultrasonically welded at each of the overlapping points. The carrier either includes the electrode at least in designated areas, or includes penetrations constructed and arranged to receive an electrode in designated areas.

Abstract: An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external parts. Each of these contact members 1201 has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface 1202 on each end and a layer of reflowable material on each end. Each member is solder-attached (1204) at one end to a chip contact pad 903b, while the other end (1203) of each member is operable for reflow attachment to external parts.

Abstract: A method for forming connections within a multi-layer electronic circuit board 10 which allows for the selective, efficient, and reliable interconnection between at least one conductive layer and a ground plane or layer.

Abstract: A method of manufacturing a multilayer wiring board according to the present invention comprises the step of heating and pressurizing a stacked product to be integrated in a state in which a plurality of double-sided wiring boards (10) having a wiring pattern (12) formed on both surfaces of an insulating layer (11) are laminated through a prepreg (1) obtained by impregnating a resin porous film with a thermosetting resin. The present invention is advantageous to mass production because a gap for forming an insulating layer can easily be controlled, and furthermore, can provide thinner layers of the whole board and is also advantageous to the flattening of the surface of the board.

Abstract: A method of manufacturing an integrated circuit carrier includes providing a substrate. At least one receiving zone for an integrated circuit is demarcated on the substrate. A plurality of island-defining portions is arranged about each of the receiving zones. Rigidity-reducing arrangements are created between neighboring island-defining portions by removing material from the substrate.

Abstract: A method of mounting an electronic part on a board, in which an electronic part and a mounting board on which the electronic part is to be mounted are placed in a vacuum or inert atmosphere, and the electronic part is mounted on the board by bringing the bonding members of the electronic part and the board into contact with each other at normal temperature to thereby mount the electronic part on the board, the method comprising forming the bonding members of at least one of the electronic part and the board out of a solder material, and bringing the bonding members of the electronic part and the board into contact with each other without preprocessing the bonding surfaces of the bonding members.

Abstract: Solder balls such as, low melt C4 solder balls, undergo volume expansion during reflow, such as may occur during attachment of chip modules to a PCB. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodated this volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

Abstract: A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are “stacked up” so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed. The interposer has resilient contact structures extending from both the top and bottom surfaces thereof, and ensures that electrical connections are maintained between the space transformer and the probe card throughout the space transformer's range of adjustment, by virtue of the interposer's inherent compliance.

Abstract: An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.