Abstract: Disclosed are a method of manufacturing a metal wiring buried flexible substrate and a flexible substrate manufactured by the same. The method includes coating a sacrificial layer including a polymer soluble in water or an organic solvent, or a photodegradable polymer on a substrate (Step 1), forming a metal wiring on the sacrificial layer in Step 1 (Step 2), forming a metal wiring buried polymer layer by coating a curable polymer on the sacrificial layer including the metal wiring formed thereon in Step 2 and curing (Step 3) and separating the polymer layer in Step 3 from the substrate in Step 1 by removing through dissolving in the water or the organic solvent or photodegrading only the sacrificial layer present between the substrate in Step 1 and the polymer layer in Step 3 (Step 4).

Abstract: The present invention provides an inventive biosensor that includes multiple regions in which the electrical pattern is formed from different electrically conductive materials. The present invention also provides an inventive method for mass producing biosensors as just described. In one embodiment of this method, first and second different electrically conductive materials are deposited side by side on a portion of an electrically insulating base material, and a plurality of electrical patterns is formed on the portion of the base material. Each electrical pattern includes a first region formed from the first electrically conductive material electrically connected to a second region formed from the second electrically conductive material.

Abstract: A printed circuit board (PCB) prevents damage to tabs of the PCB and pins of a slot by reducing insertion force when the PCB is inserted in the slot. The PCB includes a body portion including a first surface and a second surface and a metal interconnection layer formed on at least one of the first and second surfaces. The metal interconnecting layer includes tabs formed along a first edge of the body portion. An insertion force alleviation portion in which at least a portion of the body portion is removed is formed in the first edge to reduce the insertion force required to seat the PCB within the slot.

Abstract: Provided is a method of manufacturing a printed circuit board including, disposing first and second insulating members and first and second conductive films on both sides of a separating member to perform a thermocompression bonding process on the first and second insulating members and the first and second conductive films on the both sides of the separating member, so as to attach the first member to the second member with the separating member therebetween and attach the first insulating member to the first conductive film and attach the second insulating member to the second conductive film, selectively removing the first and second conductive films to form first and second circuit patterns, and cutting the separating member and the first and second insulating members to separate the first and second insulating members with the first and second circuit patterns from the separating member.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract: A wiring board having an insulation layer, and a buildup structure formed on the insulation layer and including insulation layers. The insulation layer and the buildup structure form a board structure in which a cavity portion having an opening on a surface of the buildup structure on the opposite side of the insulation layer is formed. The cavity portion is extending through one or more of the insulation layers in the buildup structure and has a groove portion formed on the bottom surface of the cavity portion along a wall surface of the cavity portion. The board structure composed of the insulation layer and the buildup structure has a pad formed on the bottom surface of the cavity portion in a position farther from the wall surface of the cavity portion than the groove portion.

Abstract: A method of manufacturing an implantable electronic device, including: providing a silicon wafer; building a plurality of layers coupled to the wafer including an oxide layer coupled to the silicon wafer; a first reactive parylene layer coupled to the oxide layer, an electrode layer coupled to the first reactive parylene layer, and a second reactive parylene layer, coupled to the electrode layer, that chemically bonds to the first reactive polymer layer, and a second polymer layer coupled to the second reactive parylene layer; coating the plurality of layers with an encapsulation, and modifying the encapsulation and at least one of the plurality of layers to expose an electrode site in the electrode layer.

Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.

Abstract: An electrochemical biosensor with electrode elements that possess smooth, high-quality edges. These smooth edges define gaps between electrodes, electrode traces and contact pads. Due to the remarkable edge smoothness achieved with the present invention, the gaps can be quite small, which provides marked advantages in terms of test accuracy, speed and the number of different functionalities that can be packed into a single biosensor. Further, the present invention provides a novel biosensor production method in which entire electrode patterns for the inventive biosensors can be formed all at one, in nanoseconds—without regard to the complexity of the electrode patterns or the amount of conductive material that must be ablated to form them.

Abstract: A method of fabricating a piezoelectric resonator includes providing a bottom electrode and a piezoelectric layer coupled to the bottom electrode. A bottom metal layer of a top electrode is deposited on the piezoelectric layer. A top metal layer of the top electrode is deposited on the bottom metal layer. A photoresist layer is deposited on the top metal layer. The photoresist layer is patterned and etched. The top metal layer is patterned and etched while the etched photoresist layer remains. The bottom metal layer is patterned and etched such that an entire perimeter side surface of the top metal layer is recessed relative to a perimeter edge of the bottom metal layer. The etched photoresist layer is removed. A passivation layer is deposited on the top and bottom metal layers such that the top and bottom metal layers are isolated from a subsequent metal etch step.

Abstract: A printed circuit board includes an inner substrate, a stuffing layer, an adhesive layer and a plurality of second copper trace layer. The inner substrate includes an insulating layer and an copper trace layer formed on a surface of the insulating layer. The first surface includes a low copper density region. In the low copper density region, the area of first surface covered by the copper trace layer is less than 60 percent of the area of the low copper density region. The stuffing layer is only formed on the first inner substrate in the region. The present disclosure also provides a method for manufacturing the printed circuit board.

Abstract: A method of making a transparent touch-responsive capacitor apparatus includes providing a transparent substrate having a material layer formed over the transparent substrate; pattern-wise defining electrically connected first micro-wires over the transparent substrate in a plurality of first transparent conductor areas in the materials layer; pattern-wise defining electrically connected second micro-wires over the transparent substrate in a plurality of second transparent conductor areas spaced apart from the first transparent conductor areas in the material layer, the first micro-wires electrically connected to the second micro-wires; and wherein the height of at least a portion of the first micro-wires is greater than the height of at least a portion of the second micro-wires and the total area occupied by the first micro-wires is less than 15% of the first transparent conductor area and the total area occupied by the second micro-wires is less than 15% of the second transparent conductor area.

Abstract: A manufacturing method of a circuit board is provided. Providing a substrate, where a first laser resistant structure is disposed on a first dielectric layer and at the periphery of a pre-removing area, a second dielectric layer covers the first laser resistant structure, a circuit layer is disposed on the second dielectric layer, a second laser resistant structure is disposed on the second dielectric layer and at the periphery of the pre-removing area, a third dielectric layer covers the circuit layer and the second laser resistant structure. There are gaps between the second laser resistant structure and the circuit layer, and the vertical projection of the gaps on the first dielectric layer overlaps the first laser resistant structure. A laser machining process is performed to etch the third dielectric layer at the periphery of the pre-removing area. The portion of the third dielectric layer within the pre-removing area is removed.

Abstract: One embodiment of the present disclosure provides an apparatus comprising a flex circuit substrate having a core, a first solder mask and first traces disposed on the core on a first side of the flex circuit substrate, and a second solder mask and second traces disposed on the core on a second side of the flex circuit substrate. The first side is opposite to the second side. The apparatus further includes vias formed through the core to electrically couple the first traces to the second traces, and a stiffening structure coupled to the first side of the flex circuit substrate to increase structural rigidity of the flex circuit substrate. The stiffening structure provides structural support to allow attachment of an integrated circuit die to the first side of the flex circuit substrate.

Abstract: Printed circuit boards have circuit layers with one or more via filled holes with copper wraps and methods of manufacturing the same. An embodiment of the present invention provides a method to enhance the consistency of the wraparound plating of through-hole vias of printed circuit boards with (requiring) via filling to provide extra reliability to the printed circuit boards and enables the designers and/or manufacturers of printed circuit boards to design and manufacture boards with relatively fine features and/or tight geometries.

Abstract: Printed conductive lines and a method of preparing them using polymer nanocomposites with low resistivity and high current carrying capacity. Plasma treatment selectively removes polymers/organics from nanocomposites. Subsequent selective metal is deposited on top of the exposed metal surface of the printed conductive lines in order to improve current carrying capacity of the conductive printed lines. The printed conductive lines use a conductive ink or printing process and are then cured thermally and/or by a lamination process. Next, the printed conductive lines are treated with the plasma for 5-15 minutes in order to remove organics. E-less copper (Cu) is selectively deposited only at the conducting particle surface of the printed conductive lines. If desired, e-less gold, silver, tin, or tin-lead can be deposited on top of the e-less Cu.

Abstract: A method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method including a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract: Provided are processes for making multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film.

Abstract: A method of manufacturing a flex-rigid wiring board including disposing a flexible board comprising a flexible substrate and a conductor pattern formed over the flexible substrate and a non-flexible substrate adjacent to each other, covering a boundary between the flexible board and the non-flexible substrate with an insulating layer comprising an inorganic material, providing a conductor pattern on the insulating layer, forming a via hole opening which passes through the insulating layer and reaches the conductor pattern of the flexible board, and plating the via hole opening to form a via connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.

Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.

Abstract: Disclosed herein is a printed circuit board including: a substrate; first upper and lower insulating layers covering upper and lower sides of the substrate; a via penetrating the substrate and the first upper and lower insulating layers to form an electrical connection; and second upper and lower insulating layers covering or surrounding the via, wherein the first upper and lower insulating layers or the second upper and lower insulating layers include a general circuit region including general circuit patterns and circuit patterns connected to the via and a microcircuit region including microcircuit patterns having a smaller circuit line width than that of the general circuit region.

Abstract: A method for manufacturing a FPCB substrate includes the following steps. First, a FPCB material including an insulation layer and an electrically conductive layer formed on the insulation layer is provided. The electrically conductive layer has a first surface and an opposite second surface. The insulation layer has a third surface and an opposite fourth surface. The third surface comes into contact with the second surface. Secondly, a through hole extends from the first surface to the fourth surface is formed. The through hole includes a metal hole in the electrically conductive layer and an insulation hole in the insulation layer. Thirdly, the insulation hole is enlarged to expose a portion of the electrically conductive layer around the metal hole. Finally, the exposed portion is bent to form a hook which passes through the enlarged insulation hole and protrudes out from the fourth surface of the insulation layer.

Abstract: Methods of manufacturing at least a portion of a printed circuit board. The circuit board is formed to include a plurality of sub-assemblies, each of the sub-assemblies including a plurality of circuit layers and having at least one countersink and at least one hole, the countersink having a first diameter and a first depth from a first side of at least one of the sub-assemblies and into the at least one sub-assembly, the hole having a second diameter smaller than the first diameter and a second depth longer than the first depth from the first side of the at least one sub-assembly and into the at least one sub-assembly at the countersink; a metal metalized within the hole and the countersink; a lamination adhesive interposed between one and a corresponding one of the sub-assemblies and having at least one via formed therethrough; and a counter paste filled within the via.

Abstract: A method for manufacturing a multilayer FPCB which includes providing a first substrate, a second substrate and a binder layer; defining an opening on the binder layer; defining a first slit in the dielectric layer of the first substrate; laminating the first substrate, the binder layer and the second substrate; forming a second slit in the conductive layer of the first substrate, the second slit being created so as to align with the first slit, cutting the first substrate, the binder layer and the second substrate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.

Abstract: In one embodiment, a method of fabricating a lead comprises: providing a lead body comprising a plurality of conductive wires; providing a flex film connector structure, the flex film connector structure comprising a plurality of conductive pads on a first portion of the flex film connector structure, a plurality of contacts on a second portion of the flex film connectors, and a plurality of traces electrically connecting the plurality of conductive pads with the plurality of contacts; placing the first portion of the flex film connector adjacent to a cross-section of one end of the lead body; electrically coupling the plurality of conductive pads of the flex film connector structure to the plurality of conductive wires at the one end of the lead body; and wrapping the second portion of the flex film connector structure about the lead body to form a plurality of electrical contacts.

Abstract: A method of fabricating a wiring board includes forming a surface plating layer on a support member, and forming an external connecting pad on the surface plating layer formed on the support member such that an area of the external connecting pad formed on the surface plating layer is smaller than an area of the surface plating layer. The method also includes forming an insulating layer and a wiring layer on a surface of the support member where the external connecting pad is formed, and removing the support member.

Abstract: A process for fabricating a piezoactuated storage device having a tip array and a memory media, which includes but is not limited to: etching the regions on the surface of the silicon wafer to produce substantially pyramidal etch pits by anisotropic etching or chemical etching with potassium hydroxide (KOH); growing an oxide layer on a top surface of the silicon wafer and in the substantially pyramidal etch pits to produce oxidation sharpening of the substantially pyramidal etch pits; forming an array of conductive tips of a nanocarbon film of nanostructured carbon material by deposition, wherein the nanostructured carbon material is ultrananocrystalline diamond (UNCD), ta-C, or diamond-like carbon films; and forming an oxygen diffusion barrier layer by deposition of a TiAl, TaAl, or any other oxygen diffusion barrier layer material on the nanocarbon film.

Abstract: A method and structure for a semiconductor device which provides for an etch of a metal layer such as an interconnect layer which does not affect a thinner layer such as a thin film resistor (TFR) layer, such as a circuit resistor. In one embodiment, a TFR resistor layer is protected by a patterned protective layer during an etch of the metal layer, and provides an underlayer for the metal layer. In another embodiment, the TFR layer is formed after providing the patterned metal layer. The metal layer can provide, for example, end caps for the circuit resistor.

Abstract: The present invention relates to an embedded printed circuit board and a manufacturing method thereof. The present invention provides an embedded printed circuit board including a substrate in which a cavity is formed in a predetermined portion and a wiring layer is formed in a portion without the cavity; a chip inserted into the cavity and including a plurality of pads; a filler filled between the chip and the cavity to fix the chip; and a connection layer formed between the wiring layer and the pads to connect the wiring layer and the pads to each other. Further, the present invention provides a manufacturing method of the embedded printed circuit board.

Abstract: Method of manufacturing printed circuit board, including: providing a substrate including a first circuit layer having a lower land of a via; forming an insulating layer on the first circuit layer; forming a via hole in the insulating layer; filling the via hole with a first metal, thus forming a via; forming a seed layer with a second metal on the insulating layer and an exposed surface of the via; applying a resist film on the seed layer, and forming a resist pattern having an opening for a second circuit layer with a width formed on the via being smaller than a width of the via; plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and removing the resist film, and selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.

Abstract: The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.

Abstract: A method for manufacturing a printed wiring board including preparing a carrier, forming a metal layer on the carrier, forming an etching resist on the metal layer, forming a metal film from the metal layer underneath the resist by removing portion of the metal layer exposed through the resist and part of the metal layer contiguous to the portion of the metal layer and underneath the resist, forming a coating layer on side surface of the film and the carrier, forming a pad on the coating layer, removing the resist, forming a resin insulation layer on the film and surface of the pad, forming an opening reaching the surface of the pad in the insulation layer, forming a conductive circuit on the insulation layer, forming a via conductor connecting the circuit and the pad in the opening, removing the carrier from the film and coating layer, and removing the film.

Abstract: A method for RF matching of an RF plug connector includes a printed circuit board having contact points for RF contacts and contact points for insulation-displacement contacts, with one contact point for the RF contacts in each case being connected to a respective contact point for the insulation-displacement contacts, and with capacitive coupling which causes near-end crosstalk occurring between the RF contacts, with at least one first conductor track being arranged on the printed circuit board and, together with at least one second conductor track which is arranged on and/or in the printed circuit board, forming a capacitor, with at least one frequency-dependent parameter of the arrangement being measured and being compared with a nominal parameter, and the conductor track with which contact is made on one side being partially removed or cut through as a function of the difference.

Abstract: The present invention is to provide a method of manufacturing a printed wiring board with a component mounting pin to connect a printed wiring board and an electronic component.

Abstract: A method of manufacturing an insulating sheet, a method of manufacturing a copper clad laminate, and a method of manufacturing a printed circuit board, as well as a printed circuit board manufactured using these methods are disclosed. The method of manufacturing an insulating sheet can include: forming a thermoplastic reinforcement material, which includes fibers secured by a thermoplastic polymer binder, and in which pores are formed; forming a thermoplastic resin layer such that the thermoplastic reinforcement material is impregnated with a thermoplastic resin; and hot pressing the thermoplastic reinforcement material and the thermoplastic resin layer. This method can be utilized to manufacture an insulating sheet, which has a low rate of moisture absorption and superb electrical properties, including a low dielectric constant (Dk) and low dielectric loss (Df), and in which the fibers can readily be impregnated with the resin.

Abstract: A method for fabrication of passive electronic components includes disposing a sacrificial layer on a carrier and forming a curable resin layer on top of the sacrificial layer and patterning the curable resin to form a cured resin template having multiple pattern levels. A metal material is deposited into the first pattern level to form a first structure. A dielectric material is then formed on exposed portions of the first structure. A nonselective subtractive process is used to expose the sacrificial layer in a bottom of the second pattern level and metal material is deposited into the second pattern level and built up to include a portion which crosses over the dielectric material.

Abstract: The present invention relates to a method of manufacturing a web of a plurality of conductive structures which may be used for example to produce an antenna, electronic circuit, photovoltaic module or the like. The method involved simultaneously patterning at least one pattern in a conductive layer using a plurality of registration marks. The registration marks serve to align and guide the creation of the plurality of conductive structures. Optical brighteners may also be utilized within the adhesive layer and the registration marks of the present invention in order to detect the location where conductive structures are to be placed.

Abstract: A device includes a ground plane, a substrate coupled to the ground plane, and a patterned layer on a surface of the substrate. The patterned layer includes multiple conductive regions, where adjacent conductive regions of the multiple conductive regions are coupled to one another. The patterned layer also includes multiple non-conductive regions interspersed with the multiple conductive regions. The multiple non-conductive regions are complementary to the multiple conductive regions.

Abstract: A touch screen panel is disclosed. The touch screen panel includes a substrate; a plurality of first electrode serials arranged on the substrate; a plurality of second electrode serials arranged to cross over the first electrode serials; and an insulation layer formed at the intersections of the first and second electrode serials and to electrically insulate the first and second electrode serials, wherein each of the first electrode serials comprises a plurality of first electrode patterns and second connection patterns for connecting neighboring first electrode patterns, each of the second electrode serials comprises a plurality of second electrode patterns and first connection patterns for connecting neighboring second electrode patterns, and each of the first electrode patterns comprises a lower layer formed on the substrate and an upper layer formed on the lower layer, and the second connection pattern connects neighboring first electrode pattern upper layers.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages.

Abstract: A method of manufacturing a low capacitance density, high voltage MIM capacitor and the high density MIM capacitor. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

Abstract: Methods are disclosed for manufacturing tuning-fork type piezoelectric vibrating devices. In an exemplary method a metal film is formed on both surfaces of a piezoelectric wafer, followed by application of photoresist. A first metal-film-etching step etches the metal film after removal of the photoresist layer outside the profile outline of the devices. A first piezoelectric-etching step etches the wafer surface but not through to the rear surface; thus, outside the profile outline the metal film is removed. A second metal-film-etching step etches the metal film after removal of the photoresist layer from first groove regions. A second piezoelectric-etching step etches outside the profile outline and the groove regions through to the rear surface.

Abstract: In a method for manufacturing a piezoelectric oscillating circuit in thin film technology, wherein the oscillating circuit includes a predetermined natural frequency and a plurality of layers, first of all at least a first layer of the piezoelectric oscillating circuit is generated. Subsequently, by processing the first layer a frequency correction is performed. Subsequently, at least a second layer of the piezoelectric oscillating circuit is generated and processed for performing a second frequency correction.

Abstract: Disclosed are a carrier substrate including an insulating base material with a copper foil layer formed on at least one surface thereof, a metal layer formed on the copper layer and having a length shorter than that of the copper foil layer, and an insulating layer formed on the metal layer, a fabrication method thereof, a printed circuit board (PCB) using the same, and a fabrication method thereof. Because there is no land at the via and core in the substrate, because a circuit pattern connected with the via can be formed to be finer, so the circuit pattern can be highly integrated and the substrate can become thinner. Thus, a printed circuit board (PCB) having a smaller size and reduced number of layers can be fabricated.

Abstract: The invention relates to a novel process for producing a metal ceramic substrate, especially a copper-ceramic substrate, in which at least one metal foil at a time is applied to the surface sides of a ceramic layer or a ceramic substrate using a high temperature bonding process and the metal foil is structured on at least one surface side for forming conductive tracks, contact surfaces, and the like.

Abstract: A method of manufacturing a wire may include forming a wire pattern, which at least includes a first conductive layer, a second conductive layer, and a third conductive layer arranged in the order stated on a substrate. At least the second conductive layer may have higher etch selectivity than the first and third conductive layers. Side holes may be formed by removing portions of the second conductive layer at ends of the wire pattern, and fine wires may be formed by injecting a masking material into the side holes and patterning the wire pattern by using the masking material as a mask.

Abstract: The disclosure relates to a method for controlling an object configured to be handheld and including vibratory actuators. The method including mechanically coupling a first group of at least one vibratory actuator to a first part of the object, mechanically coupling a second group of at least one vibratory actuator to a second part of the object, the first and the second parts being configured to be able to vibrate independently of each other, and to come into contact with different areas of the hand of the user holding the object, and transmitting to each group of actuators, an electrical signal having a frequency adapted to the resonance frequency of the part to which it is mechanically coupled.

Abstract: A coupling conductor for a YIG filter or YIG oscillator, which may be produced from a metallic foil by eroding, laser cutting and/or etching of a metallic foil. The coupling conductor includes at least one curved section, which at least partially surrounds a YIG element and at least one conductor section.

Abstract: A multilayer printed wiring board is manufactured by a method in which a core substrate is provided, an insulation layer including a thermosetting resin material is formed over the core substrate, an uncured resin layer including a thermoplastic resin material is placed on the insulation layer, the uncured resin layer is cured to form a resin complex layer including a resin complex comprising the thermosetting resin material and the thermoplastic resin material, and a conductive circuit is formed over the resin complex layer.