Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Abstract: Methods for the manufacture of electrical components, such as ultrasound transducers, are illustrated and described. In particular, several embodiments of the methods can include patterning electrodes, such as for the connection of an ultrasound transducer to an electrical circuit. The methods also can include depositing metal on surfaces and making an integrated matching layer for an ultrasound transducer. Ultrasound transducers produced by these methods also are illustrated and described.

Abstract: A solder pad structure with a high bondability to a solder ball is provided. The present invention provides a larger contact area with the solder ball so as to increase the bondability according to the principle that the bondability is positive proportional with the contact area therebetween. The solder pad structure includes a circuit board having a solder pad opening defined by a solder resist layer surrounding a circuit layer. The circuit layer within the solder pad opening is defined as a solder pad. In such a way, after filling the solder ball into the solder pad opening, besides walls of the solder pad opening, there is an extra contact area provided by a geometric shape of the solder pad for further improving the bondability of the solder pad and the solder ball.

Abstract: A method for manufacturing a heat dissipation structure of a printed circuit board includes: forming a barrier layer on the dimple in the first copper plating layer; forming a nickel plating layer; removing the nickel plating layer and the barrier layer on the dimple; forming a second copper plating layer to make the total height of the first copper plating layer and the second copper plating layer in the second opening higher than that of the first copper plating layer in the first opening; filling the dimple in the second copper plating layer with an etching-resistant material; removing the second copper plating layer; removing the nickel plating layer and the etching-resistant material to make the second copper plating layer in the second opening being at the same height as the first copper plating layer in the first opening; and forming the heat dissipation structure by photolithography.

Abstract: An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied of the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern for detecting an alignment error in response to a position of the conductive via. The apparatus for detecting pattern alignment error can detect the alignment of lower wiring in a device with multi-layer wiring.

Abstract: A layer of transparent conductive material is disposed on a surface of a substrate. Further layers of conductive material are deposited on the layer of transparent conductive material or on an opposite surface of the substrate. The layers are selectively etched to yield a layout of pads for mounting electrical components and conductive traces forming an electrical circuit.

Abstract: Methods of backdrilling printed circuit boards (PCBs) to remove via stubs and related apparatuses. The method may include removing a via stub through a combination of backdrilling and chemical etching. The backdrilling may remove a masking layer from the via stub. Portions of an underlying layer may remain in the region of the via stub after the backdrilling is completed. The remaining portions of the underlying layer may be removed in a subsequent etching process thereby removing the via stub from the PCB. As the backdrilling step may be used for the limited purpose of removing the outer layer and portions of the underlying layer remaining in the via can be tolerated, the diameter of the backdrilling need not be as large as traditional backdrilling where all layers within the via must be ensured of being completely removed.

Abstract: A method for making a coaxial cable including an inner conductor, an outer conductor, and a dielectric material layer therebetween may include forming the inner conductor by at least forming a bimetallic strip into a tubular bimetallic layer having a pair of longitudinal edge portions at a longitudinal seam. The bimetallic strip may include an inner metal layer and an outer metal layer bonded thereto and coextensive therewith. Each of the longitudinal edge portions may be folded over. The method may also include forming a welded joint between adjacent portions of the folded over longitudinal edge portions and defining surplus material at the welded joint. The method may further include removing the surplus material at the welded joint and forming the dielectric material layer surrounding the inner conductor. The method may also include forming the outer conductor surrounding the dielectric material layer.

Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract: Provided are a photovoltaic apparatus and a manufacturing method thereof. The photovoltaic apparatus includes: substrate; a back electrode layer disposed on the substrate; a plurality of first intermediate layers disposed on the back electrode layer; a plurality of second intermediate layers disposed on the back electrode layer and each disposed between the first intermediate layers; light absorbing layers disposed on the first intermediate layers and the second intermediate layers; and a front electrode layer disposed on the light absorbing layer.

Abstract: A process for manufacturing an electrical lead having one or more electrodes includes providing an elongate member having at least one polymeric region and further having at least one electrical conductor that extends along at least a part of a length of the elongate member and that is contained in a wall of the elongate member. A length of the at least one electrical conductor is accessed at the at least one polymeric region. An electrically conductive adhesive is applied to the length of the at least one electrical conductor that has been accessed.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A backlight assembly includes a light source part, a base substrate, an insulation layer, and a reflection layer. The base substrate includes a light incident surface into which the light from the light source part is incident, and a light exiting surface adjacent to the light incident surface and through which the light exits. The insulation layer is formed on the light exiting surface of the base substrate. The reflection layer is formed on the insulation layer and forms a concave pattern along with the base substrate and the insulation layer and has an opening portion through which the light exiting from the light exiting surface passes.

Abstract: A method for manufacturing a printed wiring board includes preparing a metal sheet having metal members and connectors joining the metal members, forming a structure having core substrates which are connected through the connectors and which have insulation structure portions covering the metal members, respectively, cutting the connectors in the structure such that an independent core substrate having a recessed portion is formed and a respective one of the connectors is removed from the independent core substrate, and covering the recess portion of the independent core substrate with a resin. The covering of the recess portion includes either forming an interlayer insulation layer on a surface of the independent core substrate or forming interlayer insulation layers on opposing surfaces of the independent core substrate.

Abstract: Embodiments of the invention generally include a method of forming a low cost flexible substrate having one or more conductive elements that are used to form a low resistance current carrying path used to interconnect a plurality of solar cell devices disposed in a photovoltaic module. A surface of the one or more conductive elements will generally comprise a plurality of patterned electrical contact regions that are used to form part of the electrical circuit that interconnects the plurality of solar cell devices. The plurality of electrical contact points form an electrical circuit that has a lower series resistance versus conventional designs. Embodiments may also include a method and apparatus that form the electrical contact regions on an inexpensive conductive material before electrically connecting the anode or cathode regions of a formed solar cell to the conductive material.

Abstract: A circuit board includes a substrate and a conductor layer disposed on the substrate. The conductor layer includes conducting wires and gapped electrostatic protected areas (EPAs) forming a reticulated pattern and electrically isolated from the conducting wires. The manner and method of construction of the circuit board reduces warping and bulging, to induce more reliable component connections. A method for manufacturing the circuit board is also provided.

Abstract: An object of an aspect of the present invention is to provide a method of producing a circuit board that allows highly accurate preservation of the circuit profile and gives a circuit having a desired depth in preparation of a fine circuit by additive process.

Abstract: The present invention relates to the field of laser processing methods and systems, and specifically, to laser processing methods and systems for laser processing multi-material devices. Systems and methods may utilize high speed deflectors to improve processing energy window and/or improve processing speed. In some embodiments, a deflector is used for non-orthogonal scanning of beam spots. In some embodiment, a deflector is used to implement non-synchronous processing of target structures.

Abstract: Disclosed are a multi-layer substrate and a manufacturing method of the multi-layer substrate. By employing a carrier to alternately form dielectric layers and metal structure layers thereon. Each dielectric layer adheres with the adjacent dielectric layer to embed the metal structure layers in the dielectric layers corresponding thereto. Comparing with prior arts, which have to use prepregs when hot pressing and adhering different layers of different materials, the present invention takes fewer processes, thus, fewer kinds of materials without using prepregs. Therefore, the present invention can promote the entire quality and yield of manufacturing the multi-layer substrate to satisfy mechanical characteristic matching of the multi-layer substrate and to reduce cost of the whole manufacturing process.

Abstract: Methods of fabricating microfluidic structures featuring substantially circular channels are provided. The methods involve (a) providing a patterned wafer comprising at least one exposed electrically conductive region and at least one exposed electrically insulating region; (b) electroplating an inverse channel portion with substantially semicircular cross section onto the wafer, thereby forming a first master mold; (c) employing the first master mold so as to emboss a channel portion in a first polymer sheet; and (d) aligning and bonding the first polymer sheet with a second polymer sheet having a corresponding channel portion such as to define a first channel with substantially circular cross section between the polymer sheets.

Abstract: This disclosure relates to an improved electrochemical sensor that has a simplified electrode assembly. The electrode assembly incorporates electrodes into or onto a single polymeric substrate. The working electrode can be porous, to enable an analyte, such as a toxic gas, to access an electrode-electrolyte interface. Ionic connection between electrodes can be made by an electrolyte on a back side of the electrode assembly, and external electronic circuitry can be connected directly to the electrode assembly. This construction dramatically simplifies the sensor, resulting in reduced costs and potentially improved performance. The construction is compatible with batch fabrication methods.

Abstract: A process of electronic structure is provided. First, a carrier board is provided, in which the carrier board has a first surface. Next, a first release layer is formed on the first surface of the carrier board. The first release layer has property of withstanding high-temperature and temporary adhesion capability and the first release layer entirely or mostly overlays the first surface. Then, a built-up structure is formed on the first release layer. Finally, a separating process is performed so that the built-up structure is separated from the carrier board to form an electronic structure.

Abstract: A radiation detector using gas amplification includes: a first electrode pattern which is formed on a first surface of an insulating member and has a plurality of circular openings; and a second electrode pattern which is formed on a second surface of the insulating member opposite to the first surface thereof and has convex portions of which respective forefronts are exposed to centers of the openings of the first electrode pattern; wherein a predetermined electric potential is set between the first electrode pattern and the second electrode pattern; wherein edges of the first electrode pattern exposing to the openings are shaped in respective continuous first curved surfaces by covering the edges thereof with a first solder material.

Abstract: According to the present invention, a circuit board having a further-microfabricated circuit pattern that can be manufactured in further simplified steps is obtained. For such purpose, a mold 10, which has protrusions 11 formed in a pattern corresponding to a circuit pattern, is used to apply a conductive material layer (metal paste) 13 to head portions of the protrusions 11 of the mold 10. The mold is heat- and pressure-welded to the surface of a substrate 20 that is made of a resin film or the like. Accordingly, a pattern comprising the protrusions 11 and the conductive material layer (metal paste) 13 are transferred to the substrate 20. After transfer, the resin substrate (resin molding 30) is immersed in a copper sulfate plating bath for electrolytic plating treatment. Copper ions in the plating bath were deposited inside each recess 31 while the conductive material layer 13 is used as a base material for the formation of a metal wiring 32.

Abstract: A method for manufacturing a surface acoustic wave filter device includes a step of forming grooves in one principal surface of a piezoelectric substrate, a step of embedding a metallic film in the grooves to form IDT electrodes, a step of performing a process of removing a portion of the piezoelectric substrate from the one principal surface of the piezoelectric substrate, thereby forming a recessed portion including the bottom surface in which the IDT electrodes are embedded, and a step of bonding a cover member to the piezoelectric substrate.

Abstract: The present invention provides a method for forming a metal pattern comprising a step of forming a polymer layer on a substrate; (a2) a step of applying a metal ion or the like to the polymer layer; (a3) a step of forming a conductive layer by reducing the metal ion or the like; (a4) a step of forming a patterned resist layer on the conductive layer; (a5) a step of forming a metal pattern by electroplating in the regions where the resist layer is not formed; (a6) a step of separating the resist layer; (a7) a step of removing the conductive layer from regions protected by the resist layer; and (a8) a step of performing a hydrophobilizing treatment.

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract: A printed circuit board (“PCB”) includes a first pattern structure, a second pattern structure, a third pattern structure, and a fourth pattern structure. The first pattern structure includes a first ground pattern. The second pattern structure includes a first line pattern overlapping the first ground pattern and a second ground pattern electrically insulated from the first line pattern. The third pattern structure includes a third ground pattern overlapping the first line pattern and a second line pattern overlapping the second ground pattern. The fourth pattern structure includes a fourth ground pattern overlapping the second line pattern. Therefore, the PCB may decrease noise.

Abstract: Printed circuit boards have circuit layers with one or more copper filled through-holes and methods of manufacturing the same. An aspect of an embodiment of the present invention enhances thermal characteristics of filled through-holes of printed circuit boards to provide extra reliability to the printed circuit boards. In one embodiment, a printed circuit broad has a plurality of through-holes to connect copper patterns on different layers of the printed circuits broad. Here, at least one of the through-holes is copper plated closed at both ends with at least 70% volume of the through-hole plated with copper to, e.g., enhance thermal characteristics of the through-hole, thereby providing extra reliability to the printed circuit board. In one embodiment, the printed circuit board includes a surface conductor (or cap) that is directly plated over the copper filled barrel plated through-hole.

Abstract: The invention aims to provide substrate treatment equipment that can automatically collect a substrate in a normal condition without needing manual operation. The equipment includes a substrate holder for holding substrates in a multistage manner and a substrate transfer unit for transferring the substrates into the substrate holder, wherein a substrate holding condition of the substrate holder is sensed by a sensing section. The sensing section has photo-sensors, and sensing waveforms sensed by the photo-sensors are compared with a normal waveform. A control section is provided, which controls a substrate transfer unit such that substrates other than at least a substrate that was determined to be abnormal are transferred by the unit.

Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

Abstract: A test point design comprising: a circuit board comprising a plurality of layers including a power plane and a ground plane, the circuit board further comprises a differential pair of signal lines including a first signal line and a second signal line; and a pair of test point pads including a first test point pad connected to the first signal line and a second test point pad connected to the second signal line, wherein a first portion of the power plane and a first portion of the ground plane below the first test point pad are removed and a second portion of the power plane and a second portion of the ground plane below the second test point pad are removed.

Abstract: A MEMS device (40) includes a base structure (42) and a microstructure (44) suspended above the structure (42). The base structure (42) includes an oxide layer (50) formed on a substrate (48), a structural layer (54) formed on the oxide layer (50), and an insulating layer (56) formed over the structural layer (54). A sacrificial layer (112) is formed overlying the base structure (42), and the microstructure (44) is formed in another structural layer (116) over the sacrificial layer (112). Methodology (90) entails removing the sacrificial layer (112) and a portion of the oxide layer (50) to release the microstructure (44) and to expose a top surface (52) of the substrate (48). Following removal, a width (86) of a gap (80) produced between the microstructure (44) and the top surface (52) is greater than a width (88) of a gap (84) produced between the microstructure (44) and the structural layer (54).

Abstract: A process for producing a circuit module including, carried out in this order, preparing a ceramic carrier substrate having ceramic substrate pads for mounting electronic parts, forming solder paste layers on the ceramic substrate pads, forming precoated solder layers by heating the ceramic carrier substrate having the solder paste layers on the ceramic substrate pads to melt the solder paste layers, and then cooling for solidifying the solder, preliminarily fixing stepped lid having protrusions adjacent to a cavity and dents adjacent to the cavity with the protrusions intervening therebetween to the precoated solder layers of the ceramic carrier substrate and joining the stepped lid to the ceramic carrier substrate with solder by placing the ceramic carrier substrate having the stepped lid preliminarily fixed to the precoated solder layers in a reflow furnace.

Abstract: A method of producing a piezoelectric thin film resonator is provided. A sacrificial layer is formed on a part of the piezoelectric film. The sacrificial layer is patterned, and thereafter an upper electrode is formed on the piezoelectric layer. The method further includes removing the sacrificial layer formed on the piezoelectric layer; and patterning the piezoelectric film. In the step of removing the sacrificial layer, the sacrificial layer is removed such that at least a portion of the periphery of the upper electrode has a reversely tapered shape that reflects the tapered portion of the sacrificial layer, and in the step of patterning the piezoelectric film, the piezoelectric film is removed such that a lower end of the reversely tapered periphery of the upper electrode is placed so as to coincide with or to be in the vicinity of an end portion of the patterned piezoelectric film.

Abstract: Methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices include forming memory cells. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. A conductive line is formed in a trench in the substrate.

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract: A projective capacitive touch sensor structure includes following elements. Two second transparent patterned electrodes are disposed on a substrate and located at two sides of a first transparent patterned electrode. A bridging wire strides over the first transparent patterned electrode and electrically bridges the second transparent patterned electrodes to form a conducting wire. A transparent dielectric pad is disposed between the bridging wire and the first transparent patterned electrode. A dielectric portion of the transparent dielectric pad located above the first transparent patterned electrode and the second transparent patterned electrodes includes an upper surface, a lower surface and an inclined side surface connecting the upper surface and the lower surface, an area of the upper surface is 70%-95% of an area of the lower surface, and an included angle between the inclined side surface and the lower surface is an acute angle.

Abstract: A flexible circuit electrode array with more than one layer of metal traces comprising: a polymer base layer; more than one layer of metal traces, separated by polymer layers, deposited on said polymer base layer, including electrodes suitable to stimulate neural tissue; and a polymer top layer deposited on said polymer base layer and said metal traces. Polymer materials are useful as electrode array bodies for neural stimulation. They are particularly useful for retinal stimulation to create artificial vision, cochlear stimulation to create artificial hearing, or cortical stimulation many purposes. The pressure applied against the retina, or other neural tissue, by an electrode array is critical. Too little pressure causes increased electrical resistance, along with electric field dispersion. Too much pressure may block blood flow.

Abstract: Forming a thin film acoustic device by patterning a layer of non-conducting material on a first side of a substrate to expose a portion of the first substrate side; depositing layers of conducting material on the layer of non-conducting material and the exposed portion of the first substrate side; depositing a layer of piezoelectric material on the layers of conducting material; depositing and patterning additional layers of material on the layer of piezoelectric material to form a first device electrode; depositing and patterning a masking layer on a second side of the substrate to expose a portion of the second substrate side; etching away the exposed substrate portion to expose the patterned layer of non-conducting material and a portion of the layers of conducting material; and etching away the exposed portion of the layers of conducting material to form a second device electrode.

Abstract: A manufacturing method for a printed wiring board includes forming an electroless plated film on an interlayer resin insulation layer, forming on the electroless plated film a plating resist with an opening to expose a portion of the electroless plated film, forming an electrolytic plated film on the portion of the electroless plated film exposed through the opening, removing the plating resist using a resist-removing solution containing an amine, reducing a thickness of a portion of the electroless plated film existing between adjacent portions of the electrolytic plated film by using the resist-removing solution, and forming a conductive pattern by removing the portion of the electroless plated film existing between the adjacent portions of the electrolytic plated film by using an etchant.

Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board, by forming at least one bump for interlayer conduction on a surface of a board and stacking an insulation layer on the surface of the board, can include the operations of forming at least one dam on the surface of the board that surrounds a region corresponding to the bump, forming the bump by printing conductive paste onto the region corresponding to the bump, and stacking the insulation layer onto the surface of the board. This method can be utilized to improve productivity and resolve the problem of spreading.

Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board can include: forming surface roughness on an insulation layer, coating a chemical compound onto the insulation layer that lowers the surface energy of the insulation layer, and forming a circuit pattern by inkjet printing on the insulation layer coated with the chemical compound. Certain embodiments of the invention can be utilized to improve adhesive strength between the insulation layer and the inkjet-printed circuit patterns, suppress spreading in the inkjet-printed circuit patterns to improve resolution, and reduce manufacturing costs by forming the circuits using inkjet printing.

Abstract: According to one embodiment, a ceramic circuit board includes a ceramic substrate, a copper circuit plate and a brazing material protrudent part. The copper circuit plate is bonded to at least one surface of the ceramic substrate through a brazing material layer including Ag, Cu, and Ti. The brazing material protrudent part includes a Ti phase and a TiN phase by 3% by mass or more in total, which is different from the total amount of a Ti phase and a TiN phase in the brazing material layer that is interposed between the ceramic substrate and the copper circuit plate. The number of voids each having an area of 200 ?m2 or less in the brazing material protrudent part is one or less (including zero).

Abstract: An embodiment of the disclosed technology provides a method for preventing electrostatic breakdown during the manufacturing process of the array substrate. The method comprises: when forming a conductive pattern of a substrate, connecting conductive lines for forming the conductive pattern with a closed conductive ring on a same layer as the conductive lines in a peripheral region of the substrate, and wherein when electrostatic charges are generated over the metal line, the electrostatic charges are led to the closed conductive ring.

Abstract: A method for manufacturing a touch screen sensor assembly that includes providing a first transparent substrate, depositing a first non-metallic conductive layer onto the first substrate, removing the first conductive layer from a viewing portion of the first substrate, depositing a second non-metallic conductive layer onto the viewing portion, and removing portions of the second and first conductive layers to respectively form a first electrode pattern and a plurality of traces. The disclosed method also includes providing a second transparent substrate, depositing a third non-metallic conductive layer onto a viewing portion of the second substrate, removing portions of the third conductive layer to form a second electrode pattern, and bonding the first substrate to the second substrate using an optically clear adhesive. Each trace on the first substrate formed from the first conductive layer is electrically coupled to at least one electrode of either the first or second electrode patterns.

Abstract: A method for manufacturing a coupled resonator device includes forming a first BAW-device on a first substrate, forming a second BAW-device on a second substrate, and bonding the first and the second BAW-device such that the bonded first and second BAW-device are sandwiched between the first and second substrate.

Abstract: An object is to obtain a dielectric layer constituting material, a capacitor circuit forming piece, etc. in which unnecessary dielectric layer is removed except capacitor circuit parts that improve accuracy of position of an embedded capacitor circuit in a multi-layer printed wiring board. For the purpose of achieving the object, “a method for manufacturing a dielectric layer constituting material characterized in that step a is a step for forming a first electrode circuit by etching a conductor layer on one side of a metal clad dielectric comprising a conductor layer on each side of a dielectric layer; step b is a step for removing the dielectric layer that is exposed between the first electrode circuits to manufacture the dielectric layer constituting material; and the step a is conducted and then the step b is conducted” is adopted.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the resists, and forming a wiring having a pad and a conductive circuit thinner than the pad by removing the metal film exposed through the removing of the plating resist, a solder-resist layer on the surface of the board and wiring, in the layer an opening exposing the pad and a portion of the circuit contiguous to the pad, a solder film on the pad and portion of the circuit exposed through the opening, and a solder bump on the pad by solder reflow.