With Molding Of Insulated Base Patents (Class 29/848)
  • Patent number: 4944087
    Abstract: A highly accurate circuit pattern in intimate contiguous relationship with a curved plastic body and a method of manufacture thereof. In accordance with the present invention, circuit pattern is detachably fixed to a flexible substrate and is placed into a mold. A molding compound is then forced into the mold pressing the circuit against the mold wall and filling all of the mold voids. The molded product is thereafter removed from the mold. The flexible substrate, on which the metallic circuit is printed, is removed from the molded product leaving the metallic circuit imbedded into the molded product.
    Type: Grant
    Filed: October 5, 1988
    Date of Patent: July 31, 1990
    Assignee: Rogers Corporation
    Inventor: Vincent R. Landi
  • Patent number: 4924590
    Abstract: A method for the manufacturing of a metal core pc board which provides for manufacturing of two or three dimensional metal core pc boards of any form with or without throughplating. The manufacturing of such pc boards can occur by injection molding, injection/compressing molding or by a pressing method. High-heat resistant thermoplastics, as well as duroplastics are preferably employed as pc board materials. A metal with good thermal conductibility is used for the core. The material is selected such that the thermal expansion coefficients of the metal core and the pc board material are optimally equal.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: May 15, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helmut Hadwiger, Hans Schmidt
  • Patent number: 4920640
    Abstract: Dense ceramic sheets suitable for electronic substrates are prepared by hot pressing ceramic green sheets containing ceramic powder and organic binders which leave no undesirable residue upon pyrolysis in the absence of oxygen. Boron nitride sheets made of boron nitride powder in a similar binder are placed on each side of the ceramic green sheet to form a composite. After hot pressing the composite so as to remove the binder and densify the ceramic, the BN layers are removed.
    Type: Grant
    Filed: January 27, 1988
    Date of Patent: May 1, 1990
    Assignee: W. R. Grace & Co.-Conn.
    Inventors: Jack H. Enloe, John W. Lau, Christian B. Lundsager, Roy W. Rice
  • Patent number: 4918812
    Abstract: Two cores for circuit boards or cards are simultaneously processed.In particular, two cores are provided wherein each is a dielectric material having conductive planes on both major surfaces thereof. The two cores are temporarily fixed together by sealing the peripheral face planes thereof.The two external conductive planes are then simultaneously processed to thereby form signal patterns.The seal is then removed from the peripheral face planes and the two cores are separated from each other, thereby simultaneously providing the two cores.
    Type: Grant
    Filed: June 29, 1988
    Date of Patent: April 24, 1990
    Assignee: International Business Machines Corporation
    Inventor: Robert E. Ruane
  • Patent number: 4912844
    Abstract: A punch has a planar surface and raised portions extending from the planar surface. First ones of the raised portions may have a height of approximately 3-25 mils. Second ones of the raised portions may have a greater depth than the first raised portions. The punch may be heated and/applied to the planar surface of a substrate which may also be pre-heated and which has properties of becoming deformed when subjected to heat and pressure. The punch produces cavities and grooves in the substrate at the positions of the raised portions. Electrical components may be disposed in the cavities in the substrate and an electrically conductive material may be disposed in the grooves to communicate with the electrical components. The raised portions in the punch may be provided by printed circuit techniques or by matching or by laser techniques. Alternatively, a foil may be disposed on the planar surface of the punch and the raised portions of the punch.
    Type: Grant
    Filed: August 10, 1988
    Date of Patent: April 3, 1990
    Assignee: Dimensional Circuits Corporation
    Inventor: Frederick Parker
  • Patent number: 4888307
    Abstract: A method for correctly positioning a metallic plate supporting a semiconductor chip in a mold used for encapsulation, wherein according to a first solution, at least a pair of retractable locating pins are utilized together with a lead connected to the supporting plate. The ends of the locating pins are retracted in the final phase of encapsulation, from the surfaces of the plate, whereas in the initial phase they are in direct contact with the surfaces. According to a second solution, a pair of clamping pins are indirectly connected to the plate through the interposition of insulating thicknessings.
    Type: Grant
    Filed: August 27, 1987
    Date of Patent: December 19, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Antonio P. Spairisano, Marino Cellai
  • Patent number: 4875966
    Abstract: An improved pressure transfer plate assembly is provided for an apparatus to heat bond flexible printed circuits in a hydraulic press. The plate assembly comprises aluminum top and bottom plates with two or more thin sheet liners in between. A plurality of workpiece-locating pins are based in stainless steel plug inserts in the bottom plate to give excellent wear resistance. The alignment of top and bottom plates is effected by a plurality of plate-alignment pins screwed into the bottom plate and having slotted head portions to allow for easy removal and installation.
    Type: Grant
    Filed: September 12, 1988
    Date of Patent: October 24, 1989
    Assignee: General Dynamics Corp., Pomona Div.
    Inventor: Louis S. Perko
  • Patent number: 4867839
    Abstract: A process for forming a circuit substrate comprising placing an electrodeposited metal foil having a rough surface provided with a large number of fine projections in a cavity of a mold in such a manner that the rough surface faces an inside of the mold cavity; pouring a melting resin into the mold cavity to form a molded article; peeling the metal foil from the molded article to form a large number of fine concavities corresponding to the projections; electroless-plating the resin base to form a metal film; and photoetching to form a circuit pattern on the resin base.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: September 19, 1989
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takeshi Sato, Katsuya Fukase, Kiyotaka Shimada, Hirofumi Uchida
  • Patent number: 4857483
    Abstract: To encapsulate integrated circuits mounted on continuous dielectrical strips (surface-mounted circuits) it is proposed to transfer mold a thermosetting resin around circuits carried by the strip, the resin being injected outside the parting plane of the mold, contrary to the usual practice in this field. The protection of the circuits is improved while, at the same time, the ability to test the strip is preserved.
    Type: Grant
    Filed: December 29, 1987
    Date of Patent: August 15, 1989
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Francis Steffen, Jean Labelle
  • Patent number: 4825539
    Abstract: Green sheets can be laminated without destroying the cross-sectional shape of a metallization pattern printed on a green sheet by burying the pattern in the green sheet while freezing the pattern and heating the green sheet until the green sheet containing the pattern has a flat top surface. Accordingly, the pattern is buried in the green sheet and the shape of the pattern is preserved. When laminated and pressed, the pattern is not damaged since it has been buried in the green sheet.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: May 2, 1989
    Assignee: Fujitsu Limited
    Inventors: Kanji Nagashima, Yuji Yamada, Toshihiro Kusagaya
  • Patent number: 4817276
    Abstract: A ceramic substrate for densely integrated semiconductor arrays which is superior in a coefficient of thermal expansion, dielectric constant, strength of metallized bond, and mechanical strength, comprising a sintered body composed essentially of mullite crystals and a non-crystalline binder composed of SiO.sub.2, Al.sub.2 O.sub.3, and MgO, is provided.
    Type: Grant
    Filed: April 2, 1986
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Gyozo Toda, Takashi Kuroki, Shousaku Ishihara, Naoya Kanda, Tsuyoshi Fujita
  • Patent number: 4811482
    Abstract: A method for producing circuit boards having embedded three-dimensional wiring patterns and exposed mounting pads for receiving surface mounted components and terminals in which the exposed mounting pads are formed by forming junctions between the conductors and a substrate which is in turn used as at least a portion of mold for receiving hardenable material for encapsulating the conductors and forming the circuit board and in which the junctions become exposed to define mounting pads when the substrate is removed.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: March 14, 1989
    Inventor: Kenneth W. Moll
  • Patent number: 4812420
    Abstract: A method of producing a semiconductor device having a light transparent window, includes: a process of die bonding a chip onto a lead frame; a process of attaching a wall surrounding a picture element to either of the external contour surface of the surface of the chip or the light transparent window surrounding the picture element; a process of inserting the chip and the light transparent window into a metal mold in such a manner that an empty closed space is produced between the chip and the light transparent window via the wall; and a process of plastic molding the device except for the light transparent window by filling resin into the metal mold and making the resin hardened.
    Type: Grant
    Filed: September 30, 1987
    Date of Patent: March 14, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Sadamu Matsuda, Kunito Sakai, Takashi Takahama
  • Patent number: 4790902
    Abstract: A thin metal layer with a thickness of 1 to 5 .mu. is formed electrolytically (S2) on an electrically conductive single-plate substrate having a predetermined roughness, a resist mask is formed (S3) on the surface of the thin metal layer, and a conductor circuit is then electroformed thereon (S4) using copper. After the surface of the conductor circuit is roughened (S5), the conductor circuit, along with the single plate and the interposed thin metal layer, is stacked on an insulating substrate for lamination, and the individual layers are adhered integrally to one another by the application of heat and pressure (S7). Then, the single plate only is peeled off (S8), and the exposed thin metal layer is removed by etching (S9). The thin metal layer and the conductor circuit are electroplated under high-speed conditions including a solution contact speed of 2.6 to 20 m/sec and a current density of 0.15 to 4.0 A/cm.sup.
    Type: Grant
    Filed: October 16, 1987
    Date of Patent: December 13, 1988
    Assignee: Meiko Electronics Co., Ltd.
    Inventors: Tatsuo Wada, Keizo Yamashita, Tasuku Touyama, Teruaki Yamamoto
  • Patent number: 4766671
    Abstract: A method of manufacturing a ceramic electronic device includes the steps of: forming a pattern of a predetermined shape made of a photosensitive resin; forming an electrical circuit element on a ceramic green sheet; stacking and pressing the pattern, the ceramic green sheet having the electrical circuit element thereon, and at least one ceramic green sheet to prepare a laminated body; and sintering the laminated body. A ceramic electronic device integrally including a cavity and the electrical circuit element therein is manufactured by this method.
    Type: Grant
    Filed: October 24, 1986
    Date of Patent: August 30, 1988
    Assignee: NEC Corporation
    Inventors: Kazuaki Utsumi, Hideo Takamizawa, Mitsuo Tsuzuki, Michihisa Suga, Sadayuki Takahashi
  • Patent number: 4758459
    Abstract: A circuit board is molded of a heat resistant synthetic resin. Component mounting positions are formed at the time of molding, the mounting positions comprising formations, such as recesses or protrusions, on at least one surface. A circuit pattern is formed on at least one surface and the circuit pattern extends to and over a surface of each formation. A circuit board can be planar or non-planar and be of any desired shape, not necessarily rectangular.
    Type: Grant
    Filed: January 28, 1987
    Date of Patent: July 19, 1988
    Assignee: Northern Telecom Limited
    Inventor: Mahendra C. Mehta
  • Patent number: 4741101
    Abstract: A contact device comprises a resiliently deformable member having two opposite surface regions, and strips of conductive material bonded to the deformable member at one of its two opposite surface regions. The strips of conductive material are of substantially uniform width, substantially parallel to each other and substantially uniformly spaced from each other. The width and spacing of the strips are less than the width and spacing of the terminal areas of the conductor runs that are to be connected by means of the contact device, so that each terminal area contacts at least two strips of the contact device.
    Type: Grant
    Filed: September 29, 1986
    Date of Patent: May 3, 1988
    Assignee: Tektronix, Inc.
    Inventors: William E. Berg, Andrew E. Finkbeiner
  • Patent number: 4689103
    Abstract: A plurality of physically separate plastic substates are injection molded, each with at least one pattern of channels formed in a surface of thereof defining a conductive circuit to be formed. The plurality of substrates are then physically connected in a common planar array either by inserting them in corresponding receptacles in a carrier board, by mating peripheral connecting elements, by using adhesive or by some other suitable connecting mechanism. Where a carrier board with pre-formed receptacles is not utilized, the individual substrates in the array are pierced and replaced. The planar array is processed to simultaneously form a conductive circuit on each substrate consisting of metal deposited in its pattern of channels. The planar array of metallized substrates may then be stuffed with electronic components on an automatic insertion machine, wave soldered. The individual finished circuit boards are then pressed out.
    Type: Grant
    Filed: November 18, 1985
    Date of Patent: August 25, 1987
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: Vito D. Elarde
  • Patent number: 4688328
    Abstract: A printed circuit board assembly is disclosed which includes a printed circuit board having in situ molded members for mechanically securing electrical and mechanical components and the like to the printed circuit board. The printed circuit board is manufactured using a method wherein a printed circuit board is initially prepared with the required printed circuit patterns and with apertures for in situ molded members and for the leads of the electrical components. The required molded members are then molded in situ in specified apertures of the printed circuit board. The electrical components are thereafter mechanically secured in place with the in situ molded members and the leads of the components are connected to the contact pads of the printed circuit pattern.
    Type: Grant
    Filed: December 8, 1986
    Date of Patent: August 25, 1987
    Assignee: RCA Corporation
    Inventors: Robert W. Jebens, Gerard Samuels
  • Patent number: 4682415
    Abstract: A method of making printed circuits which comprises passing a non-conductive strip of material past a device which repeatedly imparts a desired circuit pattern onto the passing strip so that a succession of identical printed circuit zones are created along the length of the strip. The strip is subsequently wound into a coil which can be stored for use as desired when printed circuit assemblies are to be fabricated. Fabrication of an assembly comprises unwinding the strip from the coil and severing of the strip between the individual printed circuit zones. A backing can be joined to the unwound strip before severing.
    Type: Grant
    Filed: October 28, 1985
    Date of Patent: July 28, 1987
    Assignee: U.S. Product Development Company
    Inventor: Robert Adell
  • Patent number: 4679320
    Abstract: A process for producing a multilayer ceramic circuit board with copper including the steps of:forming green sheets by doctoring a slurry which includes 100 parts by weight of glass ceramic particles, 5 to 20 parts by weight of a thermally depolymerizable resin binder, 2 to 10 parts by weight of a plasticizer, and up to 2 parts by weight of a fatty acid ethylene oxide adduct type, deflorculant. The glass ceramic includes 20 to 70% by weight of alumina, and 30 to 80% by weight of SiO.sub.2 -B.sub.2 O.sub.3 glass. The process further includes the steps of forming via holes through the green sheets, screen-printing a copper paste on the green sheets, and laminating the green sheets, thereby forming a multilayer structure and firing the multilayer structure in a non-oxidizable atmosphere.
    Type: Grant
    Filed: November 26, 1985
    Date of Patent: July 14, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihiko Imanaka, Hiromi Ogawa, Mineharu Tsukada, Etsuro Udagawa, Kazuaki Kurihara, Hiromitsu Yokoyama, Nobuo Kamehara
  • Patent number: 4669181
    Abstract: A thermal heating and insulating unit is manufactured by molding in situ a block of thermal insulating material about an electrical resistance element. The resistance element is first made from a continuous wire of electrical resistance material and formed into a serpentine configuration with a plurality of segments interconnected by bends at the ends of the segments. In a preferred construction, the segments are straight and the bends at the ends of the segments are in opposite directions. The resistance element is positioned in a mold on a plateau above a porous bottom, the bends overlapping the plateau, and a slurry of inorganic fibers, water and a binder is introduced into the mold to a lever above the plateau, the liquid component of the slurry passing through the porous bottom, and the fibers and a portion of the binder collecting on the porous bottom to form a block with a slot confronting the resistance element, the bends of the resistance element being embedded in the block.
    Type: Grant
    Filed: December 19, 1985
    Date of Patent: June 2, 1987
    Assignee: General Signal Corporation
    Inventor: Ludwig Porzky
  • Patent number: 4661301
    Abstract: A process for continuously molding a plate for an electrical printed circuit board wherein a resin containing uniformly distributed hollow microspheres having a specific gravity different from that of the resin is extruded into a vertically disposed moving double belt press maintained at a temperature which allows the extruded plate to harden almost completely. The plate exists the vertically disposed press maintaining a flexibility sufficient to be passed around a roller into a horizonal position where subsequent processing steps may be applied, such as lamination of reinforcing fiber and coating with a conductive material.
    Type: Grant
    Filed: August 14, 1985
    Date of Patent: April 28, 1987
    Assignee: Toray Industries, Inc.
    Inventors: Reisuke Okada, Hisami Fujino
  • Patent number: 4651417
    Abstract: An improved method is disclosed for forming a printed circuit board. The desired printed circuit is established on the surface of a plastic core sheet by placing recesses therein conforming to the desired circuit, and a conductive coating is then applied so that the coating is retained at the recesses. Circuit patterns are preferably pressed into one or both sides of the plastic core sheet, and holes can be placed through the sheet to allow circuit connections between the patterns on the opposite sides of the sheet and to receive electrical leads of circuit components. A thin conductive coating is applied by vacuum deposition, and can be thickness enhanced by electroplating.
    Type: Grant
    Filed: October 23, 1984
    Date of Patent: March 24, 1987
    Assignee: New West Technology Corporation
    Inventors: John E. Schumacher, III, Gene A. Fisher
  • Patent number: 4641112
    Abstract: In a lumped constant type delay line device, conductive plates provided with connecting portions and terminals are insert-molded with respect to a plastic base plate in such a manner that the connecting portions are exposed at one surface of the base plate and the terminals extend externally of the base plate. The delay line device further includes capacitors connected to the connecting portions of the conductive plates; and coils having taps connected to electrodes provided on cores and connected to the terminals of the conductive plates, the coils being mounted on the other surface of the base plate.
    Type: Grant
    Filed: March 4, 1986
    Date of Patent: February 3, 1987
    Assignee: Toko, Inc.
    Inventor: Masami Kohayakawa
  • Patent number: 4631100
    Abstract: The present invention contemplates fabrication of a printed circuit board blank having a predetermined pattern of pads and interconnecting conductive pathways, preferably (but not necessarily) flush with the face of the insulating substrate. To fabricate a finished circuit board of any desired circuit configuration, the printed circuit board blank is coated with a photoresist and exposed so that upon development of the photoresist and etching in accordance with the developed pattern, the interconnecting conductive pathways between pads will be selectively etched away so that only those interconnects for the desired circuit pattern remain.
    Type: Grant
    Filed: November 15, 1984
    Date of Patent: December 23, 1986
    Inventor: Peter P. Pellegrino
  • Patent number: 4606787
    Abstract: Methods and apparatus for providing fine line, high density multiple layer printed circuit board packages are disclosed. In the method for fabricating multiple layer printed circuit board package, a printed circuit board is formed having a conductive circuit pattern embedded in and integral with an insulator material substrate, such that the surface of the conductive circuit pattern is exposed along one surface of the substrate, and lays flush and coplanar with therewith. At least two of said boards are stacked with a layer of insulator material interposed between each pair of adjacent boards. The entire assembly is heat-pressed together to form a homogenous block of insulator material having conductive circuit patterns embedded and integrally molded therein.
    Type: Grant
    Filed: January 13, 1984
    Date of Patent: August 19, 1986
    Assignee: ETD Technology, Inc.
    Inventor: Peter P. Pelligrino
  • Patent number: 4598472
    Abstract: A hemispherically shaped membrane switch assembly for attaching to generally hemispherical surfaces such as cathode ray tubes is disclosed. Also disclosed are a method and apparatus for forming the assembly. The assembly is comprised of two layers of transparent film having spaced-apart conductors on the internal surfaces of both layers. The internal surfaces are separated by spacing means, the spacing means being discontinuous at the switch sites. The conductors on the two layers cross and are spaced apart at the switch sites. The assembly is hemispherically formed to the same radius as the hemispherical surface on which the assembly is to be mounted. The assembly mounts flush to the hemispherical surface and conforms uniformly to its surface thus reducing distortion and parallax.
    Type: Grant
    Filed: August 19, 1983
    Date of Patent: July 8, 1986
    Assignee: AMP Incorporated
    Inventors: James R. Schlunz, Donald G. Stillie
  • Patent number: 4591220
    Abstract: A multi-layer circuit board comprised of two or more circuit board substrates shaped by injection molding with mating interconnecting pins and holes and banded together with an electrically insulating adhesive material. Circuit leads are provided on both sides of each substrate recessed into channels formed in the surface of the substrate during the molding process. Electrical interconnection of the layers of circuitry occurs where the conductive materials of the circuit leads passes down through component lead holes axially located in the interconnecting pins and around the exterior of the interconnecting pins where contact is made with the conductive material coating on the interior of the interconnecting holes.
    Type: Grant
    Filed: August 28, 1985
    Date of Patent: May 27, 1986
    Assignees: Rollin Mettler, John Mettler, John Impey
    Inventor: John Impey
  • Patent number: 4584767
    Abstract: A molding process and resulting product is disclosed in which a printed circuit pattern carrier is placed in a mold and is molded to an insulation carrier. The insulation carrier is disclosed as a printed circuit board or the interior of the insulation housing for an electrical product. Plural laminations molded atop one another are disclosed. The printed circuit carrier has mold gate openings to enable molding of features which extend above the plane of the conductive layer. A printed circuit pattern is applied before the molding step.
    Type: Grant
    Filed: July 16, 1984
    Date of Patent: April 29, 1986
    Inventor: Vernon C. Gregory
  • Patent number: 4548451
    Abstract: A pinless connector interposer for making densely populated, inexpensive, simple, reliable, self-wiping connections between components used in semiconductor packaging such as semiconductor carrying substrates, flexible and rigid printed circuit boards and cards. The connector interposer comprises an elastomeric base member in which deformable protrusions are formed on both the top and bottom surface of the base member, wherein the protrusions correspond to contact pads of semiconductor packaging components. An electrically conductive metal coated flexible overlay is bonded to the base member, forming electrically conductive tab elements, enabling a multitude of connections to be made to a semiconductor package. The connections can be accommodated on centers as low as 0.025 inches, despite the non-planarity that may exist between the packaging components of a system.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: October 22, 1985
    Assignee: International Business Machines Corporation
    Inventors: Garry M. Benarr, Terry A. Burns, William J. Walker
  • Patent number: 4546065
    Abstract: A process for forming a pattern of conductive lines on the top of a multi-layer ceramic substrate comprising:providing a green ceramic substrate, embossing a pattern of grooves in the top surface of the green ceramic substrate,sintering the green ceramic substrate to thereby form a multi-layer ceramic substrate anddepositing a conductive material in at least a portion of said embossed pattern of grooves.
    Type: Grant
    Filed: August 8, 1983
    Date of Patent: October 8, 1985
    Assignee: International Business Machines Corporation
    Inventors: Albert Amendola, Arnold F. Schmeckenbecher, Joseph T. Sobon
  • Patent number: 4540151
    Abstract: A single piece electrode comb or device includes two circuit boards having conductor paths and two separate rows of needle-like recording electrodes which are electrically connected to separate paths of the respective circuit board encapsulated in a single plastic resin body with the electrode rows extending to a recording edge formed in a rib along one edge of the body. To form the electrode comb, a device having two substantially similar rectangular cross-sectional shaped halves is assembled in one position to form a winding core on which a wire is wound with a plurality of turns, clamped and joined to the respective circuit boards which are mounted on faces of the two halves, subsequently the wires are separated along a parting plane and the two halves are disassembled with one being rotated 180.degree.
    Type: Grant
    Filed: April 25, 1983
    Date of Patent: September 10, 1985
    Assignee: Dr. -Ing. Rudolf Hell GmbH
    Inventors: Martin Pointner, Rudiger Sommer
  • Patent number: 4532152
    Abstract: A plastic substrate is injection molded to provide a pattern of channels in at least one of its sides to define a predetermined set of conductive paths. Both the surfaces of the channels and the non-channel surfaces therebetween are metalling through one or more steps of flame spraying, a combination of electroless plating and electroplating, gas plating or vacuum deposition. In one form of the invention the metallization over the non-channel surfaces is removed by abrading. In another form of the invention the initial metallization over the non-channel surfaces is coated with a resist prior to the deposition of another metal layer. The metal covering the channels is subsequently removed by stripping the resist and etching away the initial metallization.
    Type: Grant
    Filed: July 11, 1983
    Date of Patent: July 30, 1985
    Inventor: Vito D. Elarde
  • Patent number: 4402135
    Abstract: A circuit board is fabricated by injection molding a support of an insulating material. The support is provided with channels in the pattern of conductive paths. The channels are filled by injection with electrically conductive plastic, and electrically conductive metal is precipitated galvanoplastically on the plastic.
    Type: Grant
    Filed: April 3, 1981
    Date of Patent: September 6, 1983
    Assignee: Braun Aktiengesellschaft
    Inventors: Otto Schweingruber, Werner Hafner
  • Patent number: 4374457
    Abstract: A substrate and method of manufacture wherein a substrate is molded from particulate material wherein grooves on and through the body are formed during substrate molding and prior to sintering. The substrate includes all buss structure molded therein. Cooling of chips is provided by providing a heat sink in an aperture formed within a substrate and beneath the chips.
    Type: Grant
    Filed: August 4, 1980
    Date of Patent: February 22, 1983
    Inventor: Raymond E. Wiech, Jr.
  • Patent number: 4369557
    Abstract: An insulative substrate web having a conductive surface on a first face is printed and etched to provide a repetitive conductive circuit pattern. In one form of the invention, the pattern defines a first conductive area serving as a first capacitor plate, and an inductor connected thereto; conductive material is applied to the second face of the web to define a second conductive area aligned with the first conductive area and serving as a second plate of the capacitor, and a conductive strip connecting the second conductive area to the other end of the inductor. In another form of the invention, the pattern defines first and second conductive areas connected by an inductor; the web is folded so that the conductive areas are aligned to form respective plates of a capacitor. The web may form the capacitor dielectric, or an insulative layer may be inserted for this purpose; and the web is sealed to fix the capacitance. The web is severed to provide individual planar resonant tags.
    Type: Grant
    Filed: August 6, 1980
    Date of Patent: January 25, 1983
    Inventor: Jan Vandebult
  • Patent number: 4363930
    Abstract: A circuit board is fabricated from a metal layer laminated to an underlying dielectric substrate. A stamping die, or roller, formed with a deeply impressed pattern of circuit paths, is indented through the metal and into the substrate. The metal is formed into circuit path conductors, electrically isolated from one another by insetting sheared away portions of the metal into indented portions of the substrate.
    Type: Grant
    Filed: February 4, 1980
    Date of Patent: December 14, 1982
    Assignee: AMP Incorporated
    Inventor: Norman E. Hoffman
  • Patent number: 4354895
    Abstract: A laminate for a laminated multilayer circuit board incorporates as a constituent member the plating layer from a peel-apart temporary base used in the fabrication of the laminate. The layer, with its one surface superimposed on the base, has additively plated to its opposite surface individual conductors and is subsequently personalized in register with the pattern of the plated conductor circuitry. The personalized layer and the plated conductors are embedded in a dielectric layer, the superimposed surface being flush mounted in the dielectric layer. The base has a rough-like surface profile characteristic that imparts at least a conformal surface profile characteristic in the superimposed surface of the plating layer which in turn provides improved adherence of this superimposed flush mounted surface, when subsequently exposed by the removal of the peel-apart base, to another dielectric layer thereafter laminated to the embedding dielectric layer to inhibit delamination between the two dielectric layers.
    Type: Grant
    Filed: November 27, 1981
    Date of Patent: October 19, 1982
    Assignee: International Business Machines Corporation
    Inventor: Theron L. Ellis
  • Patent number: 4329780
    Abstract: A wear-resistant reinforced liner for a center plate structure of a railway vehicle and method of making same are provided wherein the liner is defined of a polymeric material and has a top surface adapted to engage a railway body center plate and a bottom surface adapted to engage a railway truck center plate with dual-purpose means embedded in the polymeric material which serves as a matrix therefor with the dual-purpose means having a top surface portion which comprises a top surface of the liner and a bottom surface portion which comprises a bottom surface of such liner; and, the dual-purpose means provides reinforcement for the liner and a comparatively low electrical resistance path through the liner with each surface portion in contact with an associated center plate.
    Type: Grant
    Filed: June 30, 1980
    Date of Patent: May 18, 1982
    Assignee: Dayco Corporation
    Inventor: M. John Somers
  • Patent number: 4323421
    Abstract: Conductor-clad composites are advantageously fabricated using molding compounds and associated processing techniques. The conductive cladding is applied and bonded to the composite during the molding process. The conductor-clad composite may be used as printed wiring board, and in this embodiment results in improved physical, chemical, mechanical, and electrical properties.
    Type: Grant
    Filed: February 15, 1980
    Date of Patent: April 6, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Theodore H. Klein
  • Patent number: 4306925
    Abstract: A printed circuit which may be highly flexible in configuration and design includes at least one uniformly thick, planar circuit layer including a conductive circuit pattern and an insulating circuit pattern of a cured, flowable insulating material. The printed circuit may include multiple circuit layers that are selectively electrically connected to other layers and may provide circuit patterns, mechanically supportive insulator patterns and windows in almost any desired configuration. The printed circuit may be bonded to a substrate in a high thermal transfer configuration, implemented as a film carrier having plated conductors extending from the surface to receive directly pads of integrated circuit chips or used as a high strength, low coefficient of thermal expansion flexible cable.
    Type: Grant
    Filed: September 16, 1980
    Date of Patent: December 22, 1981
    Assignee: Pactel Corporation
    Inventors: Sanford Lebow, Daniel Nogavich
  • Patent number: 4301580
    Abstract: A method for fabricating electrical component assemblies includes the steps: (a) providing a first electrode and a first electrical component and locating the electrode in a recess formed by the component to produce a first laminate subassembly, (b) providing a second electrode and a second electrical component and locating the electrode in a recess formed by the second component to produce a second laminate sub-assembly, and (c) locating said two sub-assemblies in mutually stacked relation, thereby to form a resultant assembly. The components are typically provided by deposition on the electrodes and to protrude edgewise thereof beyond selected edges of the electrodes, thereby to form electrical contacts, and said locating of the sub-assemblies is carried out to cause said contacts to protrude in at least two different directions from the resultant assembly. The component typically consist of dielectric material, and the electrodes are typically deposited in the form of electrically conductive ink.
    Type: Grant
    Filed: June 15, 1979
    Date of Patent: November 24, 1981
    Inventor: Clarence L. Wallace
  • Patent number: 4236777
    Abstract: An integrated circuit package for establishing electrical contact with the terminal areas or pads of an integrated circuit chip comprises an insulating substrate having a flat surface in which there are embedded a plurality of electrodeposited conductors. The conductors have inner ends in a chip-receiving zone of the flat surface and have outer end portions which are remote from the chip-receiving zone. The inner ends of the conductors have contact bumps or promontories extending above the flat surface and located such that when a chip is placed on the promontories, they will be against the terminal areas of the chip. The chip can be held against the promontories by a suitable clamping means and contact established with the conductors at their outer ends by suitable connecting means. The device is particularly useful for testing chips prior to their being placed in service.
    Type: Grant
    Filed: July 27, 1979
    Date of Patent: December 2, 1980
    Assignee: AMP Incorporated
    Inventors: Joseph F. Merlina, John P. Redmond, George Ulbrich, Richard M. Wagner
  • Patent number: 4221047
    Abstract: A method for fabricating an interconnection package for a plurality of semiconductor chips which include the fabrication of a multi-layered glass-ceramic superstructure with a multi-layered distribution of conductors on a preformed multi-layered glass-ceramic base, by the repeatable steps of depositing a conductor pattern on the base and forming thereon a crystallizable glass dielectric layer which is then crystallized to a glass-ceramic prior to further additions of conductor patterns and crystallizable glass layers to form a monolithic compatible substrate all through. Semiconductor chips can be electrically connected to expose conductor patterns at the top surface of the resultant glass-ceramic package.
    Type: Grant
    Filed: March 23, 1979
    Date of Patent: September 9, 1980
    Assignee: International Business Machines Corporation
    Inventors: Bernt Narken, Rao R. Tummala