With Molding Of Insulated Base Patents (Class 29/848)
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Publication number: 20040158979Abstract: A method of manufacturing a semiconductor mounting board includes providing a base member and linear conductive members formed of metallic wires. The conductive members are constructed so that they extend linearly between a semiconductor element-mounting face and a circuit board-mounting face of a base member, and are integrally molded within the base member. For this purpose, a resin material for forming the base member is injected into a mold wherein the conductive members are linearly arranged beforehand.Type: ApplicationFiled: February 20, 2004Publication date: August 19, 2004Inventors: Takaaki Higashida, Koichi Kumagai, Takahiro Matsuo
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Patent number: 6772512Abstract: A method of fabricating a FCBGA (Flip-Chip Ball-Grid-Array) package without causing mold flash is proposed, which is characterized by the forming of a dummy pad over the back surface of the substrate to allow the portion of the solder mask formed over a vent hole in the substrate to be substantially raised to an elevated flat surface where a groove is then formed to surround the exit of the vent hole. During a molding process, when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the groove in the elevated flat surface over the dummy pad, thereby preventing it from flashing to nearby solder-ball pads.Type: GrantFiled: January 13, 2001Date of Patent: August 10, 2004Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Chou Tsai, Jen-Yi Tsai
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Publication number: 20040143958Abstract: Methods for forming data storage media and the media formed thereby are disclosed herein. In one embodiment, the method for forming a data storage media, comprises: injection molding a substrate comprising surface features, wherein said surface features have greater than about 90% of a surface feature replication of an original master; and disposing a data layer over at least one surface of said substrate; wherein said data storage media has an axial displacement peak of less than about 500&mgr; under shock or vibration excitation.Type: ApplicationFiled: January 14, 2004Publication date: July 29, 2004Inventors: Thomas P. Feist, Wit C. Bushko, Herbert S. Cole, John E. Davis, Thomas B. Gorczyca, Joseph T. Woods
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Publication number: 20040113221Abstract: An injection molded image sensor includes metal sheets arranged in a matrix, an injection molded structure, a photosensitive chip, bonding pads, wires, and a transparent layer. Each metal sheet has a first board, a second board, a third board, and a fourth board. The injection molded structure encapsulates the metal sheets by way of injection molding and has a first molded body and a second molded body. The injection molded structure has a U-shaped structure and is formed with a cavity. The photosensitive chip is mounted within the cavity. The bonding pads are formed on the photosensitive chip. The wires electrically connect the bonding pads to signal input terminals of the first boards. The transparent layer covers over the first molded body to encapsulate the photosensitive chip.Type: ApplicationFiled: December 16, 2002Publication date: June 17, 2004Inventors: Jackson Hsieh, Jichen Wu, Bruce Chen, Worrell Tsai
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Patent number: 6739028Abstract: A high impedance surface and a method of making same. The surface includes a molded structure having a repeating pattern of holes therein and a repeating pattern of sidewall surfaces, the holes penetrating the structure between first and second major surfaces thereof and the sidewall surfaces joining the first major surface. A metal layer is put on said molded structure, the metal layer being in the holes, covering at least a portion of the second major surface, covering the sidewalls and portions of the first major surface to interconnect the sidewalls with other sidewalls via the metal layer on the second major surface and in the holes.Type: GrantFiled: July 13, 2001Date of Patent: May 25, 2004Assignee: HRL Laboratories, LLCInventors: Daniel F. Sievenpiper, Joseph L. Pikulski, James H. Schaffner, Tsung-Yuan Hsu
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Patent number: 6739047Abstract: A package for an electronic component includes a metal support substrate having a pattern of openings therethrough and a body of an insulating material, such as glass or ceramic, on and bonded to the surface of the support substrate. The body is formed from a plurality of layers of an insulating material, and conductive vias extending through the plurality of layers to the support substrate; said insulating body having an opening therein, an electronic component directly mounted in said opening to the patterned base plate. The base plate can be cut into one or more modules and directly soldered to a motherboard having additional devices mounted thereon.Type: GrantFiled: October 30, 2002Date of Patent: May 25, 2004Assignee: Lamina Ceramics, Inc.Inventors: Mark Stuart Hammond, Ellen Schwartz Tormey, Barry Jay Thaler, Leszek Hozer, Hung-tse Daniel Chen, Bernard Dov Geller, Gerard Frederickson
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Patent number: 6735858Abstract: A method of manufacturing an electronic apparatus having a plastic housing. The method includes blow molding with a one-piece plastic housing around an electronic circuit board populated with components. The circuit board is fastened and held in-situ during the blow molding. Fastening locations are defined by contiguously sandwiched portions of the housing and the electronic circuit board.Type: GrantFiled: March 15, 2000Date of Patent: May 18, 2004Assignee: Siemens AktiengesellschaftInventor: Harald Schmidt
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Publication number: 20040078969Abstract: A method of manufacturing a circuit board by forming a circuit pattern in a short process and capable of performing pattern transfer with stability. The manufacturing method includes a step of superposing on a carrier a resist layer in which a circuit pattern is formed and which is formed of a conductor or an insulator, a step of filling the circuit pattern with an electroconductive material, a step of removing the resist layer from the carrier, and a step of transferring the electroconductive material filled in the circuit pattern into an electrical insulating material.Type: ApplicationFiled: August 4, 2003Publication date: April 29, 2004Inventors: Hideo Kanzawa, Satoru Yuuhaku, Yoshitake Hayashi
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Publication number: 20040055153Abstract: In the method for producing a molding with an integrated conductor run, a conductor run is produced on a mount component in particular with the aid of gas flame spraying or cold gas spraying. For this purpose, the surface of the mount component is selectively treated in a corresponding manner to a profile that is provided for the conductor run, such that the surface has areas of different adhesion. A germination layer is applied to the profile that is provided for the conductor run, and the actual conductor run is then in turn applied to the germination layer. This makes it possible to produce a molding with an integrated conductor run pattern in a highly flexible and cost-effective manner. Specific customer wishes can be implemented at short notice and without any problems by a change to the conductor run layout, particularly in the field of motor vehicles.Type: ApplicationFiled: August 25, 2003Publication date: March 25, 2004Inventors: Franz Zahradnik, Uli Hartmann, Knuth Gotz, Gerhard Reichinger
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Patent number: 6701614Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.Type: GrantFiled: February 15, 2002Date of Patent: March 9, 2004Assignee: Advanced Semiconductor Engineering Inc.Inventors: Yi-Chuan Ding, In-De Ou, Kun-Ching Chen
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Patent number: 6694613Abstract: A method for producing a printed-circuit board includes forming via holes that penetrate through a prepreg to whose surface a parting film is applied; filling the via holes with a conducting paste; compressing the prepreg under heat to cure the prepreg and the paste; and then peeling off the parting film. Thus, projection electrodes with a height corresponding to the thickness of the film are formed in a manner such that the projection electrodes are integrated with the via hole conductors.Type: GrantFiled: June 5, 2001Date of Patent: February 24, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Minehiro Itagaki, Hiroaki Takezawa, Yoshihiro Bessho, Tsukasa Shiraishi
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Patent number: 6678952Abstract: A microelectronic element is formed from a structure including metal layers on top and bottom sides of a dielectric. Apertures are formed in the top metal layer, and vias are formed in the dielectric in alignment with the apertures. Top and bottom conductive features are formed in proximity to the vias, as by selectively depositing a metal on the metal layers or selectively etching the metal layers. The top and bottom conductive features are connected to one another by depositing a conductive material into the vias, most preferably without seeding the vias as, for example, by depositing solder in the vias.Type: GrantFiled: July 27, 2001Date of Patent: January 20, 2004Assignee: Tessera, Inc.Inventor: Owais Jamil
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Patent number: 6671950Abstract: A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included.Type: GrantFiled: July 9, 2001Date of Patent: January 6, 2004Assignee: PPG Industries Ohio, Inc.Inventors: Lance C. Sturni, Kevin C. Olson
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Patent number: 6671949Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.Type: GrantFiled: March 13, 2001Date of Patent: January 6, 2004Assignee: Matsushita Electric Works, Ltd.Inventors: Hirokazu Yoshioka, Norio Yoshida, Kenichiro Tanaka
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Patent number: 6668450Abstract: The invention relates to a method for the production of an MID device. Proceeding from a conductor track sheet, which comprises a support sheet as well as conductor tracks arranged thereon, a plastic body is injection-molded onto this conductor track sheet. The conductor tracks have a surface having numerous microscopically small projections and depressions and are designed so as to thereby produce a positively locking connection between the conductor tracks and the plastic body.Type: GrantFiled: June 28, 1999Date of Patent: December 30, 2003Assignee: Thomson Licensing S.A.Inventors: Hans-Otto Haller, Volker Strubel, Gunter Beitinger
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Patent number: 6658734Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outsideType: GrantFiled: November 16, 2001Date of Patent: December 9, 2003Assignee: Dai Nippon Insatsu Kabushiki KaishaInventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi
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Patent number: 6661328Abstract: The present invention provides a composite magnetic body containing metallic magnetic powder and thermosetting resin and having a packing ratio of the metallic magnetic powder of 65 vol % to 90 vol % and an electrical resistivity of at least 104 &OHgr;·cm. When a coil is embedded in this composite magnetic body, a miniature magnetic element can be obtained that has a high inductance value and is excellent in DC bias characteristics.Type: GrantFiled: July 17, 2002Date of Patent: December 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Osamu Inoue, Junichi Kato, Nobuya Matsutani, Hiroshi Fujii, Takeshi Takahashi
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Patent number: 6643924Abstract: A distributed constant filter capable of being connected to a wiring pattern and the like while simultaneously achieving miniaturization, stable performance and assurance of the reliability and a manufacturing method of the distributed constant filter are provided. In a triplate structure band-pass filter, in place of a high impedance pattern which is, in the prior art, formed on the same face as that of a low impedance pattern in an inner layer, conductor patterns extending in the thickness direction of a stacked substrate are formed. Each of the conductor patterns functions as a via pattern connecting the low impedance pattern in the inner layer and a wiring pattern in the surface layer and also functions as a high impedance line. As long as the filtering characteristic is the same, the line overall length (distance in a plane) of the conductor patterns can be made shorter than the conventional line overall length and the area occupied by the conductor patterns can be reduced.Type: GrantFiled: July 11, 2001Date of Patent: November 11, 2003Assignee: Sony CorporationInventor: Takayuki Hirabayashi
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Patent number: 6631551Abstract: A process for forming stable integrated resistors (14) and capacitors (28) on organic substrates (12). The resistors (14) and capacitors (28) are capable of a wide range of resistance and capacitance values, yet can be processed in a manner that does not detrimentally effect the organic substrate (12) or entail complicated processing. The method generally entails the use of thick-film materials usually of the types used to form resistors and capacitors on ceramic substrates. The thick-film materials are applied to an electrically-conductive foil (20) and then heated to bond the thick-film material to the foil (20) and form a solid resistive or capacitive mass (16/30). The foil (20) is then laminated to an organic substrate (12), such that the resistive/capacitive mass (16/30) is attached to and preferably embedded in the organic substrate (12).Type: GrantFiled: June 26, 1998Date of Patent: October 14, 2003Assignee: Delphi Technologies, Inc.Inventors: Philip Harbaugh Bowles, Washington Morris Mobley, Richard Dixon Parker, Marion Edmond Ellis
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Publication number: 20030188429Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.Type: ApplicationFiled: May 8, 2003Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Takayuki Haze, Tsuneo Yabuuchi
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Patent number: 6625883Abstract: Disclosed is a bump structure, which has a hollow body, for electrically connecting a first member and a second member. Also disclosed is a method for making a bump structure, which has the steps of: preparing a molding plate with a concave mold to mold a bump-forming member; forming a conductive thin film so as to form a predetermined cavity in the concave mold of the molding plate; preparing a substrate to which the conductive thin film is to be transferred; and transferring the conductive thin film formed on the molding plate to the substrate.Type: GrantFiled: April 19, 2001Date of Patent: September 30, 2003Assignee: NEC CorporationInventors: Koji Soejima, Naoji Senba
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Publication number: 20030172526Abstract: The present invention provides a production method of a printed circuit board having a circuit pattern with a little variation in the thickness at a low cost without a special step for removal of a dummy pattern. The present invention is characterized in that an insulating layer 2 is formed in a given pattern on one surface of a supporting substrate 1, a circuit pattern 6 is formed on the insulating layer 2 while forming a dummy pattern 7 in an area free of the insulating layer 2 on the one surface of the supporting substrate 1, and an unnecessary part of the supporting substrate 1, which is free of the insulating layer 2 and the circuit pattern 6, is removed by dissolution together with the dummy pattern 7.Type: ApplicationFiled: March 10, 2003Publication date: September 18, 2003Applicant: Nitto Denko CorporationInventors: Makoto Komatsubara, Yasuhito Ohwaki, Takeshi Yoshimi, Shigenori Morita
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Patent number: 6604281Abstract: A packaging process of a circuit board involves a first step in which the circuit board is provided with a predetermined number of pins and is then arranged in the lower mold of a first molding tool. The upper mold of the first molding tool is joined with the lower mold before the resin is injected. The mold is then opened to remove therefrom a semifinished product, which is provided with a metal passivation layer and is subsequently placed in a second molding tool to carry out a second packaging operation. The second molding tool is opened to remove therefrom a finished product.Type: GrantFiled: July 11, 2001Date of Patent: August 12, 2003Assignee: Power Mate Technology Co., Ltd.Inventor: Dennis Shiau
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Patent number: 6601294Abstract: A semiconductor package with thermally enhanced properties is described. The semiconductor package includes a substrate upon which a die is affixed. The die and the substrate each have contacts which are respectively connected with each other. A heat sink is affixed to a surface of the die by way of a thermally compliant material. The compliant material reduces the stresses caused by temperature fluctuations which cause the heat sink and the die to expand and contract at different rates. A first molding material is deposited around the periphery of the die, compliant material and heat sink, thereby leaving exposed substantially an entire surface of the heat sink.Type: GrantFiled: September 29, 2000Date of Patent: August 5, 2003Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Mark S. Johnson
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Multi-shot injection molding process for making electrical connectors and three-dimensional circuits
Patent number: 6601296Abstract: A method of making an article, such as an electrical connector includes an injection-molded plastic substrate and a pattern of injection-molded metal conductors supported on and mechanically interlocked with the substrate, wherein one of the substrate and the conductors is over-molded onto the other of the substrate and the conductors.Type: GrantFiled: July 6, 1999Date of Patent: August 5, 2003Assignee: Visteon Global Technologies, Inc.Inventors: Daniel Phillip Dailey, Mohan R. Paruchuri, Prathap Amerwai Reddy -
Patent number: 6588099Abstract: A molded circuit board is formed by a process comprising the steps of: molding liquid crystal polymer of plating grade into a primary molded member which outline corresponds to the dimensions of the molded circuit board; roughening the surface of the primary molded member; molding a secondary molded member by coating the primary molded member with oxyalkylene-containing poly(vinyl alcohol) resin over the surface thereof except for a portion thereof on which a circuit is to be formed; heating the first and secondary molded members; applying catalyst to the portion of the surface of the primary molded member not covered by the secondary molded member; heating the first and secondary molded members in hot water to elute the secondary molded member; and chemically plating the catalyst-applied-portion to form the circuit thereon, by which the size of the molded circuit board is minimized with simple procedures and production cost reduced.Type: GrantFiled: January 22, 2001Date of Patent: July 8, 2003Assignee: Sankyo Kasei Kabushiki KaishaInventor: Tetsuo Yumoto
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Patent number: 6585024Abstract: A positioning target for a printed circuit board made of base layers and by at least two pressing processes has a first width, a second width formed in the first width, a left margin and a right margin formed on opposite sides of the second width and immediately adjacent to the second width, a first length, a second length formed in the first length, a top margin and a bottom margin. An area formed by a mix of the second width and the second length is for the laminated printed circuit board and multiple positioning holes are respectively defined in two adjacent margins horizontally respective to end sides of two adjacent margins.Type: GrantFiled: January 16, 2002Date of Patent: July 1, 2003Assignee: Compeq Manufacturing Company LimitedInventor: Hsien-Yu Chiu
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Publication number: 20030115749Abstract: A method for heat-treating a plurality of microelectronic structures attached to a non-metallic substrate is disclosed. Each of the plurality of microelectronic structures is comprised of a metallic material, and ones of the plurality of metallic microelectronic structures are insulated from other ones of the plurality of microelectronic structures. An application of the method is for heat-treatment of resilient microstructures.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Applicant: FormFactor, Inc.Inventor: Jimmy Kuo Chen
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Publication number: 20030106212Abstract: An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.Type: ApplicationFiled: January 17, 2003Publication date: June 12, 2003Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shin-Hua Chao, Shyh-Ing Wu, Kuan-Neng Liao, Gin-Nan Yeh
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Patent number: 6568073Abstract: The present invention provides a process for the fabrication of a wiring board, which comprises the following steps: (a) forming a first wiring pattern on a first side of a self-supporting carrier metal foil so as to obtain a self-supporting wiring sheet comprising the carrier metal foil and the first wiring pattern; (b) superposing and pressing the first side of said self-supporting wiring sheet on and against an insulating substrate so that the first wiring pattern is_embedded in the insulating substrate and constitutes a surface with the insulating substrate; and (c) etching off desired portions of said carrier metal foil to form a second wiring pattern made of said carrier metal foil remaining on the surface constituted by the insulating substrate and the first wiring pattern. The present invention also provides the wiring board for electrical tests so fabricated.Type: GrantFiled: March 6, 1998Date of Patent: May 27, 2003Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Hidehiro Nakamura, Hajime Nakayama, Yoshiaki Tsubomatsu, Masanori Nakamura, Kouichi Kaitou, Atsushi Kuwano, Itsuo Watanabe, Masahiko Itabashi
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Patent number: 6557225Abstract: A method of producing a surface acoustic wave device by use of a flip chip process, includes the steps of forming on a piezoelectric substrate at least one interdigital transducer and a plurality of electrode pads electrically connected to the interdigital transducer, forming bumps on the respective electrode pads, and providing an insulating film at a region other than a region where the bumps are formed.Type: GrantFiled: April 12, 2001Date of Patent: May 6, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Toshiaki Takata, Shuji Yamato, Norihiko Takada
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Patent number: 6553662Abstract: A high-density circuit has a plurality of conductors formed in grooves in a ceramic substrate, the conductors having a height less than that of the walls of the grooves. The substrate is embossed with a pattern of grooves corresponding to the grooves in an electroform made from a master tool. The same master tool is used to form a stencil which mates with the grooved substrate. A cermet paste is pushed through the stencil, so as to fill the bottom region of the grooves, and the stencil is then removed, leaving only the paste at the bottom of the grooves. The substrate is then fired, causing the substrate to harden, and causing the cermet to become conductive and to become firmly bonded to the substrate. Because the stencil and the substrate are made from the same, or replications of the same, master tool, the cermet paste can be laid down with great precision, thus enhancing the quality of the product, and reducing the cost of its manufacture.Type: GrantFiled: July 3, 2001Date of Patent: April 29, 2003Assignee: Max Levy Autograph, Inc.Inventor: Donald C. Sedberry
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Patent number: 6546622Abstract: A printed-wiring substrate 1 includes internal dielectric resin layers 12 and 14. A main-surface-side external dielectric resin layer 13 is formed on the internal dielectric resin layer 12 such that the surface thereof serves as a substrate main-surface 1A. A back-surface-side external dielectric resin layer 15 is formed on the internal dielectric resin layer 14 such that the surface thereof serves as a substrate back-surface 1B. A surface 12A of the main-surface-side internal dielectric resin layer 12 and a surface 14A of the back-surface-side internal dielectric resin layer 14 are roughened. The substrate main-surface 1A and the substrate back-surface 1B are roughened such that surface roughness thereof is lower than that of the surfaces 12A and 14A.Type: GrantFiled: March 16, 2001Date of Patent: April 15, 2003Assignee: NGK Spark Plug Co., Ltd.Inventors: Masahiro Iba, Hisashi Wakako, Kazuhisa Sato, Haruhiko Murata, Kazuyuki Takahashi, Kenzo Kawaguchi
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Publication number: 20030061705Abstract: A method of making an interactive information package, including an interactive information closure including a radio frequency identification device, contemplates that a microelectronics assembly be provided, and positioned on an associated substrate for positioning adjacent an inside surface of the top wall portion of the closure of the package. In one embodiment, the mounting substrate is provided in the form of a disc-shaped sealing liner for the closure. In an alternate embodiment, the mounting substrate is laminated to an associated sealing liner, with the substrate, and microelectronics assembly positioned thereon, inserted together with the sealing liner into the associated molded closure.Type: ApplicationFiled: August 20, 2002Publication date: April 3, 2003Inventors: Larry Smeyak, Timothy Carr, Mark Powell, John Ziegler
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Publication number: 20030061706Abstract: A method of making an interactive information package, including an interactive information closure including a radio frequency identification device, contemplates that a microelectronics assembly be provided by formation on an inside surface of the top wall portion of the closure of the package. After formation of the assembly, it is contemplated that a sealing liner be positioned within the closure so that the microelectronics assembly is positioned between the top wall portion and the sealing liner.Type: ApplicationFiled: August 20, 2002Publication date: April 3, 2003Inventors: Larry Smeyak, Timothy Carr, Mark Powell, John Ziegler
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Patent number: 6532397Abstract: An object is to reduce damage to the mechanical parts of a moving mechanism unit 5 for moving a retaining mechanism unit 7 and electric power consumption in an apparatus for taking out a molded product. The apparatus comprises a time measuring unit 4 for measuring a return time elapsing between a start of the returning operation of the retaining mechanism unit 7 in a preceding process and the next start of the penetrating operation for taking out a molded product; an arithmetic operation unit 11 for calculating a return moving speed distribution for a process succeeding the preceding process such that the returning operation terminates upon elapse of the return time measured by the time measuring means 4; and a control unit 12 for activating the moving mechanism unit 5 in such a way that the returning operation is carried out according to the return moving speed distribution in the succeeding process.Type: GrantFiled: May 25, 2000Date of Patent: March 11, 2003Assignee: Kabushiki Kaisha Yushin SeikiInventor: Koji Yamamoto
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Publication number: 20030024115Abstract: A circuit board packaging process comprises the steps of: (a) connecting a circuit board with a plurality of pins by soldering; (b) attaching a metal housing to the cavity of the lower mold of a molding tool, the lower mold cavity has a resin feeding port; the metal housing has a through hole corresponding in location to the resin feeding port; (c) attaching a metal piece to the upper mold of the molding tool; the metal piece has a plurality of through holes for receiving therethrough the pins; the upper mold cavity has a plurality of insertion holes corresponding in location to the through holes; the circuit board is retained under the metal piece such that the pins are inserted into the insertion holes via the through holes; (d) closing the upper and the lower molds to enable the circuit board to be located between the metal piece and the metal housing; (e) injecting resin toward the through hole from the resin feeding port; (f) upon completion of the cooling of the molding tool, removing a finished productType: ApplicationFiled: August 16, 2001Publication date: February 6, 2003Applicant: Power Mate Technology Co., Ltd.Inventor: Dennis Shiau
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Publication number: 20030024110Abstract: A method for manufacturing wired circuit board that enables a wired circuit board of high quality to be manufactured without changing in dimension of the wired circuit board substantially. In this method, the wired circuit board is wound in layers in the winding process in such a manner that after an uncured thermosetting resin layer is formed on the wired circuit board in the resin layer forming process, a right-side spacer and a left-side spacer are disposed on the already wound wired circuit board at both widthwise ends thereof and also an upper spacer is disposed on the right-side spacer and the left-side spacer so as to cover a widthwise area of the wired circuit board, so that the right-side spacer, the left-side spacer and the upper spacer are positioned between the layers of the wired circuit board when wound. Thereafter, the wired circuit board wound in the rolled state is heated as it is, to cure the uncured thermosetting resin layer in the curing process.Type: ApplicationFiled: July 19, 2002Publication date: February 6, 2003Inventors: Hirofumi Fujii, Shunichi Hayashi
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Publication number: 20030009877Abstract: A packaging process of a circuit board involves a first step in which the circuit board is provided with a predetermined number of pins and is then arranged in the lower mold of a first molding tool. The upper mold of the first molding tool is joined with the lower mold before the resin is injected. The mold is then opened to remove therefrom a semifinished product, which is provided with a metal passivation layer and is subsequently placed in a second molding tool to carry out a second packaging operation. The second molding tool is opened to remove therefrom a finished product.Type: ApplicationFiled: July 11, 2001Publication date: January 16, 2003Inventor: Dennis Shiau
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Patent number: 6499217Abstract: An efficient method of manufacturing a three-dimensional printed wiring board is provided in which a conductor foil can be reliably heat-fused to the board at a relatively low temperature and the three-dimensional shape such as convex and concave of a mold can be reproduced precisely with no residual stress. The method comprises the steps of providing a filmy insulator comprising a thermoplastic resin composition containing 65-35 wt % of a polyaryl ketone resin having a crystal-melting peak temperature of 260° C. or over, and 35-65 wt % of an amorphous polyetherimide resin, and having a glass transition temperature as measured when the temperature is increased for differential scanning calorie measurement of 150-230° C.Type: GrantFiled: February 6, 2001Date of Patent: December 31, 2002Assignees: Mitsubishi Plastics Inc., Denso CorporationInventors: Shingetsu Yamada, Jun Takagi, Koichiro Taniguchi, Kaoru Nomoto, Toshihiro Miyake, Kazuya Sanada, Makoto Totani
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Patent number: 6489572Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.Type: GrantFiled: January 23, 2001Date of Patent: December 3, 2002Assignee: Kingpak Technology Inc.Inventors: Mon Nan Ho, Chih-Hong Chen, Yen Cheng Huang, Li Huan Chen, Kuo Feng Peng, Jichen Wu, Allis Chen, Wen Chuan Chen
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Patent number: 6490501Abstract: A monitoring and control system for use in curing composite materials includes a model for a workpiece being cured. The model calculates current internal states of the workpiece and predicts, based upon past and current states of the workpiece, future states of the cure process. These future states are represented as virtual inputs to the controller, which controls operation of the cure process based upon both real and virtual inputs. Cure rates are affected by both external temperatures and internal heat generated by the curing process itself. The internally generated heat is considered by the model when calculating current states and predicting future states. By projecting the cure state into the future, problems caused by high cure rates can be avoided. In addition, pressure can be optimally controlled in response to estimated internal material state.Type: GrantFiled: October 6, 1999Date of Patent: December 3, 2002Assignee: Bell Helicopter Textron Inc.Inventor: Arven H. Saunders
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Patent number: 6467138Abstract: This invention is provided a method for making a backing layer for an ultrasonic matrix array transducer useful in diagnostic imaging, non-destructive material testing and treatment of human organs. The method includes placing the grid in a mold, filling the mold with an acoustically absorbent material such that the absorbent material fills the spaces between the contacts, curing the material in the mold so as to form a block formed by the cured absorbent material and the grid, and releasing the block from the mold.Type: GrantFiled: May 24, 2000Date of Patent: October 22, 2002Assignee: VermonInventor: Flesch Aimé
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Publication number: 20020148112Abstract: An encapsulation method for a ball grid array (BGA) semiconductor package, includes: adhering one sided adhesive tape to an upper portion of the semiconductor package after performing a wire bonding; carrying out a molding by using a mold having a groove of a certain size inside; and removing the one side adhesive tape after completing the molding, whereby a flash is prevented from occurring during the BGA encapsulation process.Type: ApplicationFiled: June 17, 2002Publication date: October 17, 2002Applicant: LG Semicon Co., Ltd.Inventors: Seong-Jae Heo, Chi-Jung Song
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Publication number: 20020144397Abstract: A process for the fabrication of cylindrical circuit boards. The process is easily manufacturable since rotation of the cylindrical printed circuit board about its longitudinal axis enables automatic application of dielectric and metal layers and also allows controllable curing and etching processes. Metal layers may be constructed as planar layers or as stripline layers and both may be used in combination within a single cylindrical circuit board.Type: ApplicationFiled: January 21, 2000Publication date: October 10, 2002Inventor: Terrel L. Morris
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Patent number: 6460247Abstract: A wiring board construction includes at least one microvia disposed in a base substrate and includes a deep imprinted cup shaped in the top surface thereof. A conductor material is disposed within the recess, and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion helps to complete an electrically conductor path through the substrate to help complete an electrically conductive path through the substrate.Type: GrantFiled: December 21, 1999Date of Patent: October 8, 2002Assignee: Dimensional Circuits Corp.Inventor: George D. Gregoire
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Publication number: 20020138978Abstract: A molded circuit board is formed by a process comprising the steps of: molding liquid crystal polymer of plating grade into a primary product that has an outline corresponding to the dimensions of said molded circuit board; roughening the surface of said primary product; molding a secondary molded member to produce a secondary product by coating said primary molded member with oxyalkylene-containing poly(vinyl alcohol) resin over almost the entire surface thereof except for a circuit area on which a circuit is to be formed; heating said secondary product; applying catalyst to said circuit area where portions of surface of said primary molded member are not covered with said secondary molded member; heating said secondary product in hot water to elute the secondary molded member into hot water; and chemically plating the catalyst-applied-area to form a circuit thereon. This process minimizes the size of the molded circuit board, simplifies the procedure and thus reduce the production cost.Type: ApplicationFiled: January 22, 2001Publication date: October 3, 2002Applicant: SANKYO KASEI KABUSHIKI KAISHAInventor: Tetsuo Yumoto
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Patent number: 6458472Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.Type: GrantFiled: January 8, 2001Date of Patent: October 1, 2002Assignee: Henkel Loctite CorporationInventors: Mark M. Konarski, J. Paul Krug
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Publication number: 20020084103Abstract: The present invention provides a silicon nitride ceramic substrate composed of a silicon nitride sintered body in which maximum size of pore existing in grain boundary phase of the sintered body is 0.3 &mgr;m or less, and having a thermal conductivity of 50 W/mK or more and a three point bending strength of 500 MPa or more, wherein a leak current is 1000 nA or less when an alternative voltage of 1.5 kV-100 Hz is applied to a portion between front and back surfaces of the silicon nitride sintered body under conditions of a temperature of 25° C. and a relative humidity of 70%. According to the above structure of the present invention, there can be provided a silicon nitride ceramic substrate capable of effectively suppressing a leak current generation when the above substrate is assembled into various power modules and circuit boards, and capable of greatly improving insulating property and operative reliability of power modules in which output power and capacity are greatly increased.Type: ApplicationFiled: October 26, 2001Publication date: July 4, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Michiyasu Komatsu, Haruhiko Yamaguchi, Takayuki Naba, Hideki Yamaguchi
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Patent number: 6401333Abstract: A method and apparatus (10) are used for manufacturing a wire structure wherein a wire (13) is three-dimensionally aligned at prescribed pitches. The method comprises the steps of providing one or more frame bodies (12) which have a prescribed thickness, peripherally of a rotary shaft (11). By rotating rotary shaft (11) about a rotation axis thereof, wires (13) are wound, at prescribed pitches, around frame bodies (12). Another frame body (12) is stacked on at least one existing frame body and wire (13) is wound thereon at prescribed pitches. The above steps are repeated to yield a wire structure having a wire aligned three-dimensionally and accurately at prescribed pitches.Type: GrantFiled: June 8, 2000Date of Patent: June 11, 2002Assignee: NGK Insulators, Ltd.Inventors: Tomio Suzuki, Ritsu Tanaka