Simultaneous Circuit Manufacturing Patents (Class 29/849)
  • Patent number: 9545017
    Abstract: Invention z-axis interconnection structures provide a means to mechanically and electrically interconnect layers of metallization in electronic substrates reliably and in any configuration. Invention z-axis interconnection structures comprise a novel bonding film and conductive paste and one- and two-piece building block structures formed therefrom.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: January 10, 2017
    Assignees: Ormet Circuits, Inc., Integral Technology, Inc.
    Inventors: Christopher A Hunrath, Khang Duy Tran, Catherine A Shearer, Kenneth C Holcomb, G Delbert Friesen
  • Patent number: 9238340
    Abstract: Electrical connection between the backplane and the front electrode of an electro-optic display is provided by forming a front plane laminate (100) comprising, in order, a light-transmissive electrically-conductive layer (104), a layer of electro-optic material (106), and a layer of lamination adhesive (108); forming an aperture (114) through all three layers of the front plane laminate (100); and introducing a flowable, electrically-conductive material (118) into the aperture (114), the flowable, electrically-conductive material being in electrical contact with the light-transmissive electrically-conductive layer (104) and extending through the adhesive layer (108).
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: January 19, 2016
    Assignee: E Ink Corporation
    Inventors: Matthew Joseph Kayal, Stephen Joseph Battista, Richard J. Paolini, Jr., Shyamala A. Subramanian, Jr.
  • Patent number: 9003653
    Abstract: A method for producing a ceramic multilayer circuit system, and a corresponding multilayer circuit system are provided. An embodiment of the method includes sequential deposition of a plurality of circuit layers of the multilayer circuit system on a substrate using a powder spray method; pressing of the deposited plurality of circuit layers; and thermal sintering of the pressed plurality of circuit layers. The individual circuit layers have electrically conductive areas made of at least one conductive material and electrically insulating areas made of at least one ceramic material.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: April 14, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Juergen Egerter, Walter Roethlingshoefer, Markus Werner
  • Publication number: 20150092377
    Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: JASON R. WRIGHT, Michael B. Vincent, Weng F. Yap
  • Publication number: 20150068791
    Abstract: A wiring board includes a substrate, pads formed on an electronic-component mounting surface of the substrate, and a resin insulation layer covering the electronic-component mounting surface and having opening portions such that the opening portions are exposing the pads, respectively. The pads include a non-solder mask defined pad having a wiring portion and a non-solder mask defined pad having no wiring portion, and the opening portions are formed such that the non-solder mask defined pads have exposed conductor areas which have substantially same areas inside the opening portions.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 12, 2015
    Applicant: IBIDEN CO., LTD.
    Inventor: Takenobu NAKAMURA
  • Patent number: 8943682
    Abstract: A method of making a transparent touch-responsive capacitor apparatus includes providing a transparent conductor precursor structure including a transparent substrate, a first precursor material layer formed over the transparent substrate and a second precursor material layer formed on the first precursor material layer; forming a electrically connected first micro-wires in the first and second precursor material layers; forming electrically connected second micro-wires in a precursor material layer electrically connected to the first micro-wires; and wherein the height of at least a portion of the first micro-wires is greater than the height of at least a portion of the second micro-wires, and wherein the total area occupied by the first micro-wires is less than 15% of the first transparent conductor area and the total area occupied by the second micro-wires is less than 15% of the second transparent conductor area.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Eastman Kodak Company
    Inventors: Ronald Steven Cok, Terrence Robert O'Toole
  • Patent number: 8901940
    Abstract: A sensing edge for providing a signal to a controller indicating that a forward edge of a door is obstructed during operation includes an elongated sheath and first and second end plugs. The elongated sheath is mounted to the forward door edge and has a first end, second end and first cavity connecting the ends. First and second spaced apart electrically conductive materials are disposed within the elongated sheath. The first end plug includes an inner end having first engaging structures positioned within the first cavity in an assembled configuration and an outer end having a first depression for housing an electronic component. The electronic component is electrically coupled to the electrically conductive materials. The second end plug includes an inner end having a sensing component and second engaging structures positioned within the first cavity in an assembled configuration. The sensing component is electrically coupled to the electrically conductive materials.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: December 2, 2014
    Assignee: Miller Edge, Inc.
    Inventors: Jack Provenzano, Vinay Sao, Krishnaraj Tejeswi
  • Patent number: 8875390
    Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 ?m. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: November 4, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
  • Patent number: 8850701
    Abstract: A method for manufacturing a multilayer PCB comprises the following steps. First, a PCB substrate includes a first circuit layer is provided. The first circuit layer includes a mounting portion. A first solder-resistant layer is formed on the mounting portion and a protective adhesive film is attached on the first solder-resistant layer. Next, a first copper foil, a first adhesive layer, a second copper foil, and a second adhesive layer are laminated on the PCB substrate, and the first and second copper foils are etched to form circuit layers. Then a cavity is defined and the protective adhesive film is exposed in it. After removing the protective adhesive film, an electronic component is mounted in the cavity. As such, a multilayer PCB with the electronic component embedded in is obtained.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: October 7, 2014
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Xue-Jun Cai
  • Patent number: 8782884
    Abstract: A method for manufacturing an electrode assembly. The method comprises: forming a comb having a plurality of electrode contacts, wherein the surface of at least one of the electrode contacts comprises a plurality of indentations such that the effective surface area per area unit of a center region of the at least one electrode contact is larger than the effective surface area per area unit of the of the region of the surface outside the center region; assembling an array of electrode contacts from the comb; molding a carrier member about the assembled array of electrode contacts, wherein a surface of the at least one electrode contact is covered by a layer of the carrier member material; and removing the layer of carrier member material on the surface of the at least one electrode contact.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: July 22, 2014
    Assignee: Cochlear Limited
    Inventors: Edmond D. Capcelea, Peter Gibson, Fysh Dadd
  • Patent number: 8763237
    Abstract: A method of fabricating a touch panel is provided. A substrate having a touch-sensing region and a peripheral region is provided. A touch-sensing circuit layer including first sensing series, and second meshed metal sensing pads is formed on the touch-sensing region of the substrate. An insulating layer having first contact windows is formed on the substrate to cover the touch-sensing circuit layer. The first contact windows expose a portion of the second meshed metal sensing pads. A plurality of second transparent bridge lines are formed on the insulating layer located in the touch-sensing region. Each second transparent bridge line is electrically connected to two adjacent second meshed metal sensing pads through two first contact windows. The second transparent bridge lines completely cover the portion of the second meshed metal sensing pads exposed by the first contact windows.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: July 1, 2014
    Assignee: Au Optronics Corporation
    Inventors: Yu-Feng Chien, Zeng-De Chen, Tun-Chun Yang, Seok-Lyul Lee
  • Patent number: 8732943
    Abstract: A liner for an appliance is formed by a plastic sheet formed into a three dimensional shape corresponding to at least a portion of a compartment of the appliance.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 27, 2014
    Assignee: Whirlpool Corporation
    Inventors: Martin Shawn Egan, Michael E. Stagg, Jr.
  • Publication number: 20140115889
    Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 ?m. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
  • Publication number: 20140076617
    Abstract: A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.
    Type: Application
    Filed: September 20, 2012
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hua Chen, Chen-Shien Chen
  • Patent number: 8661661
    Abstract: The invention relates to a method for producing at least one circuit part on a substrate (20). Said method comprises the following steps: at least one granulate (54), which contains an electric conductor and which has a predefined geometric distribution, is deposited on the substrate (20) and the granulate (54) is heated and forms a permanent connection with the substrate (20) and forms at least one circuit part on the substrate (20). The invention also relates to a circuit board comprising at least one substrate, on which at least one circuit part is arranged, and to a device for producing at least one circuit part on a substrate (20).
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 4, 2014
    Inventors: Axel Ahnert, Elmar Grandy
  • Patent number: 8567050
    Abstract: A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB device 101 includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. A single-shot molding process is used to form both an upper housing portion on the upper PCB surface that includes ribs extending between adjacent contact pads, and a lower molded housing portion that is formed over passive components and IC dies disposed on the lower PCB surface. The passive components are mounted using SMT methods, and the IC dies are mounted using COB methods. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: October 29, 2013
    Assignee: Super Talent Technology, Corp.
    Inventors: Siew S. Hiew, Abraham C. Ma, Nan Nan
  • Patent number: 8549743
    Abstract: In a method for hot embossing at least one conductor track onto a substrate, a film having at least one electrically conductive layer is pressed against the substrate in a die direction using an embossing die having a structured die surface. The film remains on the substrate after ending the embossing process in at least two structure planes, which are spaced apart in the die direction.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 8, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Ricardo Ehrenpfordt, Johanna May
  • Publication number: 20130235535
    Abstract: A composite substrate includes a ceramic substrate including, on at least one surface, a circuit wire on which an electronic component is to be mounted, a plurality of external connection terminals provided on one surface of the ceramic substrate, and a resin layer provided on the one surface of the ceramic substrate. The external connection terminals have a cross sectional area that decreases with increasing distance from the one surface of the ceramic substrate, and end surfaces of the external connection terminals opposite to end surfaces connected to the ceramic substrate are partially or entirely exposed from the resin layer.
    Type: Application
    Filed: April 25, 2013
    Publication date: September 12, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Kazuhiro ISEBO
  • Patent number: 8528202
    Abstract: A molding pin for a metal die is prevented from breaking, solder is surely deposited, and thus, a circuit pitch can be reduced to the limit. On the front plane of a circuit board, prescribed circuit patterns made of a conductive material are formed, and on the rear plane, prescribed circuit patterns are also formed. On the circuit board, a through hole is formed to carry electricity between the circuit patterns on both planes. The inner shape of the through hole is narrow in a direction between the adjacent circuit patterns and wide in a circuit extending direction.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: September 10, 2013
    Assignee: Sankyo Kasei Co., Ltd.
    Inventor: Tetsuo Yumoto
  • Publication number: 20130185936
    Abstract: A wiring board includes a pad exposed from an opening portion of an outermost insulating layer. The pad includes: a first metal layer a surface of which is exposed from the wiring board; a second metal layer provided on the first metal layer and formed of a material effective in preventing a metal contained in a via inside the board from diffusing into the first metal layer; and a third metal layer provided between the second metal layer and the via, and formed of a material harder to be oxidized than that of the second metal layer. The thickness of the third metal layer is relatively thick, and is preferably selected to be three times or greater than a thickness of the second metal layer. A side surface of the third metal layer and a surface of the third metal layer to which the via is to be connected are roughed.
    Type: Application
    Filed: February 12, 2013
    Publication date: July 25, 2013
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: SHINKO ELECTRIC INDUSTRIES CO., LTD.
  • Publication number: 20130039065
    Abstract: A semiconductor light-emitting element mounting module includes a metal conductor plate including at least one connection surface formed on one side thereof, wherein a semiconductor light-emitting element is connectable to the connection surface; a pair of terminals provided away from the connection surface and which are connectable to the connection surface to be electrically conductive therewith; a surface-insulation portion formed from a resin material, wherein the surface-insulation portion covers the entire surface of the metal conductor plate except for the connection surface. The pair of terminals are connectable with a corresponding pair of terminals that are provided on another semiconductor light-emitting element mounting module.
    Type: Application
    Filed: July 20, 2012
    Publication date: February 14, 2013
    Applicant: KYOCERA CONNECTOR PRODUCTS CORPORATION
    Inventors: YOSHIFUMI OKABE, HIROMITSU KURIMOTO, TORU WAGATSUMA
  • Publication number: 20130025120
    Abstract: A wiring board having high connection reliability is provided. The wiring board comprises: an insulating base material (30); wiring patterns (51-57) formed on one main surface of the insulating base material (30); and vias (11V, 12V) which penetrate from the one main surface side of the insulating base material (30) to the other main surface side and which is conductive with the wiring patterns (51-57), wherein the vias (11V, 12V) have connection base portions (111V, 121V) which merge into the wiring patterns (51-57) to have certain curvatures, and cone-like portions (113V, 123V) of which the outer diameters become thinner as approaching top head portions (112V, 122V) of the vias (11V, 12V) from the connection base portions (111V, 121V).
    Type: Application
    Filed: August 6, 2012
    Publication date: January 31, 2013
    Applicant: FUJIKURA LTD.
    Inventor: Takaharu HONDO
  • Patent number: 8272128
    Abstract: A tool for changing first and second parts of a connector from a pre-assembly relationship into an assembled relationship. The tool is portable and has a frame with an operating mechanism thereon. The operating mechanism has a plunger that is movable to thereby change the relationship of the connector parts. The operating mechanism is operable by a pressurized fluid within a container that is connected to the frame.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 25, 2012
    Assignee: John Mezzalingua Associates, Inc.
    Inventors: Shawn M. Chawgo, Jeremy Amidon
  • Publication number: 20120227261
    Abstract: A method for manufacturing a printed wiring board includes forming on a support board a first resin insulation layer, forming a second resin insulation layer on the first resin insulation layer, forming in the second resin insulation layer an opening portion in which an electronic component having an electrode is mounted, accommodating the electronic component in the opening portion of the second resin insulation layer such that the electrode of the electronic component faces an opposite side of the first resin insulation layer, forming on the first surface of the second resin insulation layer and the electronic component an interlayer resin insulation layer, and forming in the interlayer resin insulation layer a via conductor reaching to the electrode of the electronic component.
    Type: Application
    Filed: February 29, 2012
    Publication date: September 13, 2012
    Applicant: IBIDEN CO., LTD.
    Inventor: Tsuyoshi INUI
  • Patent number: 8256110
    Abstract: The invention provides a method of manufacturing an electronic connector including the steps of: (a) providing an insulating body made of a fiberboard having a thermal deformation degree which is close to the printed circuit board, and a plurality of terminal receiving apertures penetrating a top surface and a under surface of the insulating body being deposed on the insulating body; (b) forming a plurality of conducting terminals respectively comprising a soldering portion soldering to the printed circuit board and a contacting arm electrically contacting with an electronic device; and (c) setting the conducting terminals into the insulating body.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: September 4, 2012
    Assignee: Lotes Co., Ltd.
    Inventor: Ted Ju
  • Patent number: 8241968
    Abstract: A printed circuit board (PCB) includes a wire pattern that has a low processing cost and a high yield by simplifying the structure of the PCB and can increase the joining characteristics and reliability of minute bumps when a flip-chip bonding process is performed. The PCB includes a body resin layer having lower and upper surfaces, a wire pattern on or in one of the upper and lower surfaces of the body resin layer, at least one through-hole contact extending from the wire pattern through the body resin layer, and a solder resist on the upper and lower surfaces of the body resin layer, openings of the solder resist corresponding to at least one of a solder ball land and a bump land, the solder ball land and the bump land being configured to couple the PCB to a semiconductor chip. If the solder ball land is on the one-layer wire pattern, the bump land is on the through-hole contact, and if the bump land is on the wire pattern, the solder ball land is on the through-hole contact.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kwan Lee, Tae-sung Park, Won-keun Kim
  • Patent number: 8220147
    Abstract: According to one mode of the present invention, metal-containing resin particles composed of a resin containing 50 wt % or more of a thermosetting resin and having a ratio of weight of absorbed moisture to weight of resin from 500 to 14500 ppm, and fine metal particles contained in said resin, is provided.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo
  • Publication number: 20120155048
    Abstract: There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.
    Type: Application
    Filed: February 24, 2012
    Publication date: June 21, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kentaro KANEKO
  • Publication number: 20120145445
    Abstract: A resin multilayer substrate includes a component-containing layer and a thin resin layer stacked on a surface of the component-containing layer. The resin multilayer substrate further includes a surface electrode located on a surface opposite to the surface of the thin resin layer stacked on the component-containing layer, a first via conductor provided in the component-containing layer, which includes an end reaching one surface of the component-containing layer, and a second via conductor provided in the thin resin layer, which includes a first end electrically connected to the surface electrode and a second end electrically connected to the via conductor. A portion of the thin resin layer in contact with the second via conductor defines a projection projecting into the first via conductor.
    Type: Application
    Filed: February 23, 2012
    Publication date: June 14, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masashi ARAI, Mayuko NISHIHARA
  • Patent number: 8171628
    Abstract: A photosensitive conductive film 10 according to the invention includes a support film 1, a conductive layer 2 containing conductive fiber formed on the support film 1, and a photosensitive resin layer 3 formed on the conductive layer 2.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: May 8, 2012
    Assignee: Hitachi Chemical Company, Ltd.
    Inventor: Hiroshi Yamazaki
  • Patent number: 8166648
    Abstract: There is provided a wiring substrate manufacturing method. The wiring substrate includes: a plurality of conductor patterns formed on a mounting surface on which an electronic component is to be mounted, wherein each of the conductor patterns is covered with a corresponding one of solder layers; and partition walls made of insulating material and formed along the conductor patterns on the mounting surface such that each of the partition walls is provided between the adjacent conductor patterns with a clearance interposed therebetween.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 1, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Katsuya Fukase
  • Patent number: 8146247
    Abstract: A method for packaging the sensor units is shown below. First step is providing a substrate, and each sensor area on the substrate is partitioned into two individual circuit areas. An emitter and a detector are installed on the two circuit areas respectively. Step two is forming a first packaging structure to cover the two circuit areas, the emitter and the detector by a mold. Next step is cutting the first packaging structure to form cut groove between and around the emitter and the detector. Next step is forming a second packaging structure in the cut grooves by the same mold. At last, the panel of sensor units is diced and separated as individual sensor units. As above-mentioned, the second packaging structure is used for isolating the signals of the emitter and the detector.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: April 3, 2012
    Assignee: Lite-On Singapore Pte. Ltd.
    Inventors: Sin-Heng Lim, Amy Ge
  • Publication number: 20120075816
    Abstract: In a hybrid integrated circuit device of the present invention, leads are fixedly attached on the upper surface of a circuit board. The lead includes an island portion, a slope portion, and a lead portion. A transistor and a diode are mounted on the upper surface of the island portion. Electrodes provided on the upper surfaces of the transistor and the diode are connected to a bonding portion through a fine metal wire. The bonding portion of the lead is disposed at a higher position than the island portion. Thus, the fine metal wires connected to the bonding portion are separated from each other.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 29, 2012
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Shigeki MASHIMO, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
  • Patent number: 8096049
    Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 17, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tetsuya Koyama, Tsuyoshi Kobayashi, Hiroyuki Kato, Yoshihiro Machida
  • Patent number: 8065796
    Abstract: A method of creating an active electrode that may include providing a flex circuit having an electrode made of a first material and providing a first mask over the flex circuit, the first mask having an offset region and an opening that exposes the electrode. The method may also include depositing a second material over the offset region and the opening, the second material being different from the first material and providing a second mask over the second material, the second mask having an opening over a portion of the second material that is over the offset region.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: November 29, 2011
    Assignee: Edwards Lifesciences Corporation
    Inventor: Kenneth M. Curry
  • Patent number: 8037597
    Abstract: Positioning marks are formed on both sides of each printing block on a tape carrier for TAB. A long-sized circuit board is transported by a roll-to-roll system in screen printing. When an optical sensor detects a positioning mark, transportation of the long-sized circuit board is stopped. Thereafter, the screen printing of a solder resist is performed to the printing block of the long-sized circuit board by a screen printing device.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: October 18, 2011
    Assignee: Nitto Denko Corporation
    Inventor: Makoto Tsunekawa
  • Publication number: 20110207266
    Abstract: A printed circuit board (PCB) includes a wire pattern that has a low processing cost and a high yield by simplifying the structure of the PCB and can increase the joining characteristics and reliability of minute bumps when a flip-chip bonding process is performed. The PCB includes a body resin layer having lower and upper surfaces, a wire pattern on or in one of the upper and lower surfaces of the body resin layer, at least one through-hole contact extending from the wire pattern through the body resin layer, and a solder resist on the upper and lower surfaces of the body resin layer, openings of the solder resist corresponding to at least one of a solder ball land and a bump land, the solder ball land and the bump land being configured to couple the PCB to a semiconductor chip. If the solder ball land is on the one-layer wire pattern, the bump land is on the through-hole contact, and if the bump land is on the wire pattern, the solder ball land is on the through-hole contact.
    Type: Application
    Filed: November 3, 2010
    Publication date: August 25, 2011
    Inventors: Yong-kwan LEE, Tae-sung Park, Won-keun Kim
  • Patent number: 8001682
    Abstract: A high-efficiency production method for a power module substrate with reduced line width of a conductive pattern provides an insulation substrate suitable for realizing a large current and a high voltage of a power module. According to the method, a brazing sheet is temporarily fixed on a first surface of a ceramics substrate by surface tension of a volatile organic liquid. The brazing sheet is also temporarily fixed on the first surface of a conductive pattern member punched from a base material by surface tension of same type of volatile organic liquid. The brazing sheet and the conductive pattern member are heated so as to volatilize the volatile organic liquid and a pressure is applied to the conductive pattern member in its thickness direction. The brazing sheet is melted to join the conductive pattern member with the first surface of the ceramics substrate.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: August 23, 2011
    Assignee: Mitsubishi Materials Corporation
    Inventors: Takeshi Negishi, Toshiyuki Nagase
  • Patent number: 7992297
    Abstract: One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Shiyou Zhao, Houfei Chen, Hao Wang
  • Publication number: 20110174527
    Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided in a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. The first electrode has a first conductor having the same thickness as that of a wiring layer provided in an insulating layer, a second conductor formed on the first conductor, a gold plating layer provided on the second conductor.
    Type: Application
    Filed: June 30, 2009
    Publication date: July 21, 2011
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Kiyoshi Shibata
  • Publication number: 20110099806
    Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
    Type: Application
    Filed: December 30, 2010
    Publication date: May 5, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tetsuya Koyama, Tsuyoshi Kobayashi, Hiroyuki Kato, Yoshihiro Machida
  • Patent number: 7922918
    Abstract: There is provided a method of manufacturing a circuit board having a first fixed contact and a second fixed contact that extend substantially orthogonal to each other on the same surface, the life span required for the first fixed contact being longer than that required for the second fixed contact. The method includes: etching a copper foil formed on the entire surface of an insulating substrate to form the patterns of the first and second fixed contacts; polishing the surface of the insulating substrate with buff to remove an oxide film adhered to the copper foil; and sequentially forming a nickel layer having a thickness of about 1 to about 5 ?m and a gold layer having a thickness of about 0.01 to about 0.5 ?m on each of the first and second fixed contacts. In the method, the buffing direction is substantially aligned with a direction in which a first movable contact slides on the first fixed contact.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: April 12, 2011
    Assignee: Alps Electric Co., Ltd.
    Inventors: Yasuo Matsui, Shunji Araki
  • Patent number: 7915540
    Abstract: A tamper-proof structure for protecting an electronic module, comprising a pattern of signal lines having a highly unpredictable layout, which is an approximation of a space-filling curve obtained by the replication of at least one elementary space element having an inscribed base curve inscribed therein. The base curve is adapted, by replication of the elementary space element, to generate an approximation of an at least two-dimensional space-filling curve, the replication being such that an end of the base curve in one elementary space element is connected to the end of the base curve in another, adjacent elementary space element of the replication.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventor: Stefano Sergio Oggioni
  • Patent number: 7886438
    Abstract: At least one base material having a wiring circuit that has been formed into a predetermined outer shape is bonded to a motherboard. The motherboard wiring board and the base material having a wiring circuit are electrically connected to each other at least one portion through an inner via hole. The outer shape of the base material having a wiring circuit is smaller than the outer shape of the motherboard, with the base material having a wiring circuit having an island shape on the motherboard.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: February 15, 2011
    Assignee: Fujikura Ltd.
    Inventors: Shoji Ito, Ryoichi Kishihara, Osamu Nakao, Hiroki Hashiba, Masahiro Okamoto
  • Patent number: 7882627
    Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: February 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tetsuya Koyama, Tsuyoshi Kobayashi, Hiroyuki Kato, Yoshihiro Machida
  • Patent number: 7866028
    Abstract: A resonant element is manufactured through a process including a setting step and a forming step. A substrate of the resonant element is made of a dielectric material. A ground electrode is formed on a rear principal surface side of the substrate. Principal-surface electrodes that define resonators together with the ground electrode and the dielectric material are formed on a front principal surface side of the substrate. An electrode protecting layer is formed on substantially entire surfaces on a front principal surface side of the principal-surface electrodes and the substrate. A coupling adjusting electrode with both ends facing a plurality of the principal-surface electrodes is formed on a front principal surface side of the electrode protecting layer. In the setting step, the shape of the coupling adjusting electrode is set in each manufactured lot.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: January 11, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Motoharu Hiroshima, Soichi Nakamura, Yasunori Takei, Hirotsugu Mori
  • Patent number: 7841086
    Abstract: A method of fabricating an inkjet printhead. The method includes the steps of: (a) forming a plurality of MEMS ink ejection assemblies on an ink-ejection surface of a silicon substrate, each ink ejection assembly being sealed with roof material spanning across the ink ejection assemblies to define a nozzle plate; (b) etching partially into the roof material to form simultaneously a respective nozzle rim for each ink ejection assembly and a plurality of projections patterned across the nozzle plate between nozzle rims; and (c) etching through the roof material to form a respective nozzle aperture for each ink ejection assembly. The projections patterned across the nozzle plate between nozzle rims are useful for reducing stiction between particulates and the nozzle plate.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: November 30, 2010
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7815122
    Abstract: A method of making an electronic label including a chip (1) provided with two contact strips (2, 3) onto which a conducting wire (4) is welded in a single operation. The segment of conducting wire (4) forming the antenna is then cut between the two contact strips (2, 3) of chip (1). The group of chip and antenna thus realized may then be encapsulated between two sheets of a fibrous or plastic material.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: October 19, 2010
    Inventor: Pierre-Alain Bauer
  • Publication number: 20100200279
    Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.
    Type: Application
    Filed: December 24, 2009
    Publication date: August 12, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Takashi KARIYA, Daiki Komatsu
  • Patent number: 7676919
    Abstract: A method for forming a via in a printed circuit board is disclosed, which via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal planes. The method comprises forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Shiyou Zhao, Houfei Chen, Hao Wang