With Molding Of Insulated Base Patents (Class 29/848)
  • Patent number: 11682599
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 20, 2023
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 11404811
    Abstract: A short, high density interposer. The interposer has multiple contacts, with upwards and downwards-facing contact surfaces. Each of the contacts may be formed as a beam stamped from a sheet of metal. Two sheets of metal may be used in forming the interposer. A first sheet may be stamped with upwards facing contacts. A second sheet may be stamped with downwards facing contacts. Bases of the beams on the first sheet may be fused with bases of the beams on the second sheet, creating a conducting path through the interposer, with compliant contacts at each end. The joined contacts may be separated from the sheets from which they are stamped and held together with an insulative base of the interposer. Beams shaped to form contacts in the interposer may be closely spaced when stamped in a sheet of metal and may have a low height.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 2, 2022
    Assignee: Amphenol Corporation
    Inventors: Trent K. Do, Paul R. Taylor
  • Patent number: 11306398
    Abstract: A conductive portion of a circuit body is formed by performing spraying on a surface of a resin casing. For spraying of the conductive portion, a cold spray method in which metal powder and inert gas are sprayed to an object is used. A circuit component is mounted on the conductive portion. Each terminal portion of the conductive portion is provided with a connector for connection with an external circuit body. An insulating resin is laminated on a surface of the conductive portion. The circuit body is directly formed on the surface of the resin casing by a series of processes described above.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 19, 2022
    Inventors: Keita Shimakura, Takuo Matsumoto
  • Patent number: 11153975
    Abstract: A wiring board manufacturing method includes a sheet laminate forming step of impregnating a glass cloth with a synthetic resin to form a plurality of sheets and next stacking these sheets to form a sheet laminate having a first surface and a second surface, a core member forming step of stacking a release plate on the first surface of the sheet laminate, stacking an electrode plate on the second surface of the sheet laminate, next using a pressure plate to press the release plate, the sheet laminate, and the electrode plate in their stacked condition, thereby uniting them together to form a core member, and a grinding step of grinding the release plate of the core member in a condition where the electrode plate of the core member is held on a chuck table, thereby making a thickness of the core member uniform.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 19, 2021
    Inventor: Katsuhiko Suzuki
  • Patent number: 11071214
    Abstract: Provided is a method of manufacturing a multilayer wiring board, in which electrical inspection can be performed with accurate probing while warpage of a multilayer laminate is reduced. This method includes providing a laminated sheet including a first support, a first release layer and a metal layer; alternately stacking wiring layers and insulating layers on a surface of the metal layer, wherein an n-th wiring layer being the uppermost layer includes an n-th connection pad; bonding a second support having an opening on a surface, remote from the laminated sheet, of the multilayer laminate with a second release layer therebetween such that at least a part of the n-th connection pad is disposed within the opening; releasing the first support from the reinforced multilayer laminate at the first release layer; and putting conductors into contact with the n-th connection pads of the reinforced multilayer laminate to perform electrical inspection.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 20, 2021
    Inventors: Yoshinori Matsuura, Yasuhiro Seto, Toshimi Nakamura
  • Patent number: 10866265
    Abstract: The inspection jig includes a rigid substrate, a flexible substrate connected to the rigid substrate, a support for supporting a part of the flexible substrate in a state that the part of the flexible substrate is protruded with respect to the rigid substrate, and a stretchable contactor provided on a protruding portion of the flexible substrate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 15, 2020
    Assignee: YOKOWO CO., LTD.
    Inventor: Takahiro Nagata
  • Patent number: 10854355
    Abstract: A stretchable conductor includes a substrate with a first major surface and an elongate wire, wherein the substrate is an elastomeric material, the elongate wire is on the first major surface of the substrate, the wire includes a first end and a second end, and further includes at least one arcuate region between the first end and the second end. At least one portion of the arcuate region of the wire in the region has a first surface area portion embedded in the surface of the substrate and a second surface area portion unembedded on the substrate and exposed in an amount sufficient to render at least an area of the substrate in the region electrically conductive. The unembedded second surface portion of the arcuate region may lie above or below a plane of the substrate. Additionally, different methods of preparing said stretchable conductor are disclosed. Composite articles including said stretchable conductor in durable electrical contact with a conductive fabric are also disclosed.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: December 1, 2020
    Inventors: Ankit Mahajan, Jr., James Zhu, Saagar A. Shah, Mikhail L. Pekurovsky, Vivek Krishnan, Kevin T. Reddy, Christopher B. Walker, Jr., Michael A. Kropp, Kara A. Meyers, Teresa M. Goeddel, Thomas J. Metzler, Jonathan W. Kemling, Roger W. Barton
  • Patent number: 10811302
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung II Kang, In Seob Bae, Jea Won Kim
  • Patent number: 10811348
    Abstract: A method of manufacturing a wiring substrate includes providing a support that includes a support substrate and first and second metal layers stacked in order over the support substrate. A surface of the second metal layer facing away from the first metal layer is a roughened surface or formed of particles. The second metal layer is selectively etchable with respect to the first metal layer. The method further includes selectively forming a third metal layer on the surface of the second metal layer, forming a first wiring layer that is a laminate of the second and third metal layers by simultaneously roughening the third metal layer and dissolving the second metal layer not covered with the third metal layer using an etchant, forming an insulating layer that covers the first wiring layer on the first metal layer, removing the support substrate, and removing the first metal layer by etching.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 20, 2020
    Inventors: Kazuhiro Kobayashi, Yusuke Karasawa
  • Patent number: 10750614
    Abstract: Deformable electrical contacts with conformable target pads for microelectronic assemblies and other applications are provided. A plurality of deformable electrical contacts on a first substrate may be joined to a plurality of conformable pads on a second substrate during die level or wafer level assembly of microelectronics, for example. Each deformable contact deforms to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. The deformation process also wipes each respective conformable pad with the deformable electrical contact to create a fresh metal-to-metal contact for good conduction. Each conformable pad collapses as pressured by a compressible material to assume the approximate deformed shape of the electrical contact, providing a large conduction surface area, while also compensating for horizontal misalignment.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Gabriel Z. Guevara
  • Patent number: 10719179
    Abstract: A system and method for manufacturing a planar capacitive touch sensor that can be folded over a three-dimensional object that does not require substantial modification to function, wherein columns and rows of capacitive measurement nodes follow substantially linear designs, and wherein the algorithms used for detection and tracking objects are substantially the same as for a planar touch sensor design.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 21, 2020
    Assignee: Cirque Corporation
    Inventor: Paul Glad
  • Patent number: 10535935
    Abstract: An electrical connector for electrically connecting a chip module to a circuit board includes an insulating body, and a plurality of terminals. Each of the terminals has a base accommodated in the insulating body and a mating portion contacting a conductive sheet of the chip module. A plurality of supporting portions extend upward from an upper surface of the insulating body, and an upper end of each of the supporting portions is provided with a crumple portion located below the mating portion of one of the terminals. The chip module is mounted on the electrical connector, the conductive sheet presses the mating portion, the mating portion abuts the crumple portion, and the crumple portion is pressed so that a height of the crumple portion is decreased.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 14, 2020
    Assignee: LOTES CO., LTD
    Inventors: Ted Ju, Zhi Yong Zhou
  • Patent number: 10231623
    Abstract: A roll-to-roll printing process for large scale manufacturing of nanosensor systems for sensing pathophysiological signals is disclosed. The roll-to-roll manufacturing process may include three processes to improve the throughput and to reduce the cost in manufacturing: fabrication of textile based nanosensors, printing conductive tracks, and integration of electronics. The wireless nanosensor systems can be used in different monitoring applications. The fabric sheet printed and integrated with the customized components can be used in a variety of different applications. The electronics in the nanosensor systems connect to remote severs through adhoc networks or cloud networks with standard communication protocols or non-standard customized protocols for remote health monitoring.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 19, 2019
    Assignee: Nanowear Inc.
    Inventors: Vijay K. Varadan, Pratyush Rai, Se Chang Oh
  • Patent number: 9484568
    Abstract: The present invention provides a method of manufacturing and an apparatus for manufacturing a layered structure comprising a solid electrolyte layer, a positive electrode active material layer, and a negative electrode active material layer, which together constitute an all-solid-state battery.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 1, 2016
    Assignee: SINTOKOGIO, LTD.
    Inventors: Masahiko Nagasaka, Shogo Nakajima, Takayuki Nozawa, Osamu Sugino, Ikuto Mishima
  • Patent number: 9478674
    Abstract: A method of manufacturing a circuit board includes: forming a plurality of metal electrodes so as to be separated from each other on a holding sheet by cutting a metal foil held on the holding sheet to remove a portion of the metal foil; forming adhesive layers on surfaces of the plurality of metal electrodes; adhering the adhesive layers to a base material by closely contacting the adhesive layers with the base material; and transcribing the adhesive layers and the plurality of metal electrodes onto the base material by detaching the holding sheet from the plurality of metal electrodes.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: October 25, 2016
    Assignee: DSM IP ASSETS B.V.
    Inventors: Koichi Kumai, Ryuji Ueda, Kentaro Kubota, Shigeki Kudo, Minoru Kawasaki
  • Patent number: 9470715
    Abstract: A probe head includes a plate, a probe, and at least one composite coating layer. The plate has at least one through hole therein. The probe is at least partially disposed in the through hole of the plate. The composite coating layer includes a metal layer and a plurality of lubricating particles. The metal layer is disposed in the through hole of the plate and between the plate and the probe. The lubricating particles are dispersed in the metal layer.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: October 18, 2016
    Assignee: MPI Corporation
    Inventors: Horng-Kuang Fan, Hsien-Ta Hsu
  • Patent number: 9453768
    Abstract: A medical measurement device, such as an electronic thermometer, having a probe. The probe includes a molded plastic substrate having a conductive circuit pattern formed directly on its surface. The circuit pattern extends at least from a first end margin of the molded plastic substrate to a second end margin opposite the first. The device also includes a sensor mounted on the molded plastic substrate for detecting a physiological parameter, such as temperature. The sensor is positioned on the molded plastic substrate at the first end margin by at least one positioning element integrally formed in the substrate. The conductive circuit pattern provides an electrical connection between the sensor and a processor.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: September 27, 2016
    Assignee: Covidien AG
    Inventors: James Harr, Joseph T. Gierer
  • Patent number: 9449909
    Abstract: In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 20, 2016
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., Global Unichip Corp.
    Inventors: Chin-Sung Lin, Li-Hua Lin, Yu-Yu Lin
  • Patent number: 9204547
    Abstract: A non-planar printed circuit board has an interior surface and an exterior surface. Between the interior surface and exterior surfaces are layers of conductive and dielectric materials. Passive and active electrical components are embedded within the interior and exterior surfaces. A hollow region is defined by the interior surface of the non-planar circuit board. The non-planar printed circuit board is manufactured on a mandrel having a non-planar shape such as, for example, a cylinder or sphere so as to form a hollow, curved non-planar structure.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: December 1, 2015
    Assignee: The United States of America as represented by the Secratary of the Army
    Inventor: Bruce V. Hughes
  • Patent number: 9049807
    Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Javier Soto, Charan Gurumurthy, Robert Nickerson, Debendra Mallik
  • Publication number: 20150144384
    Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
    Type: Application
    Filed: December 12, 2013
    Publication date: May 28, 2015
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Chi-Ching Ho, Ying Chou Tsai, Sheng-Che Huang
  • Publication number: 20150142090
    Abstract: An assembly for a medical lead includes an elongated lead body, and a conductive element located at a distal portion of the lead body. The conductive element substantial!)? encircles a longitudinal axis of the lead body. The assembly further includes a plurality of insulated conductors extending within the lead body, each of the insulated conductors being in electrical contact with the conductive element and extending to a proximal end of the lead body. Each of the insulated conductors contacts a different circumferential portion of the conductive element. The conductive element is configured to facilitate mechanical and electrical separation of different circumferential portions of the conductive element to form two or more electrode segments for the medical lead from the conductive element.
    Type: Application
    Filed: February 14, 2013
    Publication date: May 21, 2015
    Inventors: Victor Duijsens, Paulus C. van Venrooij
  • Patent number: 9009958
    Abstract: A mountable device includes a bio-compatible structure embedded in a polymer that defines at least one mounting surface. The bio-compatible structure includes an electronic component having electrical contacts, sensor electrodes, and electrical interconnects between the sensor electrodes and the electrical contacts. The bio-compatible structure is fabricated such that it is fully encapsulated by a bio-compatible material, except for the sensor electrodes. In the fabrication, the electronic component is positioned on a first layer of bio-compatible material and a second layer of bio-compatible material is formed over the first layer of bio-compatible material and the electronic component. The electrical contacts are exposed by removing a portion of the second layer, a conductive pattern is formed to define the sensor electrodes and electrical interconnects, and a third layer of bio-compatible material is formed over the conductive pattern.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 21, 2015
    Assignee: Google Inc.
    Inventor: James Etzkorn
  • Patent number: 8997342
    Abstract: A method of fabricating a multilayer electronic support structure comprising electroplating copper substructures, laying a dielectric pre-preg comprising a polymer resin over the copper substructures, and pressing to pressures of 200 to 600 PSI against a release film having a higher hardness than the resin of the prepreg but a lower hardness than the cured resin, and heating through a curing cycle while maintaining pressure.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Patent number: 8976535
    Abstract: Provided are a vehicle card key and a method of manufacturing the same. The vehicle card key is used to lock/unlock a vehicle door or start an engine in wireless communication with a vehicle. The vehicle card key includes a lower cover, a circuit board stacked on and coupled to a top of the lower cover, and an upper cover coupled to the lower cover as one body to cover an upper side of the circuit board. The lower cover and the upper cover are formed of a thermo-hardening resin.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Hyundai Mobis Co., Ltd.
    Inventors: Seung Hak Paek, Ick Tae An
  • Patent number: 8973261
    Abstract: A manufacturing method of an object having a conductive line includes the following steps. A hardening layer and a conductive line layer are formed in an in-mold roller (IMR) material in sequence. The conductive line layer is formed on a non-conductive substrate by an IMR process. A carrier sheet is then separated to expose the hardening layer. A connecting piece is formed on the hardening layer. The connecting piece runs through the hardening layer by a connection process, and the connecting piece is electrically connected to the conductive line layer. Therefore, an object structure having the conductive line is formed.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Getac Technology Corporation
    Inventor: Cheng-Hung Chiang
  • Patent number: 8943682
    Abstract: A method of making a transparent touch-responsive capacitor apparatus includes providing a transparent conductor precursor structure including a transparent substrate, a first precursor material layer formed over the transparent substrate and a second precursor material layer formed on the first precursor material layer; forming a electrically connected first micro-wires in the first and second precursor material layers; forming electrically connected second micro-wires in a precursor material layer electrically connected to the first micro-wires; and wherein the height of at least a portion of the first micro-wires is greater than the height of at least a portion of the second micro-wires, and wherein the total area occupied by the first micro-wires is less than 15% of the first transparent conductor area and the total area occupied by the second micro-wires is less than 15% of the second transparent conductor area.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Eastman Kodak Company
    Inventors: Ronald Steven Cok, Terrence Robert O'Toole
  • Patent number: 8881387
    Abstract: This is directed to methods and apparatus for shielding a circuitry region of an electronic device from interference (e.g., EMI). A conductive dam may be formed about a periphery of the circuitry region. A non-conductive or electrically insulating fill may then be applied to the circuitry region within the dam. Next, a conductive cover may be applied above the fill. The cover may be electrically coupled to the dam. The dam may include two or more layers of conductive material stacked on top of one another. In some embodiments, the conductive cover may be pad printed or screen printed above the fill. In other embodiments, the conductive cover may be a conductive tablet that is melted above the fill.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 11, 2014
    Assignee: Apple Inc.
    Inventors: Gloria Lin, Wyeman Chen, Michael Nikkhoo, Michael Rosenblatt, Hammid Mohammadinia, Ziv Wolkowicki, Amir Salehi
  • Patent number: 8850700
    Abstract: A wiring board includes a substrate having an adhesive surface, a first wiring, and a second wiring. The adhesive surface is in contact with the first wiring and the second wiring. The first wiring has a penetrating hole extending in a direction perpendicular to the adhesive surface. The second wiring has a first region, a second region, and a third region, which are adjacent regions arranged in that order. The first region is inside the penetrating hole in the first wiring and in contact with a first portion of the adhesive surface that forms part of the penetrating hole. The second region is in contact with the first wiring and faces the first wiring and the substrate. The third region is in contact with a second portion of the adhesive surface outside the first portion.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Sumida
  • Publication number: 20140237816
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes extruding a substrate material according to the shape of the Z-directed component. A conductive material is then selectively applied to the extruded substrate material and the Z-directed component is formed from the extruded substrate material.
    Type: Application
    Filed: May 2, 2014
    Publication date: August 28, 2014
    Inventors: Paul Kevin Hall, Keith Bryan Hardin, Zachary Charles Nathan Kratzer, Qing Zhang
  • Patent number: 8810040
    Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Kazuhiro Kobayashi
  • Patent number: 8796556
    Abstract: The present invention provides flake having a thickness up to 350 nm, the flake being made of basalt, ceramics, alumina, graphite, a metal, a metal oxide or a combination of any two or more thereof. Equipment for manufacturing such flake is also described as is a method for the manufacture of the flake. The equipment comprises a cup mounted for rotation and for receiving molten glass. The equipment further comprises either insulating means extending at least partially around said cup or means for heating the cup while it is rotating.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: August 5, 2014
    Inventor: Charles Watkinson
  • Patent number: 8782884
    Abstract: A method for manufacturing an electrode assembly. The method comprises: forming a comb having a plurality of electrode contacts, wherein the surface of at least one of the electrode contacts comprises a plurality of indentations such that the effective surface area per area unit of a center region of the at least one electrode contact is larger than the effective surface area per area unit of the of the region of the surface outside the center region; assembling an array of electrode contacts from the comb; molding a carrier member about the assembled array of electrode contacts, wherein a surface of the at least one electrode contact is covered by a layer of the carrier member material; and removing the layer of carrier member material on the surface of the at least one electrode contact.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: July 22, 2014
    Assignee: Cochlear Limited
    Inventors: Edmond D. Capcelea, Peter Gibson, Fysh Dadd
  • Patent number: 8779561
    Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi Ho Jeong, Si Young Yang, Jae Wook Kwon, Jeong Hoon Park, Hyun Ju Yi, Choon Keun Lee
  • Patent number: 8732943
    Abstract: A liner for an appliance is formed by a plastic sheet formed into a three dimensional shape corresponding to at least a portion of a compartment of the appliance.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 27, 2014
    Assignee: Whirlpool Corporation
    Inventors: Martin Shawn Egan, Michael E. Stagg, Jr.
  • Patent number: 8720053
    Abstract: A process for fabricating a circuit board that includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: May 13, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Chang Lee, Kun-Ching Chen, Ming-Loung Lu, Chun-Che Lee
  • Publication number: 20140111955
    Abstract: Representative implementations of devices and techniques provide improved electrical access to components, such as chip dice, for example, disposed within layers of a multi-layer printed circuit board (PCB). One or more insulating layers may be located on either side of a spacer layer containing the components. The insulating layers may have apertures strategically located to provide electrical connectivity between the components and conductive layers of the PCB.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Inventor: Martin STANDING
  • Patent number: 8701283
    Abstract: A method for producing an integrated device including a capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate, forming a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate, forming a second conductive layer including a second plate of the capacitor and functional connections to the functional circuits on a portion of the layer of insulating material corresponding to the dielectric layer, forming a protective layer of insulating material covering the second plate and the functional connections, forming a first contact for contacting the first plate, and forming a second contact and functional contacts for contacting the second plate and the functional connections, respectively, through the protective layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 22, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alessandro Dundulachi
  • Publication number: 20140098507
    Abstract: The present invention relates to a printed circuit board, a semiconductor package using the same, and a method for manufacturing the printed circuit board and the semiconductor package. The method for manufacturing a semiconductor package in accordance with the present invention includes: forming a circuit of a predetermined pattern on a PCB substrate; applying a first insulating material on the substrate; removing the first insulating material in the remaining portion except a predetermined portion by exposing and developing the substrate; forming a solder bump in the circuit portion exposed; molding a certain region of an upper surface portion of the PCB substrate including the solder bump by filling a second insulating material on the PCB substrate including the circuit portion; mounting a semiconductor chip on the PCB substrate; and completing one package in which the semiconductor chip and the PCB substrate are integrated.
    Type: Application
    Filed: March 14, 2013
    Publication date: April 10, 2014
    Inventors: Young Soon Kim, Jun Han Kim
  • Patent number: 8677605
    Abstract: A method for manufacturing a sensor unit includes the steps of: Step 1 is providing a substrate having sensor unit areas. Each sensor unit area is partitioned into two individual circuit areas. A signal emitting device and a signal detecting device are respectively disposed on the two circuit areas. Step 2 is forming a packaging structure to cover the two circuit areas, the signal emitting device, the signal detecting device, and a cutting area between the two circuit areas using a mold. Step 3 is cutting the packaging structure along the cutting area to form a separation cut groove. Step 4 is assembling a separation member onto each sensor unit area. The separation member is disposed on the separation cut groove so that the signal emitting device and the signal detecting device on the same sensor unit area are isolated from each other.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 25, 2014
    Assignee: Lite-On Singapore Pte. Ltd.
    Inventors: Sin-Heng Lim, Teck-Chai Goh
  • Patent number: 8671562
    Abstract: A method for manufacturing a circuit board includes the steps of: forming a first wiring layer on a substrate; forming an insulating layer on the surface of the first wiring layer by means of electrophoretic deposition; forming a second wiring layer on the insulating layer and the surface of the substrate; and performing the follow-up procedures, such as forming a solder mask; thereby reducing the thickness of the circuit board and increasing the density of the circuit layout.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Chien Hao Wang
  • Patent number: 8631567
    Abstract: A method of manufacturing a rigid-flexible printed circuit board, including providing a base substrate in which coverlays are respectively formed on two sides of a flexible copper foil laminate on both sides of which inner circuit patterns are respectively formed; layering insulation layers and copper foil layers on portions of coverlays which are to be a rigid region of the flexible copper foil laminate; forming a via hole in the rigid region, and, simultaneously, forming first windows in the coverlays in a flexible region; forming outer circuit patterns including areas adjacent to the first windows; and applying solder resist in the rigid region to expose portions of the external circuit patterns, where the outer circuit patterns formed in the areas adjacent to the first windows include additional plating portions for covering portions of the coverlays.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: January 21, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yang Je Lee, Il Woon Shin, Going Sik Kim, Doo Pyo Hong, Ha Il Kim, Dong Gi An
  • Patent number: 8629354
    Abstract: A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: January 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shi-Yun Cho, Ho-Seong Seo, Youn-Ho Choi
  • Patent number: 8615872
    Abstract: A flow measurement device and a method of manufacturing a flow measurement device having a measurement tube made from plastic or at least a plastic liner are provided. According to an exemplary embodiment, the measurement tube can be fabricated from plastic in an injection molding apparatus. Thereafter, electrical components of the measurement tube, such as electrodes and a coil holder, for example, can be concomitantly injection molded in a common, separate injection molding process. The electrical components can there be installed easier and more reliably in position.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: December 31, 2013
    Assignee: ABB Technology AG
    Inventors: Karl-Heinz Rackebrandt, Klaus Schäfer, Marco Ehrenberg
  • Patent number: 8607444
    Abstract: Improved techniques for forming an electronic device housing in which an outer housing member can be assembled with one or more other housing members of the electronic device are disclosed. The one or more other housing members can together with a thin substrate layer (or thin substrate) form a frame to which the outer housing member can be secured. The thin substrate layer facilitates molding of the one or more other housing members adjacent to the outer housing member. In one embodiment, the outer housing member can be made of glass and the one or more other housing members can be made of a polymer, such as plastic. The substrate layer can, for example, be formed of a polymer or a metal. The resulting electronic device housing can be thin yet be sufficiently strong to be suitable for use in electronic devices, such as portable electronic devices.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 17, 2013
    Assignee: Apple Inc.
    Inventors: Daniel W. Jarvis, Stephen Paul Zadesky, Pinida Jan Moolsintong, Tang Yew Tan
  • Patent number: 8567049
    Abstract: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1).
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 29, 2013
    Assignee: Raytheon Company
    Inventor: Keith V. Guinn
  • Patent number: 8567050
    Abstract: A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB device 101 includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. A single-shot molding process is used to form both an upper housing portion on the upper PCB surface that includes ribs extending between adjacent contact pads, and a lower molded housing portion that is formed over passive components and IC dies disposed on the lower PCB surface. The passive components are mounted using SMT methods, and the IC dies are mounted using COB methods. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: October 29, 2013
    Assignee: Super Talent Technology, Corp.
    Inventors: Siew S. Hiew, Abraham C. Ma, Nan Nan
  • Publication number: 20130273756
    Abstract: An electrical connector includes a dielectric housing, a plurality of electrical signal contacts supported by the dielectric housing, and an electrically conductive ground plate supported by the dielectric housing. The dielectric hosing defines at least one protrusion, and the ground plate defines at least one aperture that receives the protrusion. The apertures can define a first dimension along a select direction and a second dimension along the select direction, wherein the first dimension is greater than the second dimension so as to define a lead-in for the protrusion. The protrusion can be press-fit to the electrically conductive ground plate at the second dimension of the aperture so as to secure the ground plate to the dielectric housing.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 17, 2013
    Inventors: Stuart C. Stoner, Douglas M. Johnescu, Jonathan E. Buck
  • Patent number: 8555493
    Abstract: Described herein is a method of manufacturing a molded printed circuit board. The printed circuit board may be placed inside of a mold and a material is injected therein. The material hardens in the mold around the printed circuit board thereby forming an overmolded printed circuit board. The overmolded material may have apertures in it to allow access to the leads on the printed circuit board so that components to be connected to it. The overmolded printed circuit boards may allow a plurality of electrical components to selectively and removably attach to it. Further, the printed circuit board may be molded with components or a dock attached to it.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 15, 2013
    Assignee: Psion, Inc.
    Inventors: Bo Xu, Yanmin Mao
  • Patent number: 8549737
    Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 8, 2013
    Assignee: General Dynamics Advanced Information Systems, Inc.
    Inventor: Deepak K. Pai