Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.

Abstract: A method for forming a molded circuit board is provided. The method includes the steps of forming a circuit having a first section and a second section on a conductive substrate, the first section and the second section being coplanar; then deforming the conductive substrate by mold-pressing, so that the first section and the second section become non-coplanar; providing a plastic material to cover the circuit and the conductive substrate; curing the plastic material by injection-molding; and removing the conductive substrate to expose the circuit. The molded circuit board made by this method is also provided.

Abstract: A method for forming a via in a printed circuit board is disclosed, which via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal planes. The method comprises forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.

Abstract: A poly sheet continuously moving in a machine direction is heated to a temperature just below its glass thermal temperature to make the poly malleable. A circuit (e.g., RFID chip, EAS chip, transponder, IC) is placed on the poly sheet and embedded into the poly sheet, preferably with a heat resistant soft (e.g., rubber) roller that presses the circuit into the poly without breaking the circuit. A conductive strip or wire may be applied on or into the poly sheet to align with connection points (e.g., conductive bumps) of the circuit for conductive communication with the circuit. The conductive strip or wire is preferably cut to form gaps that are nonconductive between the cut sections of wire to avoid shorting of the circuit and/or allow the conductive strip or wire to function as an antenna for the circuit, and thus to form a chip strap or tag. The poly sheet thus provides a protective womb or shield for the circuit and wire.

Abstract: The present invention generally relates to a method for forming a flat panel for an X-ray detector device. The method comprises forming an active area of a first size on a substrate of a second size and extending at least one contact of the active area. The method further comprises trimming the substrate to the first size forming the flat panel.

Abstract: A method of forming a low-stiction nozzle plate for an inkjet printhead, said nozzle plate having a plurality of nozzle apertures defined therein, each nozzle aperture having a respective nozzle rim, said method comprising the steps of: (a) providing a partially-fabricated printhead comprising a plurality of inkjet nozzle assemblies sealed with roof material; (b) etching partially into said roof material to define simultaneously said nozzle rims and a plurality of stiction-reducing formations; and (c) etching through said roof material to define said nozzle apertures, thereby forming said nozzle plate.

Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

Abstract: A multilayer PCB including at least one carrier, wherein the at least one carrier comprises a pseudo three-layer core. Each three-layer core includes a first metal layer, a first dielectric layer, an internal bridge layer, a second dielectric layer, and a second metal layer. The bridge layer includes a plurality of bridge pads. Each carrier includes a plurality of interlayer interconnection units for interconnecting the first and second metal layers. Each interlayer interconnection unit comprises a pair of opposed blind vias and a bridge pad disposed between, and in electrical contact with, the pair of blind vias.

Abstract: A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least another portion integral with the fixed portion, laterally unsupported within a thickness of the substrate and extending beyond a side thereof. Dual-sided compliant contact structures, methods of forming compliant contact structures, a method of testing a semiconductor device and a testing system are also disclosed.

Abstract: An exemplary method of manufacturing a metal cover (1) with blind holes (3) therein includes: step (60), preparing a metal substrate; step (62), covering the metal substrate with a protective film formed by electrophoretic deposition; step (64), forming holes in the protective film according to an intended pattern of the blind holes in the metal cover, thus exposing the metal surface through the holes; step (66), etching the metal substrate in the exposed areas to form the blind holes; and step (68), removing a remainder of the protective film from the metal substrate, thereby obtaining the finished metal cover. The method involving etching is relatively low-cost. Additionally, because electrophoretic deposition is used to cover the metal substrate with the protective film, the protective film can be formed on all surfaces of the metal substrate. Thus the method is especially advantageous for manufacturing a metal cover having a three-dimensional shape.

Abstract: An electronic component and an electronic-component production method in which the magnitude of a stray capacitance produced between adjacent outer electrodes is controllable. The electronic component includes a chip body and first to fourth outer electrodes. In the chip body, first and second coil block are sandwiched between magnetic substrates. Dielectric layers are interposed between the outer electrodes and the chip body such as to be away from exposed portions of coil patterns in the coil blocks. The dielectric layers have a width larger than a width of the outer electrodes, and a dielectric constant of the dielectric layers is set to be lower than the dielectric constant of the magnetic substrates.

Abstract: A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Abstract: A method for fabricating a tape substrate includes forming, on an insulating film, a copper foil pattern having a connecting area; coating a solder resist on the formed copper foil pattern, at a region other than the connecting area; plating a barrier layer on the copper foil pattern at the connecting area after the coating of the solder resist; and plating tin on the plated barrier layer plated, thereby forming a tin layer on the barrier layer. Another method for fabricating a tape substrate includes forming, on an insulating film, a copper foil pattern having a connecting area; plating a barrier layer over the formed copper foil pattern; plating tin over the barrier layer after the plating of the barrier layer, thereby forming a tin layer over the barrier layer; and coating a solder resist on the tin layer at a region other than the connecting area, after the formation of the tin layer.

Abstract: A method of manufacturing an electronic part packaging structure including a step of mounting an electronic part, which has a connection terminal and a passivating film to cover the connection terminal, on a mounted body to direct the connection terminal upward, a step of forming an insulating layer to cover the electronic part, a step of forming a via hole in a portion of the passivating film and the insulating layer on the connection terminal to expose the connection terminal, and a step of forming a wiring pattern, which is connected electrically to the connection terminal via the via hole, on the insulating layer.

Abstract: The present invention relates to a method for forming an active area or flat panel in an X-ray detector device. The method comprises forming at least one flat form factor panel in a first size on a substrate of a second size and extending at least one contact of the at least one flat form factor panel. The method further comprises trimming the substrate to the first size forming the at least one flat panel.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the comers of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.

Abstract: An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making an electrode structure by providing a substrate; forming a plurality of electrodes on the substrate; growing at least one nano-wire from the edge of a first electrode; and connecting the at least one nano-wire to the edge of a second electrode is also disclosed.

Abstract: A process for producing a printed wiring board-forming sheet comprising a resin sheet having a through hole in the thickness direction and a metal chip inserted in the through hole. The sheet is produced by placing a resin sheet and conductive metal sheet in this order on a die base having a die hole, performing punching from the conductive metal sheet side to form a punched hole in the conductive metal sheet and to form a punched hole in the resin sheet and inserting the punched conductive metal chip in the through hole of the resin sheet whereby the front and back surfaces of the sheet can be electrically connected to each other. If the conductive metal chip is so inserted that its tip protrudes from the surface of the sheet, and if a large number of such substrates are laminated, electrical connection in the thickness direction can readily be made by virtue of the protruded conductive metal chips and a multi-layer board can be readily produced.

Abstract: A method for forming a conductive circuit on a substantially non-conductive substrate includes indenting a major surface of a substrate with a plurality of features, plating the major surface and the indentations formed with a conductive layer, and removing a portion of the conductive layer leaving at least one of the plurality of the indentations filled with conductive material separated from at least one other of the plurality of the indentations filled with conductive material separated by non-conductive material. An electrical device formed includes a sheet of insulative material having grooves therein. The sheet of insulative material has a first planar surface, and a second planar surface. A conductive material is positioned within the grooves. The conductive material within the grooves forms electrical traces in the electrical device. The conductive material within the grooves fills the groove and includes a surface coplanar with at least one of the first planar surface or the second planar surface.

Abstract: A common electrode line for plating is used for forming conductive patterns of a plurality of circuit substrates on a main substrate. The main substrate has a cut line for dividing one and the other circuit substrates and a plurality of through holes formed on the one and the other circuit substrates along the cut line. The common electrode lines for plating includes first common electrode lines formed on one side of the main substrate, and second common electrode lines formed on the other side of the main substrate. Each first common electrode line extends from one through hole formed on the one circuit substrate to one through hole formed on the other circuit substrate. Each second common electrode line extends from the one through hole formed on the one circuit substrate to another through hole formed on the other circuit substrate.

Abstract: The touch panel comprises two conductive substrates arranged in parallel and secured to each other with a gap existing between the conductive substrates The process for implementing a conductive tracing layout in a touch panel includes steps of forming a first conductive layer on at least one of the conductive substrates; forming a first photo-resist layer on the first conductive layer; removing a specified portion of the first photo-resist layer to form a first specified mask on a specified portion of the first conductive layer; and removing the first conductive layer except the specified portion of the first conductive layer to form a first conductive tracing layout.

Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.

Abstract: Method and apparatus for controlling an injection molding machine having a first surface and a second surface includes a piezo-ceramic sensor configured to be disposed between the first surface and a second surface. The piezo-ceramic sensor is configured to sense a force between the first surface and the second surface, and to generate corresponding sense signals. Transmission structure is coupled to the piezo-ceramic sensor and is configured to carry the sense signals. Preferably, a piezo-ceramic actuator is also disposed between the first surface and a second surface, and is configured to provide an expansive force between the first surface and a second surface in accordance with the sense signals.

Abstract: A method and apparatus are disclosed for controlling temperature of a plant comprising plural temperature control zones, wherein an effective control parameter for a first zone for which a signal representing measured temperature is available is produced according to an algorithm relating measured temperature, a desired temperature and a control parameter associated with a device affecting temperature in the first temperature control zone, the effective control parameter is summed with an offset value representing a proportional offset of the effective control parameter of a second temperature control zone relative to the effective control parameter of the first temperature control zone and the result is applied to control a device affecting temperature in the second temperature control zone.

Abstract: By using a method for manufacturing a dielectric laminated device, an opening is formed on a first dielectric sheet, a strip line and an input and output line including an input and output electrode are formed by burying electrode materials in said opening, the first dielectric sheet is laminated with the second and third dielectric sheets disposed above and below respectively to form a laminate, a first and second shield electrodes and a ground electrode are formed, an end of the strip line is connected to the ground electrode, the first shield electrode and the second shield electrode are mutually connected through the ground electrode, and the input and output electrode is exposed along the line direction of the strip line. By this constitution of the above dielectric laminated device, the mounting reliability of the dielectric laminated device can be further increased.

Abstract: A method for manufacturing multilayer ceramic substrates in accordance with a multiple formation method using a non-shrinkage process allows the multilayer ceramic substrates to be smoothly formed by dividing a sintered multilayer mother substrate, and in addition, external terminal electrodes in a preferable state can be efficiently formed. When a green composite laminate comprising shrinkage suppression layers and a green multilayer mother substrate provided therebetween is formed, through-holes are provided on dividing lines so as to divide conductors, and in addition, cut-in grooves are provided along the dividing lines. After the shrinkage suppression layers are removed from the fired composite laminate, the multilayer ceramic substrates are obtained by dividing the multilayer mother substrate along the through-holes and the cut-in grooves.

Abstract: A resin filled board is manufactured by forming roughened surfaces on a conductive layer in a throughhole before it is filled with a resin, forming smooth surfaces on conductive layers on the top and bottom of the board, printing the resin using a mask having an opening at a position corresponding to the throughhole to selectively fill the resin in the throughhole, and curing the resin. In this way, the surface of the conductive layer around the throughhole is smoothed, so that hardly any of the resin remains on the surfaces near the throughhole when the surfaces of the board is mechanically polished after the resin is cured. Also, the filling resin will not fall down into the throughhole.

Abstract: The invention encompasses methods of preparing interposers for utilization in semiconductor packages. The invention includes a method in which an interposer substrate having a surface and a conductive layer extending over the surface is provided. Pads are formed on the conductive layer by plating a conductive material on the conductive layer while using the conductive layer as an electrical connection to a power source and without utilizing conductive busses, other than the conductive layer. Subsequent to the formation of the pads, the conductive layer is patterned into circuit traces. Methodology of the present invention can be utilized for, for example, forming board-on-chip constructions.

Abstract: A method of manufacturing a circuit board by forming a circuit pattern in a short process and capable of performing pattern transfer with stability. The manufacturing method includes a step of superposing on a carrier a resist layer in which a circuit pattern is formed and which is formed of a conductor or an insulator, a step of filling the circuit pattern with an electroconductive material, a step of removing the resist layer from the carrier, and a step of transferring the electroconductive material filled in the circuit pattern into an electrical insulating material.

Abstract: The invention relates to a microbeam oscillator. Tuning of the oscillator is carried out by addition or subtraction of material to an oscillator member in order to change the mass of the oscillator member.

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.

Abstract: A high-density circuit has a plurality of conductors formed in grooves in a ceramic substrate, the conductors having a height less than that of the walls of the grooves. The substrate is embossed with a pattern of grooves corresponding to the grooves in an electroform made from a master tool. The same master tool is used to form a stencil which mates with the grooved substrate. A cermet paste is pushed through the stencil, so as to fill the bottom region of the grooves, and the stencil is then removed, leaving only the paste at the bottom of the grooves. The substrate is then fired, causing the substrate to harden, and causing the cermet to become conductive and to become firmly bonded to the substrate. Because the stencil and the substrate are made from the same, or replications of the same, master tool, the cermet paste can be laid down with great precision, thus enhancing the quality of the product, and reducing the cost of its manufacture.

Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.

Abstract: The present invention provides a method of forming a solder ball on a portion, e.g., one end, of a contact. In one exemplary embodiment, the contact is a terminal pin which is intended for use in an electrical connector and more particularly, for use in a solder ball grid array (SBGA) connector. Generally and according to one embodiment, the method includes providing the contact along with a solder-holding clip having a body with an opening. The body has a solder-holding conformation adjacent the opening and a solder mass is held by the conformation. The contact is then positioned proximate to the body opening and heat is applied to the solder mass causing the solder to reflow so that the solder flows into a spherical shape. This results in a solder ball being formed on the portion of the contact. Subsequent to forming the solder ball, the solder-holding clip is separated from the contact leaving a contact with a solder ball affixed thereto.

Abstract: An object is to reduce damage to the mechanical parts of a moving mechanism unit 5 for moving a retaining mechanism unit 7 and electric power consumption in an apparatus for taking out a molded product. The apparatus comprises a time measuring unit 4 for measuring a return time elapsing between a start of the returning operation of the retaining mechanism unit 7 in a preceding process and the next start of the penetrating operation for taking out a molded product; an arithmetic operation unit 11 for calculating a return moving speed distribution for a process succeeding the preceding process such that the returning operation terminates upon elapse of the return time measured by the time measuring means 4; and a control unit 12 for activating the moving mechanism unit 5 in such a way that the returning operation is carried out according to the return moving speed distribution in the succeeding process.

Abstract: By using a method for manufacturing a dielectric laminated device, an opening is formed on a first dielectric sheet, a strip line and an input and output line including an input and output electrode are formed by burying electrode materials in said opening, the first dielectric sheet is laminated with the second and third dielectric sheets disposed above and below respectively to form a laminate, a first and second shield electrodes and a ground electrode are formed, an end of the strip line is connected to the ground electrode, the first shield electrode and the second shield electrode are mutually connected through the ground electrode, and the input and output electrode is exposed along the line direction of the strip line. By this constitution of the above dielectric laminated device, the mounting reliability of the dielectric laminated device can be further increased.

Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.

Abstract: A monitoring and control system for use in curing composite materials includes a model for a workpiece being cured. The model calculates current internal states of the workpiece and predicts, based upon past and current states of the workpiece, future states of the cure process. These future states are represented as virtual inputs to the controller, which controls operation of the cure process based upon both real and virtual inputs. Cure rates are affected by both external temperatures and internal heat generated by the curing process itself. The internally generated heat is considered by the model when calculating current states and predicting future states. By projecting the cure state into the future, problems caused by high cure rates can be avoided. In addition, pressure can be optimally controlled in response to estimated internal material state.

Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.

Abstract: A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip is used to make a notch in a vertical interconnect area of two organic electrically conducting areas separated from each other by an organic electrically insulating area. The method is used in the manufacture of integrated circuits consisting substantially of organic materials.

Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.

Abstract: Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.

Abstract: A method of manufacturing a multilayer printed circuit board, which ensures connections between vias. First, insulating sheets are attached to respective end faces of inner via holes formed through an insulating layer, and then a new insulating layer is formed on the insulating layer. Then, a circuit pattern is formed on the new insulating layer, and then each land formed on the new insulating layer at a location opposed to a corresponding one of the inner via holes is perforated by using a laser beam to have a hole continuous with an inner hole of the corresponding inner via hole. Thereafter, plating is carried out to form a build-up via for connecting between each of the lands and the corresponding inner via hole. The same process is repeatedly carried out whenever a new insulating layer is provided on the existing layers.

Abstract: At least one conductive circuit 46 is formed on a substrate 12 that has a conductive layer 28 and a cover layer 40 bonded thereto. The conductive circuit 46 is formed by the severing of the conductive layer 28 into a conductive circuit 46 and a remaining portion 48 by a cutting edge of a cutting tool 50. The edge of the tool also causes the severed edges of the conductive path and the remaining portion to form a gap 52. An electrical insulating coating 54 covers the cover layer while filling the gaps 52. The insulator coating 54 is allowed to set for maintaining separation and integrity of the conductive path 46. The method of the present invention lends itself to manual, semi-automatic and/or automatic production of discrete articles.

Abstract: A circuit substrate utilizes buried edge connectors. The buried edge connectors are mechanically disposed within the edge of the substrate and have substantial thickness. The configuration and method for making the same provides relatively large edge connectors mechanically constrained in the edge of a circuit substrate.