Abstract: An interconnection substrate includes: a substrate having a first surface and a second surface opposite the first surface; and a transmission line including two parallel through-hole interconnections that are exposed to the first and second surfaces and are formed inside the substrate. Also, at least one of the two through-hole interconnections includes a narrow portion having a smaller diameter than a diameter of the through-hole interconnection in the first surface and a diameter of the through-hole interconnection in the second surface.

Abstract: A printed circuit board package structure includes a substrate, plural ring-shaped magnetic elements, a support layer, and first conductive layers. The substrate has two opposite first and second surfaces, first ring-shaped recesses, and first grooves. Each of the first ring-shaped recesses is communicated with another first ring-shaped recess through at least one of the first grooves, and at least two of the first ring-shaped recesses are communicated with a side surface of the substrate through the first grooves to form at least two openings. The ring-shaped magnetic elements are respectively located in the first ring-shaped recesses. The support layer is located on the first surface, and covers the first ring-shaped recesses and the first grooves. The support layer and the substrate have through holes. The first conductive layers are respectively located on surfaces of support layer and substrate facing the through holes.

Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention may include: an insulating layer; a first via depressed from one surface of the insulating layer; a second via depressed from the other surface of the insulating layer; and a circuit pattern formed in the insulating layer and bonded to the first and second vias.

Abstract: The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.

Abstract: A method for metalizing at least one blind via formed in at least one substrate, including: a) arranging at least one solid portion of electrically conductive material in the blind via, b) performing a thermal treatment of the solid portion of electrically conductive material, making it melt in the blind via, cooling the electrically conductive material, solidifying it in the blind via, and wherein, before carrying out step a), at least part of the walls of the blind via is covered with a material able to prevent wetting of said part of the walls of the blind via by the melted electrically conductive material obtained during the performance of step b), the solidified electrically conductive material obtained after carrying out step c) being able not to be secured to said non-wetting part of the walls of the blind via.

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

Abstract: A method for manufacturing an interposer including forming a first insulating layer comprising an inorganic material on a supporting substrate, forming a first wire in the first insulating layer, forming a second insulating layer on a first side of the first insulating layer, forming a second wire with a longer wire length and a greater thickness than the first wire on the second insulating layer, and removing the supporting substrate.

Abstract: The disclosed structure (10) is provided with: at least three conductors (111, 131, 151) which face one-another; a through-via (101) which passes through each of the conductors (111, 131, 151); openings (112, 152) which are provided so as to surround the circumference of the through-via (101); and conductor elements (121, 141) which are located in different layers to those in which the conductors (111, 131, 151) are located, and which are connected to the through-via (101). Facing opening 112 is conductor element 121, which is larger than said opening (112), and facing opening 152 is conductor element 141, which is larger than said opening (152).

Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.

Abstract: A method for manufacturing multilayer printed circuit board includes step below. A metal substrate is provide, the metal substrate includes a number of substrate unit. A first insulating layer is formed on one surface of the metal substrate. The first insulating layer has a number of first through holes. An electrically conductive circuit is formed in each substrate unit. A second insulating layer is formed on the other surface of the metal substrate. The second insulating layer has a number of second through holes. A first metal cylinder is formed in a first through hole and a second metal cylinder is formed in a second through hole. The number of substrate units are folded and laminated, the connected and aligned first metal cylinder and the second metal cylinder communicates the electrically conductive circuits.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: A process for manufacturing a multilayer article, the article comprising two crosslinked semiconductive layers separated by and bonded to an insulation layer, the semiconductive layers formed from a peroxide-crosslinkable olefin elastomer and the insulation layer comprising composition comprising a silane-grafted olefinic elastomer, the process comprises the steps of: (A) injecting the silane-grafted olefinic elastomer between the two crosslinked semiconductive layers so as to have direct contact with each semiconductive layer, and (B) crosslinking the silane-grafted olefinic elastomer in the absence of a peroxide catalyst.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.

Abstract: A metal core substrate is obtained as a result of outline shaping performed on a substrate including a core plate and an insulating layer provided on each of two surfaces of the core plate. At least a part of an outer circumferential edge of the metal core substrate has an insulating structural portion, which includes an end surface of the core plate that is retracted from an end surface of the outer circumferential edge of the metal core substrate and an insulating covering portion that is formed of a resin used to form the insulating layers and covers the end surface of the core plate. Separation portions to be filled with the resin and coupling portions which are to be removed before outline shaping are formed at outline shaping positions of the core plate. At the time of outline shaping, only the resin is present at the outline shaping positions. Thus, outline shaping can be performed without using a die.

Abstract: Disclosed herein are an interposer board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the interposer substrate may include: a base substrate; a circuit pattern formed on the base substrate; and a through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern.

Abstract: A wiring substrate is provided with a support substrate (31), an insulating layer (32), and a wiring layer (33). The support substrate (31) is formed with a hole (34) including an opening portion in one surface of the support substrate (31). The insulating layer (32) is formed on a surface of the support substrate (31) opposite to the one surface thereof including the opening portion. The wiring layer (33) includes a wiring pattern of a predetermined structure on the insulating layer (32). Further, an orthographic projection to be obtained when the wiring pattern is projected on a predetermined surface of the support substrate (31), and an orthographic projection to be obtained when the hole (34) is projected on the predetermined surface of the support substrate (31) include a shared portion.

Abstract: Disclosed herein is a device embedded printed circuit board, including: a first core layer having a first via and having a via land for a first connection pad disposed on a lower surface thereof; a build-up layer formed on the first core layer and having a plurality of circuit layers including a second connection pad, a plurality of insulating layer disposed between the plurality of circuit layers, and a second via connecting the plurality of circuit layers; and a second core layer formed on the build-up layer and having a cavity.

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract: A method for forming an acoustical stack for an ultrasound probe comprises partly dicing a single crystal piezoelectric material to form single crystal pieces that are partly separated by a plurality of kerfs. The single crystal piezoelectric material comprises a carrier layer. The kerfs are filled with a kerf filling material to form a single crystal composite and the carrier layer is removed. At least one matching layer is attached to the single crystal composite, and dicing within the kerfs is accomplished to form separate acoustical stacks from the single crystal composite.

Abstract: A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.

Abstract: An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulation layer; pattern parts formed on both surfaces of the insulation layer; a connection pad disposed between the pattern parts and having a step part; a first plated layer formed on the pattern part; an oxide film formed on a region excluding a region on which the first plated layer is formed; a second plated layer formed on the connection pad; and a solder ball covering the connection pad.

Abstract: A manufacturing method of a package carrier is provided. An insulation substrate having an upper surface, a lower surface, plural cavities located at the lower surface and plural through holes passing through the insulation substrate and respectively communicating with the cavities is provided. Plural vias is defined by the cavities and the through holes. A conductive material filling up the vias is formed to define plural conductive posts. An insulation layer having a top surface and plural blind vias extending from the top surface to the conductive posts is formed on the upper surface. A patterned circuit layer filling up the blind vias, being connected to the conductive posts and exposing a portion of the top surface is formed on the top surface. A solder mask layer is formed on the patterned circuit layer and has plural openings exposing a portion of the patterned circuit layer to define plural pads.

Abstract: Disclosed herein is a method for manufacturing a multi-layered printed circuit board, the method including: an operation of preparing a substrate having an insulating layer and a surface-treated copper foil sequentially formed on an inner layer circuit; an operation of forming a hole exposing the insulating layer by performing a primary processing for the surface-treated copper foil and a part of the insulating layer with laser; and an operation of forming a through-hole exposing the inner layer circuit by performing a secondary processing for the exposed insulating layer with a chemical etching liquid.

Abstract: A method for preparing a conductive circuit can begin with the preparation of a non-conductive substrate having a top surface and a bottom surface, and then utilizing a pulse laser to create a top circuit pattern upon the top surface, a bottom circuit pattern upon the bottom surface, and a through hole connecting the top circuit pattern with the bottom circuit pattern. Subsequently, a conductive circuit is formed upon the top circuit pattern and the bottom circuit pattern and inside the through hole, wherein the conductive circuit is restricted from being formed upon the top surface outside of the top isolation region and the bottom surface outside of the bottom isolation region.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.

Abstract: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.

Abstract: A bolometric detector includes a substrate; bolometric detection microbridges suspended above the substrate and thermally insulated from the substrate; bolometric compensation microbridges suspended above the substrate and thermalized to the substrate; and a read circuit formed in the substrate to apply a biasing to the detection microbridges and to the compensation microbridges and to form differences between signals generated by detection microbridges and signals generated by compensation microbridges under the effect of the applied biasing. Each detection microbridge and each compensation microbridge includes electrically-conductive anchoring nails connected to the read circuit, a membrane attached to the anchoring nails above the substrate, and a thermometric element arranged in the membrane. The detector further includes thermal short-circuit elements between the membrane of each compensation microbridge and the substrate.

Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.

Abstract: There is provided a method of manufacturing liquid transporting apparatus including: providing a channel unit; providing a piezoelectric actuator having a first and second active portion corresponding to a central portion and an outer periphery portion of the pressure chamber, respectively. The first and second active portions are sandwiched between an upper electrode and an intermediate electrode, and between the upper electrode and a lower electrode, respectively. The method further includes joining the channel unit and the piezoelectric actuator by positioning such that the intermediate electrode overlaps the central portion of the pressure chamber. Accordingly, since it is possible to make the first active portion overlap the central portion of the pressure chamber, it is possible to apply a appropriate pressure to the liquid in the pressure chamber without excessively small deformation of the first active portion.

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.

Abstract: The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Abstract: A method of forming an interconnect assembly including forming a substrate with a plurality of through holes extending from a first major surface to a second major surface. A plurality of recesses are formed in the second major surface of the substrate that at least partially overlap with the plurality of through holes. The recesses have a cross-sectional area greater than a cross-sectional area of the through holes. At least one discrete contact member is inserted in a plurality of the through holes. The contact members include proximal ends extending into the recesses, distal ends extending above the first major surface, and intermediate portions engaged with an engagement region of the substrate located between the first major surface and the recesses. Retention members at least partially deposited in the recesses bond to the proximal ends to retain the contact members in the through holes.

Abstract: In some embodiments, a printed circuit board, configured to be coupled to electronic components, includes a first material portion and any number of second material portions. Each second material portion is sized and spaced apart from an adjacent second material portion such that electromagnetic waves associated with the operation of the electronic components are substantially not reflected. The first material portion defines a first dielectric constant and the second material portion defines a second dielectric constant that is different than the value of the first dielectric constant.

Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.

Abstract: An animal deterrent device includes an elongated carrier having an internal cavity. A conductive trace can be coupled to the carrier by a first fastener that extends from the conductive trace to the cavity, which prevents water from contacting the fastener and shorting the conductive trace.

Abstract: The present invention provides a micropackaged device comprising: a substrate for securing a device; a corrosion barrier affixed to said substrate; optionally at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer configured to encapsulate the micropackaged device.

Abstract: A multilayer printed wiring board includes a core base material having a penetrating portion, a low-thermal-expansion substrate accommodated inside the penetrating portion of the core base material and having a first surface for mounting a semiconductor element and a second surface on the opposite side of the first surface, a first through-hole conductor provided inside the low-thermal-expansion substrate and provided for electrical connection between the first surface and the second surface of the low-thermal-expansion substrate, a filler filled in a gap between the low-thermal-expansion substrate and an inner wall of the core base material, and a wiring layer formed on at least one of the first surface and the second surface of the low-thermal-expansion substrate and having a resin insulation layer and a conductive layer. The wiring layer has a via conductor connecting the first through-hole conductor and the conductive layer.

Abstract: A method of manufacturing a circuit board includes: forming a first through hole in a core material; forming a first conductive film on an inner wall of the first through hole; forming an insulating layer on both surfaces of the core material and in the first through hole; forming a second through hole in the insulating layer in the first through hole; forming a second conductive film on an inner wall of the second through hole; and forming, on surfaces of the insulating layers formed on the both surfaces of the core material, a signal circuit layer electrically connected to the second conductive film.

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.

Abstract: A multilayer inductor device in which parasitic inductance is made smaller while preventing increase in a mounting area of the device and complexity of a wiring pattern, and a manufacturing method of the stated multilayer inductor device. An outer electrode and a terminal electrode are connected to each other through a via hole. A side surface of a non-magnetic member forms a part of an end surface of the device, while the other side surface thereof being in contact with the via hole. A side surface of the via hole that makes contact with the non-magnetic member is opened, which prevents the parasitic inductance from being increased. The via hole being provided in an arbitrary position makes it possible to prevent the wiring pattern from being complicated and a mounting area of the device from being increased.

Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.

Abstract: A high speed communication jack including a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug and a shielding case surrounding the housing. A flexible circuit board between the shielding case and the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, and a shielding plane on a second side of the substrate opposite the first side of the substrate.

Abstract: Methods of fabricating components for microelectronic devices are described herein. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. Bit line contact openings can be formed in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. A first conductive material is deposited into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. A conductive line is formed in a trench in the substrate. Dielectric features can electrically insulate the conductive line.

Abstract: A method for manufacturing a printed wiring board includes preparing a core substrate having a first surface and a second surface on the opposite side of the first surface, forming on the first-surface side of the substrate a first opening portion tapering from the first toward second surface, forming on the second-surface side of the substrate a second opening portion tapering from the second toward first surface, forming a third opening portion such that a penetrating hole formed of the first opening portion, the second opening portion and the third opening portion connecting the first and second opening portions is formed in the substrate, forming a first conductor on the first surface of the substrate, forming a second conductor on the second surface of the substrate, and filling a conductive material in the penetrating hole such that a through-hole conductor connecting the first and second conductors is formed.

Abstract: A circuit board includes a substrate and a through via. The substrate has a first surface and a second surface opposite to the first surface. The substrate includes circuit layers and insulation layers. The insulation layers are sandwiched between the circuit layers. The through via goes through the substrate and has portions defining a first portion and a second portion. The first portion of the through via is coated with a first metal layer and electrically connected to at least one of the circuit layer by the first metal layer. The second portion of the through via is coated with a second metal layer and electrically connected to at least one of the circuit layer by the second metal layer. The first and second portions are electrically insulted, and the diameter of the second portion is larger than that of the first portion.