Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration.

Abstract: A temperature coefficient factor circuit is provided which generates a current which varies with temperature according to a programmable temperature coefficient factor. The temperature coefficient factor circuit comprises a first current source providing a first current with a positive temperature coefficient factor, a second current source providing a second current with a negative temperature coefficient factor, a common terminal, a first programmable amplifying current mirror, a second programmable amplifying current mirror and a current output circuit. The first programmable amplifying current mirror provides in dependence of a control signal ctrl an amplified first current to the common terminal. The second programmable amplifying current mirror conducts away in dependence of the control signal ctrl an amplified second current from the common terminal. The current output circuit provides the output current based on a difference current between the amplified first current and the amplified second current.

Abstract: A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current.

Abstract: According to one embodiment, the semiconductor device includes a power-on reset circuit and a constant voltage generation circuit. The power-on reset circuit generates a power-on reset signal to initialize an internal circuit when power supply is turned on. The constant voltage generation circuit supplies an output voltage to the internal circuit. The constant voltage generation circuit includes a differential amplifier, a first MOS transistor, a second MOS transistor, a switch, and a pull-up unit. The pull-up unit is provided between the power supply input terminal and the gate terminal of the second MOS transistor. The pull-up unit controls a voltage applied to the gate terminal of the second MOS transistor in accordance with the power-on reset signal.

Abstract: A low input voltage low impedance termination stage for current inputs may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

Abstract: A reference voltage generator that does not require a start-up circuit or a feedback loop generates a proportional-to-absolute-temperature (PTAT) output voltage based on two complementary-to-absolute-temperature (CTAT) currents. The reference voltage generator provides a reference voltage that is a sum of the PTAT output voltage and a CTAT voltage.

Abstract: There is provided a switched-mode power supply including: a PWM control unit generating a clock signal having pulse widths of the clock depending on a load to provide a path switching signal; a clock counter counting the clock signal to generate a control signal; a current source generating a current; a current mirroring circuit unit having a plurality of upper side current mirroring units respectively mirroring the current from the current source to create a current having a predetermined amplitude; a first current adjusting unit individually selecting a portion of the plurality of upper side current mirroring units according to the control signal; and a path switching circuit unit switched according to the path switching signal so as to select a charging path between the first current adjusting unit and a power switch or a discharging path between the power switch and the ground.

Abstract: By arranging both a conductive and non-conductive resistive memory cell in a cross coupled arrangement to facilitate reading a data state the memory cells can have very small differences in their resistance values and still read correctly. This allows both of the memory cells' resistances to change over time and still have enough difference between their resistances to read the desired data state that was programmed. A pair of ReRAM or CBRAM resistive memory devices are configured as a one bit memory cell and used to store a single data bit wherein one of the resistive memory devices is in an ERASE condition and the other resistive memory devices of the pair is in a WRITE condition. Reading the resistance states of the resistive memory device pairs is accomplished without having to use a reference voltage or current since a trip-point is between the conductive states thereof.

Abstract: A reference voltage generating circuit with extremely low temperature dependence is provided. The reference voltage generating circuit includes a BGR circuit which generates a bandgap reference voltage; a bandgap current generating circuit which generates a bandgap current according to the bandgap reference voltage; a PTAT current generating circuit which generates a current proportional to the absolute temperature; and a linear approximate correction current generating circuit which compares the current generated by the PTAT current generating circuit and the bandgap current to generate a correction current, and the BGR circuit adds, to the bandgap reference voltage, a correction voltage generated based on the correction current.

Abstract: An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage.

Abstract: A fast startup circuit delivers current to a number of loads, comprising a P-channel current mirror circuit that provides current to an N-channel current mirror circuit that distributes current to a plurality of circuit networks. A first capacitor and a second capacitor are charged to two different voltages when the circuit is disabled and the two voltages are equalized when the circuit is enabled creating an initial operational starting point that has a steady state operating voltage that is the same as that during continuous operations. Thus there is no waiting for the fast startup circuit to start from an off condition and build up exponentially to a steady state operational level.

Abstract: The present disclosure provides a varying high voltage source implemented with low voltage domain electronic components that are less costly to manufacture. According to one aspect, the present disclosure provides a high voltage circuit apparatus comprising a pull up resistance module, a plurality of cascode cell stages, a first of the cascode cell stages being coupled to the pull up resistance module, a low voltage domain current sink module coupled to a last of the cascode cell stages, and a clamping voltage source coupled to the last of the cascode cell stages. The circuit apparatus is devoid of high-voltage transistor components.

Abstract: An electronic circuit for providing a voltage or a current linearly dependent on temperature within a temperature range, including at least two identical MOS transistors conducting the same drain current, each transistor having a fully depleted channel which is separated from a doped semiconductor region by an insulating layer, the conductive types of the dopants of said doped semiconductor regions being different, said voltage or said current being proportional to the difference between the gate-source/drain voltages of the two transistors.

Abstract: Methods and apparatuses are disclosed for generating an adjustable bias current. The value of the adjustable bias current may be determined based in part on an error signal representative of a difference between an actual output value and a desired output value of a power converter. When the error signal is below a lower threshold voltage, the adjustable bias current may be set to a first value. When the error signal is above an upper threshold voltage, the adjustable bias current may be set to a second, higher value. When the error signal is between the lower threshold voltage and the upper threshold voltage, the adjustable bias current may change linearly with the error signal.

Abstract: Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.

Abstract: Aspects of the disclosure provide a circuit that can include a depletion mode transistor coupled to a power source and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. Further, a gate terminal of the depletion mode transistor is coupled to a clamping path that includes a diode and a switch that connected in series. The clamping path clamps the voltage at the gate terminal of the depletion mode transistor to the capacitor. The clamping and the current paths respectively have a first resistance during a first stage, such as when the circuit initially receives power, and have a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.

Abstract: A boosting circuit, a backlight driving circuit and a backlight module are provided. The boosting circuit comprises a boosting chip (U1), an energy-storage inductor (L1), a freewheeling diode (D1), a first capacitor (C1), and a current mirror unit (U2), wherein an input terminal of an inputting branch of the current mirror unit (U2) IS connected with the cathode of the freewheeling diode (D1), and an output terminal of the inputting branch is connected with the signal input terminal (Vin) of the boosting circuit through a first resistor (R1), an input terminal of an outputting branch of the current mirror unit (U2) IS connected with the cathode of the freewheeling diode (D1), an output terminal of the outputting branch is grounded through a second resistor (R2), an ungrounded terminal of the second resistor (R2) is connected with a signal feedback pin of the boosting chip.

Abstract: There is provided a voltage regulator equipped with a reverse-current prevention function capable of ensuring safe performance without causing a large overshoot at an output terminal against a sharp fluctuation in source voltage. The voltage regulator provides a source voltage fluctuation detecting circuit for detecting a fluctuation in source voltage in a comparison circuit for comparing the source voltage with output voltage so that when the source voltage rises sharply, the current through constant current circuits for limiting the consumption current of the comparison circuit will be increased to improve the response characteristics.

Abstract: Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.

Abstract: This document discusses apparatus and methods for a boost converter start-up circuit. In an example, a start-up circuit can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter. The linear current generator can include a modified current mirror and a feedback circuit configured to provide a first representative of an output voltage of the output terminal to an input of each of a first and a second adjustable current source of the modified current mirror.

Abstract: A push-pull amplifier has an input node and a series connection of two resistors. The series connection comprises a first terminal, a second terminal, and a third terminal. A first resistor of the two resistors is connected between the first terminal and the second terminal. A second resistor is connected between the second and third terminals. The input node is connected to the second terminal. A first controllable current source is connected to the first terminal of the series connection for sourcing a first current to the series connection. A second controllable current source is connected to the third terminal of the series connection for sinking a second current from the series connection. A first transistor and a second transistor are connected in push-pull configuration, wherein a control input of the first transistor is connected to the first terminal of the series connection and a control input of the second transistor is connected to the third terminal of the series connection.

Abstract: A voltage regulation circuit and method where a pre-charge device (PCD) and a power gate device (PGD) are connected to a voltage line that supplies power to at least one additional device. The PCD pre-charges the line toward a supply voltage (Vdd) and PGD limits voltage changes on the voltage line caused by leakage current in the additional device(s) and does so differently under different leakage conditions. Specifically, the PGD is controlled by a variable reference voltage (Vref), which is closer to Vdd when a leakage condition is low relative to when the leakage condition is high. Since Vref is relatively high when the leakage condition is low and relatively low when the leakage condition is high, the power gate device will turn on after a smaller amount of voltage change on the voltage line when the leakage condition is low as compared to when the leakage condition is high.

Abstract: Disclosed herein is a differential amplifier circuit that includes: first and second transistors coupled to form a differential circuit; a first current mirror circuit generating first and second currents in response to a third current flowing through the first transistor; and a second current mirror circuit generating a fourth current in response to a fifth input current. A sum of the second and fourth currents flowing through the second transistor.

Abstract: A voltage detection circuit includes a voltage detection unit suitable for comparing a voltage level of a reference voltage terminal with a voltage level of an internal voltage terminal and for generating a detection signal based on a comparison result, a test reference voltage generating unit suitable for receiving an external reference voltage through a pad and for supplying a test reference voltage, which is generated by using the received external reference voltage, to the reference voltage terminal by using a first input resistance, during a test operation, and a normal reference voltage generating unit having a current mirror structure, wherein the normal reference voltage generating unit is suitable for supplying a current, corresponding to an internal reference voltage, to the reference voltage terminal by using a second input resistance different from the first input resistance, during a normal operation.

Abstract: A bidirectional current sensor circuit can be configured to generate a scaled version of a load current using a first transistor from a power regulator output stage and a second transistor that can be a mirror or scaled version of the first transistor. A trim circuit can be provided to correct gain errors under current sinking or current sourcing conditions. In an example, the bidirectional current sensor circuit can be configured to detect a polarity or a magnitude of a current signal that is used to operate a thermoelectric device.

Abstract: A current generator includes first and second current generators and an output current generator. The first current generator has an output for providing a first current, the first current proportional to a difference between a first power supply voltage and a first gate-to-source voltage. The second current generator has an output for providing a second current, the second current proportional to a second gate-to-source voltage. The second gate-to-source voltage is approximately equal to the first gate-to-source voltage. The output current generator provides an output current proportional to a sum of said first current and said second current.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: Provided is a constant current circuit in which an enhancement N-channel transistor can operate in a weak-inversion state even at high temperatures. A constant current circuit includes a current mirror circuit, a constant-current generation block circuit, and an off-leak circuit, wherein the off-leak circuit is constituted by a first enhancement N-channel transistor having a gate and a source connected to an earth terminal and a drain connected to an output of the constant current circuit. This suppresses an increase in a gate-to-source voltage of the enhancement N-channel transistor which generates a constant current, thereby maintaining its operation in a weak-inversion state.

Abstract: Systems and methods are provided for a power supply. A first output stage is configured to supply power from a power source at a target voltage to a device in an integrated circuit in response to a power demand of the device. Load detector circuitry is configured to detect a load resulting from operation of the device, and a supplemental output stage is configured to selectively supply supplemental power from the power source to the device, in addition to the power provided by the first output stage, in response to detection of an additional load resulting from operation of the device.

Abstract: A switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.

Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.

Abstract: A voltage generator is disclosed. The voltage generator includes an operational amplifier, an offset voltage tuner, and an output stage circuit. The operational amplifier receives an input voltage and adjusts an offset voltage of the operating amplifier according to a control signal. The offset voltage tuner provides the control signal. The output stage circuit generates an output voltage according to a voltage on an output terminal of the operational amplifier, and provides the output voltage to the operational amplifier.

Abstract: A current output circuit includes a current mirror circuit that has first and second transistors in each of which a source is connected to a reference voltage, and that outputs a current which is proportional to a drain current of the first transistor, from a drain of the second transistor; a switch that turns ON/OFF the current output of the current mirror circuit; a third transistor in which a gate is connected to a gate of the second transistor; and a bias circuit that applies a first voltage to a drain of the third transistor. The bias circuit switches the first voltage to two different voltages in synchronization with opening/closing of the switch.

Abstract: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.

Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.

Abstract: A voltage regulator circuitry (50) adapted to operate in a high-temperature environment of a turbine engine is provided. The voltage regulator may include a constant current source (52) including a first semiconductor switch (54) and a first resistor (56) connected between a gate terminal (G) and a source terminal (S) of the first semiconductor switch. A second resistor (58) is connected to the gate terminal of the first semiconductor switch (54) and to an electrical ground (64). The constant current source is coupled to generate a voltage reference across the second resistor 58. A source follower output stage 66 may include a second semiconductor switch (68) and a third resistor (58) connected between the electrical ground and a source terminal of the second semiconductor switch. The generated voltage reference is applied to a gating terminal of the second semiconductor switch (58).

Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.

Abstract: A control circuit includes: a first current generating circuit arranged for generating at least one output current according to a reference signal; a second current generating circuit arranged for generating a reference current corresponding to the reference signal according to the reference signal; and a follower circuit coupled to the second current generating circuit for generating a control current according to the reference current, and feeding back the control current to the first current generating circuit from the second current generating circuit in a signal-following manner to control the reference signal.

Abstract: An electronic circuit includes a functional circuit in series with at least one first current source between two terminals of application of a power supply voltage. The first current source is controllable between an operating mode where it delivers a fixed current, independent from the power consumption of said functional circuit, and an operating mode where it delivers a variable current, depending on the power consumption of the functional circuit.

Abstract: A reference voltage generator includes a constant voltage generator suitable for using a high voltage as a first power supply voltage and for generating a constant voltage, and a first reference voltage generating unit suitable for using the constant voltage as a second power supply voltage and for generating a first reference voltage.

Abstract: Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.

Abstract: A driving device comprises a first transistor (B13), a second transistor (B14), and a resistance element. The first transistor (B13) has one terminal receiving a pulsed current and a control terminal connected to the one terminal. The second transistor (B14) has one terminal connected to at least one load, the other terminal connected to a reference potential together with the other terminal of the first transistor (B13), and a control terminal connected to the control terminal of the first transistor (B13). The resistance element is connected between the control terminal of the first transistor (B13) and the other terminal of the first transistor (B13).

Abstract: An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET.

Abstract: A constant current flowing through a first depletion transistor whose gate and source are connected to each other is caused to flow through a second depletion transistor having the same threshold as the first depletion transistor, to thereby generate a first voltage between a gate and a source of the second depletion transistor. The constant current of the first depletion transistor and a constant current flowing through a third depletion transistor whose gate and source are connected to each other are caused to flow through a fourth depletion transistor. A threshold of the fourth depletion transistor is the same as that of the third depletion transistor but different from that of the first depletion transistor, and hence a second voltage is generated between a gate and a source of the fourth depletion transistor. A reference voltage is generated based on a voltage difference between the first and second voltages.

Abstract: An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device.

Abstract: A regulator for providing a plurality of output voltages is provided. The regulator includes a basic unit and a plurality of replica units. The basic unit amplifies an input voltage to obtain a core voltage according to a first control signal. Each of the replica units outputs one of the output voltages according to the input voltage and one of a plurality of second control signals, wherein at least two of the output voltages have different voltage levels. The first control signal is set according to the second control signals, to make the voltage level of the core voltage substantially equal to or less than a maximum voltage level of the output voltages and substantially equal to or greater than a minimum voltage level of the output voltages.

Abstract: A circuit includes a first current path comprising a first floating-gate transistor having a programmable threshold voltage, a second current path, and a differential amplifier. The second current path includes a second floating-gate transistor having a programmable threshold voltage and a resistor. The differential amplifier includes a first input coupled to the first current path, a second input coupled to the second current path, and an output configured to control a reference current path.

Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.

Abstract: A reference current output device and reference current output method that may adjust a reference current while maintaining a temperature gradient. In the reference current output device and reference current output method of the present invention, a reference current is outputted by a reference voltage and current output circuit, a reference voltage outputted from the reference voltage and current output circuit is converted to an adjustment current and outputted by a conversion and output circuit, the adjustment current is superimposed with the reference current and a superimposed current is outputted by a superimposition and output section.