Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: A sensor for sensing a parameter includes a control circuit that outputs a clock signal, a converter that receives the clock signal, generates a parameter-dependent voltage, and outputs an output voltage based on a comparison of the parameter-dependent voltage to a reference voltage. The sensor also includes a filter that receives the output voltage and counts a number of pulses of the clock signal based on a level of the output voltage.

Abstract: A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.

Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).

Abstract: In accordance with an embodiment, a proportional to absolute temperature (PTAT) circuit includes a first bipolar transistor having a collector coupled to a common node; a second bipolar transistor having a collector coupled to the common node; a MOSFET having a load path coupled between a base of the first bipolar transistor and a base of the second bipolar transistor; and an amplifier having a first input coupled to an emitter of the first bipolar transistor, a second input coupled to an emitter of the second bipolar transistor and an output coupled to a gate of the MOSFET.

Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.

Abstract: A pixel driving circuit includes a first transistor receiving a data signalsame. A first end of a second transistor is connected to the first end of the first transistor, and a gate of the same is connected to a second end of the second transistor. A second end of a third transistor is connected to the second end of the second transistor. A first end of a fourth transistor is connected to the gate of the first transistor. A second end of a fifth transistor is connected to the first end of the first transistor. A first end of the sixth transistor is connected to a second end of the first transistor. An anode of a light emitting diode is connected to a second end of the sixth transistor. A capacitor is connected between the first end and the gate of the first transistor.

Abstract: According to an embodiment, a power source circuit has first, second, and third one-conductivity-type transistors with commonly connected emitters, wherein the first transistor has an emitter area that is N times those of the second and third transistors. The power source circuit outputs a reference voltage that is set by a voltage drop that is caused at a resistance between bases of the first and second transistors and a forward voltage of a PN-junction diode, and outputs a BG_OK signal in response to a potential at a collector of the third transistor.

Abstract: In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.

Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.

Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power.

Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.

Abstract: Systems and devices are provided for generating a process, voltage, temperature (PVT)-independent reference current for a relatively low voltage domain. An apparatus may include a bandgap circuit that outputs a bandgap voltage and a first proportion-to-absolute temperature (PTAT) current. The apparatus may also include trimming circuitry that outputs a reference a voltage based at least in part on the bandgap voltage. Further, the apparatus may include reference current generation circuitry. In particular, the reference current generation circuitry may include a complementary-to-absolute-temperature (CTAT) current generation portion that generates a CTAT current based on the reference voltage as well as a PTAT current tuning portion that tunes a received first PTAT current to generate a second PTAT current.

Abstract: A bias generator and a method for generating a bias voltage are presented. The bias generator is for use with an electronic circuit comprising a first switch coupled in series with a second switch. The bias generator is adapted to generate a reference voltage, a first bias voltage, and a second bias voltage. The second bias voltage is based on the reference voltage. After applying the first voltage to the first switch and the second voltage to the second switch, the bias generator controls a voltage across the first switch. The bias generator may be adapted to set a value of the reference voltage to control the voltage across the first switch. For instance, the reference voltage may be set to a fix value so that the voltage across the first switch is maintained at a constant value.

Abstract: An apparatus for controlling electric current includes a power supply for supplying a voltage, a driving circuit for receiving the voltage from the power supply to supply a first current to a load electrically connected thereto, and a control circuit electrically connected to the load and the driving circuit and for receiving the voltage from the power supply to supply a second current to the load.

Abstract: In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.

Abstract: A driver port that provides selectable output currents based on connections thereto, and a driver including the same, is provided. A plurality of shunt resistors are connected in series between a negative output of a driver and a ground. A driver port having a plurality of connection points is provided, each respective connection point connected to a different connection between two of the plurality of shunt resistors. A load including one or more solid state light sources is capable of being connected between one of the connection points of the driver port and a positive output of the driver.

Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: A power stage output node stabilizer may be used to reduce ringing of a power stage output node of a switching DC-DC power converter. The power stage output node stabilizer may be a network of resistors and switches coupling the power stage output node to a higher voltage level and a lower voltage level.

Abstract: A circuit and a method using a pass device that is coupled between a supply voltage level and a load-connectable node of the circuit for providing a load current. A sense device forms a current mirror with the pass device. The sense device has transistor devices that can be switched to an active state, to adjust a mirror ratio of the current mirror. A first feedback loop regulates a voltage drop across the pass device to a predetermined value. A second feedback loop regulates a voltage drop across the sense device to the voltage drop across the pass device. Measurement circuitry sets a mirror ratio of the current mirror based on an indication of a current flowing through the sense device and generates an indication of current flowing through the pass device based on the set mirror ratio and the indication of the current flowing through the sense device.

Abstract: A system includes a trickle charge control circuit coupled to a charge pump and a motor driver circuit. The trickle charge control circuit is configured to sense a voltage at a bootstrap capacitor voltage node (VBST) of the motor driver circuit; as a result of the voltage at VBST being greater than a voltage at an input voltage node (VIN), couple a charge pump voltage node (VCP) to VBST of the motor driver circuit, where a voltage at VCP is greater than the voltage at VIN; and as a result of the voltage at VBST being less than the voltage at VIN, decouple VCP from the charge pump from VBST of the motor driver circuit.

Abstract: A gate driver circuit for driving a power switch includes a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver providing a primary gate current and an auxiliary gate current, and a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a power supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to a second input of the gate driver.

Abstract: A device for providing an activation voltage for a safety unit for a vehicle. The device includes a supply terminal for applying a first supply voltage potential, an activation terminal for outputting the activation voltage, and a control terminal for reading in a control signal. In addition, the device includes a pass-through switch that is connected between the supply terminal and the activation terminal, a first control switch, a second control switch, and a third control switch that includes a control input that is connected to the control terminal.

Abstract: According to one embodiment, a voltage-current conversion circuit includes an amplifier first, second and third inputs, a transistor including a first and second terminals, and a control terminal electrically connected to an output of the amplifier, and a serial connection including resistors connected in series between the first terminal and an ac ground, wherein a predetermined connecting point, among a first connecting point between the first terminal and the serial connection, a second connecting point between the ac ground and the serial connection, and one or more third connecting points between the resistors, is connected to the second input, and one of the connecting points other than the predetermined connecting point is connected to the third input.

Abstract: A current reference circuit and a semiconductor IC including the current reference circuit, the current reference circuit including a proportional to absolute temperature (PTAT) current generator configured to generate, in an output branch, a first current proportional to a temperature; and a current subtractor configured to generate a reference current by subtracting a second current generated based on a current flowing in an internal branch of the PTAT current generator, from the first current flowing in the output branch. The second current is set to have a same temperature-based change characteristic as the first current and a level different from a level of the first current.

Abstract: A circuit includes a startup circuit to provide a charging signal to initiate startup of a reference circuit. The startup circuit includes a detector circuit having a detector current path control, a level shifter having a level shifter current path control, and a charger circuit having a charger current path control. Each of the detector current path control, the level shifter current path control, and the charger circuit current path control enable current flow in the startup circuit when the charger turn-on signal is in the on-state and disable the current flow in the startup circuit when the charger turn-on signal is in the off state.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*ln(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VT*ln(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: An apparatus and method for a voltage reference circuit with flexible and adjustable voltage settings. A voltage reference circuit, comprising a PTAT Current Generator configured to provide current through a first resistor, a CTAT Current Generator configured to provide a CTAT current through a second resistor, a PTAT-CTAT Adder circuit configured to sum the PTAT current, and the CTAT current, wherein said sum of the PTAT and CTAT current through a third resistor is configured to provide an output voltage greater than a silicon bandgap voltage.

Abstract: A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).

Abstract: An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.

Abstract: An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S/D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.

Abstract: A non-volatile semiconductor memory device includes a current source providing a reference current to a first node and a clamp circuit. The clamp circuit includes a transistor having a current path between the first node and a second node, and an amplifier circuit having a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the transistor. The amplifier circuit is configured to output a differentially amplified signal from the output port. A memory cell is connected between a bit line and a word line and includes a variable resistance element. The bit line can be connected to the second node. A sense amplifier is connected to the first node to detect data stored in the memory cell.

Abstract: A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells. The converter includes a plurality of current sense circuits for sensing current in a respective converter cell, each of the current sense circuits configured to generate a respective current sense signal, an averaging circuit for receiving each of the respective current sense signals and generating an average signal, a plurality of imbalance detector circuits for comparing a respective current sense signal with the average signal and generating a respective current imbalance signal, and a plurality of ON time generators for activating a converter cell for a predetermined time interval and altering the predetermined time interval in accordance with a time integral of a respective current imbalance signal.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: A circuit for providing a current flowing from a supply voltage into an electric load is presented. The circuit comprises a first circuit branch connected between the supply voltage and an output node connected to the electric load, wherein the first circuit branch comprises a first transistor device, a second circuit branch connected between the supply voltage and a predetermined voltage level, wherein the second circuit branch comprises a series connection of a second transistor device that is a scaled replica of the first transistor device and a current source. The control terminals of the first and second transistor devices are connected to each other. A control circuit is configured to control the voltage at the control terminal of the first transistor device depending on a current flowing through the first transistor device. The application further relates to a method of operating such circuit.

Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.

Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.

Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.

Abstract: Examples provide a series of heaters supported at different depths within the volume. A series of temperature sensors is supported at different depths within the volume. The temperature sensors output signals indicative of dissipation of heat from the heaters to indicate a level of the liquid within the volume.

Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.

Abstract: Generally, this disclosure provides circuitry and methods for determining the output capacitance of an output load capacitor of a power supply. The output capacitance is generally determined by beginning a calibration period and charging an output capacitor with a current source to generate an output voltage. The output voltage may be compared to a reference voltage, and a time period is determined during which the output voltage is less than the reference voltage. The capacitance value, C, of the output capacitor may be determined based on, at least in part, the determined time period. This disclosure also provides circuitry and methods to adjust certain parameters of the power supply based on the determined C value. For example, in a ramp compensation portion of the power supply, the value of a ramp capacitor and/or reset resistor may be adjusted once the value of C is determined.

Abstract: Current mirror devices and methods for operating a current mirror device. The current mirror device includes a first transistor having a gate, a source, a drain, and a back gate. The drain and the gate of the first transistor are coupled to an input node of the current mirror device. The current mirror device further includes a second transistor having a gate, a source, a drain, and a back gate. The drain of the second transistor is coupled to an output node of the current mirror device, and the gate of the second transistor is coupled to the gate of the first transistor and to the input node. A voltage source supplies a bias voltage to the back gate of the first transistor that adjusts a threshold voltage of the first transistor and to the back gate of the second transistor that adjusts a threshold voltage of the second transistor.

Abstract: A current flattening circuit, a current compensation circuit and associated control method are provided. The current flattening circuit is electrically connected to a core node, and includes a reference voltage regulator and the current compensation circuit. The reference voltage regulator generates a reference voltage, wherein the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator. The current compensation circuit generates a compensation current according to a potential difference between the reference voltage and a core voltage corresponding to the core node.

Abstract: A solid state relay and a method for controlling a signal path between an AC-signal output and a load in a power amplifier assembly are disclosed. The relay comprises a first and a second MOSFET having a common gate junction, a common source junction and wherein and wherein a drain terminal of a first MOSFET and a drain terminal of a second MOSFET form relay terminals. The solid state relay further comprises a control circuit comprising a positive side comprising a first controlled current generator configured to provide a first control current to the gate junction, and a negative side comprising a current mirror circuit configured to sink a second current from the source junction. Hereby, a generic solid state speaker relay has been disclosed. The relay performs up to the most stringent demands regarding pop/click on high quality products. It can be used to ground wire break, hot wire break and BTL (Bridge Tied Load) break.

Abstract: An electronic circuit includes a plurality of current-mirror devices, which are physically laid-out in an array and are configured to receive a digital word, to further receive a reference current, and to convert the digital word into an output current by mirroring the reference current. The current-mirror devices include (i) first current-mirror devices, which are laid-out along a perimeter of the array and are configured to generate a fixed baseline component of the output current that is independent of the digital word, and (ii) second current-mirror devices, which are laid-out in an interior of the array and are configured to generate a programmable component of the output current that depends on the digital word.

Abstract: The invention relates to a method and a device for detecting a current in a measuring path, the current in said measuring path corresponding to a current in a power path. An electric current is detected by a current measuring instrument in the measuring path, while simultaneously part of the electric current is conducted parallel to the current measuring instrument by a bypass device, in order to reduce the load on the current measuring instrument.

Abstract: A zero-crossing detection circuit for a trailing edge phase control dimmer circuit for controlling alternating current (AC) power to a load, wherein the circuit includes: a switching circuit for controlling delivery of AC power to the load by conducting power to the load in an ON state and not conducting power to the load in an OFF state; a switching control circuit for controlling turn-OFF and turn-ON of the switching circuit at each cycle of the AC; and a rectifier for rectifying the AC power in the non-conduction period to generate rectified dimmer voltage to be provided to the dimmer circuit, wherein the zero-crossing detection circuit includes a current sink circuit; wherein the current sink circuit has a low impedance at low instantaneous AC voltages; a comparator circuit configured to detect zero crossings of a first threshold value of the rectified dimmer voltage.

Abstract: A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.

Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.