Including A Particular Probing Technique (e.g., Four Point Probe) Patents (Class 324/715)
  • Patent number: 11125805
    Abstract: A device is provided for electrically measuring surface characteristics of a sample. The device comprises at least one group of three electrodes: a first and second electrode spaced apart from each other and configured to be placed onto the surface of the sample, and a third electrode between the first two but isolated from these two electrodes by a one or more first insulators, wherein a second insulator further isolates the central electrode from the sample when the device is placed thereon. The three electrodes and the insulators are attached to a single or to multiple holders with conductors incorporated therein for allowing the coupling of the electrodes to power sources or measurement tools. The placement of the device onto a semiconductor sample creates a transistor with the sample surface acting as the channel. The device thereby allows the determination of the transistor characteristics of the sample in a straightforward way.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 21, 2021
    Assignee: IMEC vzw
    Inventors: Kristof Paredis, Umberto Celano, Wilfried Vandervorst
  • Patent number: 10852343
    Abstract: Apparatuses of a noise measurement system and methods for using the same are disclosed. In one embodiment, a noise measurement system may include a plurality of probe groups electrically coupled to a plurality of DUTs, where a probe group in the plurality of probe groups includes multiple channels, and where the multiple channels of each probe group are bundled as a group for reducing electromagnetic interference among the plurality of probe groups, and wherein the group is shielded from corresponding signal groups of other DUTs with a connection to a circuit ground of the noise measurement system for reducing ground loop generated signal interference. The noise measurement system may further include a controller configured to perform noise measurement.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 1, 2020
    Assignee: PROPLUS ELECTRONICS CO., LTD.
    Inventor: Zhihong Liu
  • Patent number: 10739413
    Abstract: The disclosure relates to a method for monitoring the performances of a cable for carrying a downhole assembly in a wellbore, the cable having at least a conductive core and an insulating outer layer, the method including: performing on the cable a detection operation for detecting the presence of local anomalies of the cable; generating an electrical model of a predetermined configuration of an installation including the cable and the downhole assembly disposed in the wellbore, the model being defined in function of the detected local anomalies, estimating a parameter relative to a signal transmitted by the cable between the downhole assembly and a surface equipment in the predetermined configuration on the basis of the electrical model.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 11, 2020
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: François Chevillard, Fabio Cecconi
  • Patent number: 10690733
    Abstract: A magnetic image sensor is provided. The magnetic image sensor includes: a magnetic resistance (1), arranged along a scanning direction and configured to detect a changed magnetic signal in a range to be detected; a configuration resistance (2), connected with the magnetic resistance (1), wherein a resistance value of the configuration resistance (2) is adjustable; and a driving circuit (3), connected with the magnetic resistance (1) and configured to perform output control on the changed magnetic signal detected by the magnetic resistance (1) The problem of relatively stronger noise signal caused by a magnetic resistance deviation of a magnetic image sensor is solved.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: June 23, 2020
    Assignee: WEIHAI HUALING OPTO-ELECTRONICS CO., LTD.
    Inventors: Wuchang Qi, Mingfeng Sun
  • Patent number: 10634732
    Abstract: A system and method verifies continuity with and measures voltage across a circuit under test (in some instances simultaneously) using two or more test probes. Two or more probe continuity circuits measure continuity through the test probes by injecting a test current through and measuring a processed test current received at each of the plurality of test probes. The probe continuity circuits measure the respective processed test current rendered by the test current flowing through the test circuit at each test probe. A voltmeter measures the potential difference across the test probes.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 28, 2020
    Assignee: UT-Battelle, LLC
    Inventors: Robert J. Warmack, Milton Nance Ericson, Roger A. Kisner, Yarom Polsky
  • Patent number: 10547272
    Abstract: A diagnostic device (40) having layers (25, 27, 29) corresponding to respective layers (24, 26, 28) of a given photovoltaic module (20). The diagnostic device is provided for testing and monitoring a condition of the given photovoltaic module. The layers of the diagnostic device may be made of respective materials with the same or substantially the same electrical resistance and aging characteristics as the respective layers of the given photovoltaic module under operational conditions. Electrodes (42, 44, 50A-C, 52A-C, 54A-C) of the diagnostic device are configured to independently measure electrical resistance along at least two different current resistance paths in the diagnostic device corresponding to respectively different current leakage paths (R1, R?1, R2-4, R5, R5) of the given photovoltaic module.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: January 28, 2020
    Assignee: Episolar, Inc.
    Inventors: Neelkanth G. Dhere, Ramesh G. Dhere, Narendra S. Shiradkar, Eric Schneller
  • Patent number: 10429420
    Abstract: A system for measuring and mapping sheet resistivity of the film on flat-panel has a frame, a collection of leveling chucks, a probe-mounting assembly, and a collection of four-point probes. The probe-mounting assembly is a frame that holds the four-point probes in place. The leveling chucks and the probe-mounting assembly are mounted onto the frame, within the probe chamber. The flat panel is positioned in between the probe-mounting assembly and the leveling chucks. The sheet resistivity measurement by each of the collection of four-point probes can be done by electrical switching instead of mechanical repositioning and the flat panel transportation to and from the measurement position only needs to be done in one round trip instead of two, thus much time is saved. Also, the leveling chuck's speed in pressing the flat panel against the collection of four-point probes can be well controlled to avoid damaging of the flat panel.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: October 1, 2019
    Inventor: James Chen
  • Patent number: 10303822
    Abstract: Systems and methods of designing geometry of a tool set in a numerical simulation of sheet metal forming operations including springback compensation are disclosed. Computerized die face model representing an initial geometry of a tool set is generated for forming a sheet metal work-piece to a part's desired geometry. Numerically-simulated deep drawing operation, optional trimming operation and a springback effect are conducted to obtained a trial geometry of the part. A deviation between the trial geometry and the desired geometry is obtained. When the deviation is outside of tolerance, computerized die face model is regenerated according to a modified geometry of the tool set that includes an estimated amount of springback compensation derived from the deviation due to springback together with a node adjustment scheme for ensuring model conformity along the boundary line. Final modified geometry of the tool set is iteratively obtained.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Livermore Software Technology Corp.
    Inventors: Xinhai Zhu, Li Zhang
  • Patent number: 9772423
    Abstract: A method of imaging electrical conductivity distribution of a subsurface containing metallic structures with known locations and dimensions is disclosed. Current is injected into the subsurface to measure electrical potentials using multiple sets of electrodes, thus generating electrical resistivity tomography measurements. A numeric code is applied to simulate the measured potentials in the presence of the metallic structures. An inversion code is applied that utilizes the electrical resistivity tomography measurements and the simulated measured potentials to image the subsurface electrical conductivity distribution and remove effects of the subsurface metallic structures with known locations and dimensions.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 26, 2017
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventor: Timothy C. Johnson
  • Patent number: 9632048
    Abstract: The present disclosure relates to a sheet resistance measuring method, comprising the following steps: connecting at least one to-be-measured thin film having a predetermined shape to two separate electrodes in at least one pair of electrodes; measuring the resistance between the two electrodes in each pair of electrodes; and determining the sheet resistance of the to-be-measured thin film based on the measured resistance and the shape of the corresponding to-be-measured thin film.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 25, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shi Shu, Bing Sun, Bin Zhang, Kexin Lu, Yue Shi, Zhijun Lv
  • Patent number: 9627280
    Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
  • Patent number: 9513327
    Abstract: Devices and methods for testing the operation of acoustic devices such as ultrasonic probes. The disclosed devices and methods identify failures of individual piezoelectric elements of various types of ultrasonic probes free of family-specific adapters to interface with such probes and free of acoustic coupling fluids or the like to establish acoustic coupling with the probes. In one arrangement, a testing appliance is disclosed that includes a testing unit and first and second probes electrically connected thereto. After an operator has established electrical connections between the first probe and a first contact of a connector assembly of the acoustic probe and between the second probe and a ground return path of the connector assembly, the testing device may pass a current through an electric circuit between the first and second probes and determine one or more corresponding electrical quantities of the circuit for establishing statuses of the probe.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 6, 2016
    Assignee: Acertara Acoustic Laboratories LLC
    Inventors: James Gessert, G. Wayne Moore
  • Patent number: 9374003
    Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: June 21, 2016
    Assignee: Volterra Semiconductor LLC
    Inventors: Michael D. McJimsey, David B. Lidsky, Andrew Burstein, Giovanni Garcea, Jeremy M. Flasck, Ilija Jergovic, Andrea Pizzutelli
  • Patent number: 9322844
    Abstract: A probe card 10 includes a first probe 11 configured to come into electric contact with an emitter electrode of a power device D; a block-shaped first connecting terminal 12 to which the first probe 11 is connected; a second probe 13 configured to come into electric contact with a gate electrode of the power device D; a block-shaped second connecting terminal 14 to which the second probe 13 is connected; a contact plate 15 configured to come into electric contact with a collector electrode of the power device D; and a block-shaped third connecting terminal 16 fixed to the contact plate 15. Further, the first connecting terminal 12, the second connecting terminal 14 and the third connecting terminal 16 electrically come into direct contact with corresponding connection terminals of a tester, respectively.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 26, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Shinohara, Ikuo Ogasawara, Ken Taoka
  • Patent number: 9170273
    Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Terence L. Kane, Matthew F. Stanton, Michael P. Tenney
  • Patent number: 9030216
    Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
  • Patent number: 9018958
    Abstract: An apparatus for measuring electrical parameters for an electrical system measures a first and second parameters of the electrical system between connections to the electrical system. A processor determines a third electrical parameter of the electrical system as a function of the first parameter and the second parameter. Wireless communication is provided between components of the apparatus.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 28, 2015
    Assignee: Midtronics, Inc.
    Inventor: Kevin I. Bertness
  • Patent number: 9013197
    Abstract: A chip on glass substrate includes a substrate, first, second, and third pads that are arranged on the substrate and that are electrically connected to an IC device, and first to fourth conductive patterns. A first conductive pattern is arranged on the substrate, has one end electrically connected to the first pad, and has another end that is electrically floated. Second and third conductive patterns are arranged on the substrate, each have one end electrically connected to the second pad, and each have another end that is electrically floated. A fourth conductive pattern is arranged on the substrate, has one end electrically connected to the third pad, and has another end that is electrically floated.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 21, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee
  • Patent number: 8970238
    Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 3, 2015
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Douglas J. Garcia
  • Patent number: 8914249
    Abstract: A resistance measuring apparatus includes: a voltage injector that injects an AC signal into a circuit by applying an AC voltage to an injection coil; a current measuring unit that measures an AC current produced in the circuit by the injection coil using a detection coil; a processing unit that calculates the circuit resistance from the AC signal voltage and the measured AC current; and a reference signal generator that outputs a binary reference signal that has a same period as the AC voltage and is synchronized to the clock. The voltage injector generates a stepped wave whose amplitude changes in synchronization with a clock, applies a signal based thereon as the AC voltage. The current measuring unit converts the current in the detection coil to a voltage signal, carries out synchronous detection using the reference signal, and measures the AC current based on the synchronous detection result.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: December 16, 2014
    Assignee: Hioki Denki Kabushiki Kaisha
    Inventor: Satoshi Imaizumi
  • Patent number: 8907690
    Abstract: A method of obtaining an electrical property of a test sample, comprising a non-conductive area and a conductive or semi-conductive test area, by performing multiple measurements using a multi-point probe. The method comprising the steps of providing a magnetic field having field lines passing perpendicularly through the test area, bringing the probe into a first position on the test area, the conductive tips of the probe being in contact with the test area, determining a position for each tip relative to the boundary between the non-conductive area and the test area, determining distances between each tip, selecting one tip to be a current source positioned between conductive tips being used for determining a voltage in the test sample, performing a first measurement, moving the probe and performing a second measurement, calculating on the basis of the first and second measurement the electrical property of the test area.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: December 9, 2014
    Assignee: Capres A/S
    Inventors: Dirch H. Petersen, Ole Hansen
  • Patent number: 8890552
    Abstract: A flyback converter includes a transformer to convert an input voltage into an output voltage, a control circuit senses a primary current of the transformer to generate a current sense signal, and a sensing circuit is configured to sense a variation of the current sense signal between two time points for extracting the input voltage information therefrom.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: November 18, 2014
    Assignee: Richtek Technology Corp.
    Inventors: Pei-Lun Huang, Kuang-Ming Chang
  • Patent number: 8829930
    Abstract: An apparatus and method of testing electrical impedance of a multiplicity of regions of a photovoltaic surface includes providing a multi-tipped impedance sensor with a multiplicity of spaced apart impedance probes separated by an insulating material, wherein each impedance probe includes a first end adapted for contact with a photovoltaic surface and a second end in operable communication with an impedance measuring device. The multi-tipped impedance sensor is used to contact the photovoltaic surface and electrical impedance of the photovoltaic material is measured between individual first ends of the probes to characterize the quality of the photovoltaic surface.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: September 9, 2014
    Assignee: UT-Battelle, LLC
    Inventors: Frederick Alyious List, III, Enis Tuncer
  • Patent number: 8664963
    Abstract: A test device for measuring permeability of a barrier material. An exemplary device comprises a test card having a thin-film conductor-pattern formed thereon and an edge seal which seals the test card to the barrier material. Another exemplary embodiment is an electrical calcium test device comprising: a test card an impermeable spacer, an edge seal which seals the test card to the spacer and an edge seal which seals the spacer to the barrier material.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: March 4, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Matthew Reese, Arrelaine Dameron, Michael Kempe
  • Publication number: 20140021968
    Abstract: A chip on glass substrate includes a substrate, first, second, and third pads that are arranged on the substrate and that are electrically connected to an IC device, and first to fourth conductive patterns. A first conductive pattern is arranged on the substrate, has one end electrically connected to the first pad, and has another end that is electrically floated. Second and third conductive patterns are arranged on the substrate, each have one end electrically connected to the second pad, and each have another end that is electrically floated. A fourth conductive pattern is arranged on the substrate, has one end electrically connected to the third pad, and has another end that is electrically floated.
    Type: Application
    Filed: October 24, 2012
    Publication date: January 23, 2014
    Inventor: Dae Geun LEE
  • Patent number: 8633720
    Abstract: High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Ioan Tudosa, Yuchen Zhou, Jing Zhang, Rajiv Yadav Ranjan, Yiming Huai
  • Patent number: 8564308
    Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a shunt pole-zero pair coupled to the input circuitry providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: October 22, 2013
    Assignee: Tektronix, Inc.
    Inventors: Josiah A. Bartlett, Ira G. Pollock, Daniel G. Knierim, Lester L. Larson, Scott R. Jansen, Kenneth P. Dobyns, Michael Duane Stevens
  • Patent number: 8548429
    Abstract: A cellular communication device has one or more access modes which allow reading and writing of data, for example to change its settings, for example passwords and even the entire operating system and also permitting access to personal information such as the user's telephone book. To prevent cloning and like illegal access activity, the device is configured by restricting access to such data access modes using a device unique security setting. The setting may be a password, preferably a one-time password, or it may be a unique or dynamic or one time configuration of the codes for the read and write instructions of the data mode. There is also disclosed a server, which manages the security settings such that data mode operates during an active connection between the device and the server, and a secure communication protocol for communicating between the server and the cellular device.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: October 1, 2013
    Inventor: Rafi Nehushtan
  • Publication number: 20130169298
    Abstract: A test probe has a probe portion, a current source lead attachment portion and a voltage sense lead attachment portion. The test probe includes two conductive halves secured together with an electrically insulating material disposed between the halves electrically insulating them from each other. Each half has an “L” shape including a probe portion and a test lead attachment portion extending perpendicularly outwardly from the probe portion, and provides the test probe with an overall “T” shape. The conductive halves can be made of copper-beryllium. Methods of providing and using the test probe can include uncoupling a male coupling member of a power cable connector of a loadbreak bushing assembly from a female coupling member of the loadbreak bushing and inserting the rod-shaped probe portion into the female coupling member.
    Type: Application
    Filed: January 3, 2013
    Publication date: July 4, 2013
    Applicant: Electrical Reliability Services, Inc.
    Inventor: Electrical Reliability Services, Inc.
  • Publication number: 20130154674
    Abstract: A high voltage detection device comprises a probe comprising an electrode for contacting a high voltage electrical line. The electrode is connected in series with a resistor. A meter comprises a housing enclosing an electrical circuit for measuring line voltage. The electrical circuit comprises an input circuit for connection to the probe. The input circuit is adapted to suppress high frequency noise pick up by the probe and develop a bipolar voltage representing measured line voltage. A voltage detection circuit comprises a differential amplifier circuit for converting the bipolar voltage to a proportionate voltage signal. A signal processing circuit receives the proportionate voltage signal and drives the display for displaying the measured line voltage.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Inventor: Anil NAGPAL
  • Patent number: 8446145
    Abstract: An aspect of the invention provides a method for measuring I-V characteristics of a solar cell, the solar cell comprising a plurality of fine line-shaped electrodes formed on a first surface in a predetermined direction; and a coupling line formed on the first surface that electrically couples at least two fine line-shaped electrodes among the plurality of fine line-shaped electrodes, the coupling line having a line width larger than a line width of the fine line-shaped electrodes. The method includes: contacting a probe pin for voltage measurement with the coupling line; contacting two or more probe pins for current measurement electrically connected to each other with two or more fine line-shaped electrodes including the fine line-shaped electrodes coupled to each other by the coupling line among the plurality of fine line-shaped electrodes; and measuring I-V characteristics while irradiating the first surface with light.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: May 21, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Taira, Takeshi Nishiwaki
  • Publication number: 20130118411
    Abstract: Disclosed herein are devices, systems, and methods for measuring an electropharyngeogram (EPG) in living organisms. In some embodiments, the devices and systems disclosed herein include an array for sorting and immobilizing an organism (such as a nematode) for measurement of an EPG and/or optical imaging. Also disclosed are methods for identifying therapeutic or toxic compounds utilizing the disclosed devices and systems. In some embodiments, the methods include screening for compounds with anthelmintic activity, toxicity (for example HERG channel blockers), or candidate drugs for treatment of a variety of human and/or animal diseases.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 16, 2013
    Applicants: University of Oregon
    Inventor: The State of Oregon Acting by and through the State Board of Higher E
  • Patent number: 8436624
    Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: May 7, 2013
    Assignee: Tektronix, Inc.
    Inventors: Josiah A. Bartlett, Ira G. Pollock, Daniel G. Knierim, Lester L. Larson, Scott R. Jansen, Kenneth P. Dobyns, Michael Duane Stevens
  • Patent number: 8305096
    Abstract: An apparatus and method for measuring and monitoring layer properties in web-based processes are described. The apparatus includes multiple electrode devices adjacently positioned on a surface of a web material, which advances with a predetermined speed. The electrode devices perform measurements of electrical parameters of a layer of the web material and provide an electrical signal to a layer deposition system for further adjustment of layer properties of the layer.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: November 6, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Warren Jackson, Carl Taussig
  • Patent number: 8305094
    Abstract: The resistance measuring device of the present invention includes switch transistors and switch conductive lines disposed between the bonding pads on a first substrate and between the bumps on a second substrate, such that the bonding pads and the bumps are conducted when the transistors are turned on, and the bonding resistance between at least one of the bonding pads and its corresponding bump can be directly measured.
    Type: Grant
    Filed: September 6, 2009
    Date of Patent: November 6, 2012
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8237459
    Abstract: A fall of potential method of determining earth ground resistance which utilizes an earth ground tester and eliminates the need for utilizing removable ground stakes. Rather than utilizing a “far stake” the method provides connection of the earth ground tester to the telephone wires. Rather than utilizing a “near stake” the method provides for connection of the earth ground tester to the cable shield.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 7, 2012
    Assignee: Greenlee Textron Inc.
    Inventors: Ewan G. Browne, Wayne Jacob Chappell, Paul R. Siglinger, William Cory Wood, Edwin Glenn Yancey
  • Patent number: 8232814
    Abstract: A four-wire ohmmeter connector includes a pair of elongated members spaced apart from each other by an interconnecting web. A pair of elongated contacts are mounted on forwardly projecting portions of each of the elongated members. An insulative housing surrounds the elongated members, contacts and web. The contacts mounted on one of the elongated members are connected through separate wires to a positive probe, and the contacts mounted on the other of the elongated members are connected through separate wires to a negative probe. The elongated members are inserted into respective terminal apertures of a four-wire ohmmeter. A pair of semi-cylindrical conductive sleeves are aligned with each of the apertures, and they make contact with and compress the respective contacts that are inserted into the aperture.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: July 31, 2012
    Assignee: Fluke Corporation
    Inventor: Monte Washburn
  • Publication number: 20120161799
    Abstract: An exemplary four-wire milliohmmeter includes a main body and two probe assemblies electrically connected with the main body. Each of the probe assemblies includes two plugs detachably inserted into the main body, a contact member, and two wires each electrically connecting one of the plugs to the contact member. The contact portion of each probe assembly has a needlelike free end for contacting an object.
    Type: Application
    Filed: March 31, 2011
    Publication date: June 28, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: YUN-SHAN XIAO, JIAN-CHUN PAN
  • Patent number: 8174276
    Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: May 8, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
  • Patent number: 8111079
    Abstract: A conductivity measuring apparatus includes a probe base having a pair of electrodes disposed on respective opposite surfaces of a portion of the probe base. Observing and grasping probes are supported by the probe base in a cantilever state and are arranged adjancent to and spaced apart from one another by a predetermined distance. The grasping probe has a pair of electrodes disposed on respective opposite surfaces of a portion of the grasping probe confronting the portion of the probe base. A voltage apparatus applies a voltage between the pairs of electrodes on the probe base and the grasping probe to adjust the predetermined distance between the grasping and observing probes. A movement mechanism moves a sample base and the observing and grasping probes relative to each other to bring conductive tips of the observing and grasping probes into contact with respective contact points on a sample supported on the sample base.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: February 7, 2012
    Assignee: SII NanoTechnology Inc.
    Inventors: Masatoshi Yasutake, Takakazu Fukuchi
  • Patent number: 7973541
    Abstract: Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: July 5, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Jayakannan Jayapalan, David Bang, Yang Du
  • Patent number: 7948250
    Abstract: The invention concerns a probe with at least two test prods, which are provided on a changing device connected to the probe and which can be alternately connected to an electric waveguide running inside the probe.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: May 24, 2011
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Martin Peschke
  • Patent number: 7944222
    Abstract: Calculating resistance correction factors includes contacting the arms of a four-arm probe with a test sample; selecting a first set of first and second arms and a second set of third and fourth arms; applying a first current from the first arm to the second arm of the first set; detecting a first voltage between the third and fourth arms of the second set; calculating a first resistance using the first voltage and current; selecting a third set of first and second arms including no more than one arm of the first set, and a fourth set of third and fourth arms including no more than one arm of the second set; applying a second current from the first arm to the second arm of the third set; detecting a second voltage between the third and fourth arms of the fourth set; calculating a second resistance using the second voltage and current; and calculating a correction factor using the first and second resistances.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 17, 2011
    Assignee: Capres A/S
    Inventor: Torben M. Hansen
  • Patent number: 7940038
    Abstract: Disclosed is an arrangement for quickly measuring the phase distribution or the component distribution in a flow cross section for substance mixtures also of a non-conducting type by measuring the complex electrical admittance. Said arrangement essentially features the following: at least one sine wave generator (5) which is mounted upstream from the transmitter electrodes (3a) of the excitation level and applies an alternating voltage to the transmitter electrodes (3a); current-to-voltage converters (7) which are mounted downstream from the receiver electrodes (3b), amplify the alternating current that flows from at least one excitation electrode (3a) through the medium to the receiver electrodes (3b), and convert said alternating current into a voltage signal; filter groups (10, 11, 16) and vector voltmeters (8) which are mounted downstream from the current-to-voltage converters (7) and allow the complex signal ratio Ua/Ue to be metrologically detected.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: May 10, 2011
    Assignee: Helmholtz-Zentrum Dresden-Rossendorf e.V.
    Inventors: Marco Jose Da Silva, Eckhard Schleicher, Uwe Hampel, Horst-Michael Prasser
  • Publication number: 20110084706
    Abstract: Calculating resistance correction factors includes contacting the arms of a four-arm probe with a test sample; selecting a first set of first and second arms and a second set of third and fourth arms; applying a first current from the first arm to the second arm of the first set; detecting a first voltage between the third and fourth arms of the second set; calculating a first resistance using the first voltage and current; selecting a third set of first and second arms including no more than one arm of the first set, and a fourth set of third and fourth arms including no more than one arm of the second set; applying a second current from the first arm to the second arm of the third set; detecting a second voltage between the third and fourth arms of the fourth set; calculating a second resistance using the second voltage and current; and calculating a correction factor using the first and second resistances.
    Type: Application
    Filed: November 8, 2010
    Publication date: April 14, 2011
    Inventor: Torben M. Hansen
  • Patent number: 7863911
    Abstract: A combined manufacturable wafer and test device for measuring a tunneling-magnetoresistance property of a tunneling-magnetoresistance, sensor-layer structure. The combined manufacturable wafer and test device comprises a tunneling-magnetoresistance, sensor-layer structure disposed on a substrate. The combined manufacturable wafer and test device also comprises a plurality of partially fabricated tunneling-magnetoresistance sensors; at least one of the partially fabricated tunneling-magnetoresistance sensors is disposed at one of a plurality of first locations. The test device is disposed on the substrate at a second location different from the plurality of first locations. The test device allows measurement of the tunneling-magnetoresistance property of the tunneling-magnetoresistance, sensor-layer structure using a current-in-plane-tunneling technique.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 4, 2011
    Assignee: Hitachi Global Storage Technologies, Netherlands, B.V.
    Inventors: Ying Hong, Wipul P. Jayasekara, Daniele Mauri, David J. Seagle
  • Patent number: 7852093
    Abstract: Calculating resistance correction factors includes contacting the arms of a four-arm probe with a test sample; selecting a first set of first and second arms and a second set of third and fourth arms; applying a first current from the first arm to the second arm of the first set; detecting a first voltage between the third and fourth arms of the second set; calculating a first resistance using the first voltage and current; selecting a third set of first and second arms including no more than one arm of the first set, and a fourth set of third and fourth arms including no more than one arm of the second set; applying a second current from the first arm to the second arm of the third set; detecting a second voltage between the third and fourth arms of the fourth set; calculating a second resistance using the second voltage and current; and calculating a correction factor using the first and second resistances.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: December 14, 2010
    Assignee: Capres A/S
    Inventor: Torben M. Hansen
  • Patent number: 7786739
    Abstract: Embodiments of the invention include testing arrangements for detecting proper DC-coupled board connections on the input legs of a differential receiver. The testing implementation includes a first test receiver AC-coupled to the connection between the first input/output (I/O) pad and the differential receiver positive input and/or a second test receiver coupled to the connection between the second I/O pad and the differential receiver negative input. The test receiver protects the test receiver input from DC voltages applied to the differential receiver via the differential receiver input. Also, the test receiver includes a high-pass filter arrangement that generates data capable of detecting whether the I/O pad connected to the test receiver has a proper DC-coupled connection or an improper connection when presented with a stimulus pulse. The test receiver is less susceptible to noise because than conventional arrangements that use a low-pass RC filter.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: August 31, 2010
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Manuel Salcido, James Hansen, Greg Milburn
  • Patent number: 7764071
    Abstract: An automated method is provided for testing an electrical circuit using a system tester. Load leads and sense leads of the tester are connectable to any two points of an electrical circuit, such as in a vehicle system, for displaying in real time the impedance between the tested circuit points. A controller is responsive to various sensed signals to calculate impedance, admittance or conductance, and related parameters, such as available cranking current, and provide results for read out or display. A load may be connected across the circuit points under test, the sensed signals derived from a current sense amplifier, a DC voltage amplifier, a ripple amplifier, and an AC amplifier.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: July 27, 2010
    Assignee: Snap-On Incorporated
    Inventors: Dennis G. Thibedeau, Gary Jonker, Alejandro P. Brott, Paul A. Willems, Alan D. Goetzelmann
  • Patent number: 7746061
    Abstract: This present invention discloses a method for performing an accurate calibration of signal measurement by a light-driving system including an automatic power control (APC) circuit which is pre-calibrated for a signal measurement process. By enlarging at least one measured pad of the APC circuit, multiple grounding paths are established via a plurality of probes of a test instrument. An impedance effect predicted on the contact between the probes and the pad is diminished greatly. A voltage value on the pad can be accurately measured. Thus, a reference voltage value input to a first input of a comparator of the APC circuit can be determined on a basis of a specific condition when a ramping voltage value input to a second input of the comparator is substantially equal to a sum of a predetermined reference voltage value and the voltage value of the pad.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: June 29, 2010
    Assignee: MEDIATEK Inc.
    Inventors: An-nan Chang, Chien-ming Chen