Abstract: An electronic device includes: a detection circuit configured to determine one or more operating data, one or more device sensor data, or a combination thereof associated with operation of the electronic device; a trigger circuit operably coupled to the circuit, the trigger circuit configured to generate a stress input based on detecting one or more target criteria from the one or more operating data, the one or more device sensor data, or a combination thereof; and a degradation sensor operably coupled to the trigger circuit, the degradation sensor having a threshold voltage and being configured to record the target criteria that occurs during operation of the electronic device, wherein the degradation sensor is configured to record the target criteria based on degradation of the threshold voltage according to the stress input.

Abstract: A method and system for re-using the electrical energy of an electronic component under test. The method and system includes combining a first direct current voltage output of an electronic component under test with a second direct current voltage of a device. The combined first direct current voltage and second direct current voltage are regulated to create a power. The power functions a system application. At least one metric of the electronic component under test is monitored.

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

Abstract: A passive bias temperature compensation module for silicon photomultiplier, avalanche photodiodes and similar photodetectors that possess a moderately linear temperature coefficient of gain and that may be compensated by varying an applied bias voltage. The module includes an electrical circuit and a method for determining component values to provide a constant voltage source to stabilize the gain of one or more photodetector devices. A temperature sensor in the module is held in close thermal contact with the photodetector and a filter capacitor is electrically close to the photodetector. The module is based on the concept of temperature sensitive voltage division which is applicable to situations in which large numbers of photodetectors must be gain-compensated for temperature variations over a wide range while maintaining excellent gain matching. The passive bias temperature compensation method enables multiple photodetectors to share a single constant voltage supply without loss of matching performance.

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, the testing system includes a robot disposed in an enclosure and having a range of motion operable to transfer a chip package assembly between any of a first queuing station, a second queuing station and a plurality of test stations. The system also includes an automatic identification and data capture (AIDC) device operable to read an identification tag affixed to a carrier disposed in the first and second queuing stations, and a controller configured to control placement of chip package assemblies by the robot in response information obtained from a carrier disposed in at least one of the first and second queuing stations, the predefined test routine of the test processor of the first test station, and the predefined test routine of the test processor of the second test station.

Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

Abstract: A testing method includes measuring an electrical parameter of a device under test (DUT) and a corresponding temperature of the DUT one or more times, determining coefficients in a pre-constructed model based on a plurality of measured values of the electrical parameter and corresponding measured temperatures to characterize a relationship of the electrical parameter to the temperature, and determining a quality of the DUT based on the model and a limit value of the electrical parameter at a specified temperature. The model is pre-constructed to characterize the relationship of the electrical parameter to the temperature with the coefficients that are DUT-dependent variables.

Abstract: A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level.

Abstract: An apparatus comprises a pillar formed on a top surface of a semiconductor substrate, wherein the pillar comprises a first pillar region, a second pillar region and a first cavity formed between the first pillar region and the second pillar region, and wherein the first cavity is configured to accommodate a probe pin.

Abstract: A method for measuring an electrical current with the aid of a field effect transistor inserted into a current path is disclosed, in which a control voltage is applied between the gate and source of the transistor in such a way that the voltage drop between the drain and source at the transistor in the current path remains within a specifiable range. Further, said voltage drop and the control voltage are determined. With these two values, and with a known relationship between the drain-source current, the drain-source voltage and the gate-source voltage the value of the current of interest can now be determined. Apparatus for implementing the method according to the invention is, furthermore, disclosed.

Abstract: A circuit device according to an aspect of the present invention includes a circuit board which has one or more wiring layers formed on a base material and has an insulating layer laminated on a surface of the base material opposite to the one or more wiring layers, and a guiding member which is configured to encircle at least a part of an end face of the circuit board so that a space is formed with the end face and to guide movement of a dried body which is supplied to the formed space.

Abstract: An electronic system comprises a resistive sensor structure and an electronic circuit portion whose design is selected such that different resistive sensor structures may be combined within the same electronic circuit. To this end, the resistive sensor structure is used as a voltage/current converter that provides input currents to a current amplifier, which in turn provides an amplified output voltage on the basis of a difference of the input currents. The operating range of the current amplifier is adjusted on the basis of a programmable current source irrespective of the configuration of the resistive sensor structure.

Abstract: An apparatus controls a temperature of a device by circulating a fluid through a heat sink in thermal contact with the device. The apparatus includes an adjustable cold input, which inputs a cold portion of the fluid having a first temperature, and an adjustable hot input, which inputs a hot portion of the fluid having a second temperature higher than the first temperature. The apparatus further includes a chamber, connected to the cold input and hot input, in which the cold and hot portions of the fluid mix in a combined fluid portion that impinges on the heat sink. The combined fluid portion has a combined temperature that directly affects a temperature of the heat sink. The cold input and hot input are adjusted to dynamically control the combined temperature, enabling the heat sink temperature to compensate for changes in the device temperature, substantially maintaining a set point temperature of the device.

Abstract: A method for correcting measurement of a voltage across output terminals of a sensor, the sensor configured to be assimilated with an assembly including a generator and a series resistance, each of the output terminals being respectively connected to a pull up/down resistor. The method includes: evaluating the series resistance of the sensor, including measuring first and second voltages across the output terminals when first and second bias voltages are applied on each pull up/down resistor; evaluating the series resistance from the first and second voltages; and correcting, from the series resistance, a voltage measured across the output terminals of the sensor to infer therefrom a corresponding voltage generated by the generator.

Abstract: A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

Abstract: A power measurement transducer includes a thermally conductive heat spreading device having a first surface configured to thermally couple the power measurement transducer to a device under test. Two or more temperature measurement elements are positioned within the thermally conductive heat spreading device.

Abstract: A method of determining thermal output of a device under test includes attaching a power measurement transducer to a device under test, wherein the power measurement transducer includes two or more temperature measurement elements. A test sequence is applied to the device under test. One or more signals produced by the power measurement transducer are monitored to determine a quantity of power produced by the device under test during the test sequence.

Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

Abstract: A method includes measuring a first voltage across a test diode on a semiconductor wafer while injecting a first current into the test diode, measuring a second voltage across the test diode while injecting a second current into the test diode, and determining temperature of a region proximate the test diode according to difference between the first voltage and the second voltage.

Abstract: A test apparatus includes a plurality of rails, a plurality of test zones and a movable test chamber. The test zones are located between the rails. The movable test chamber includes a passageway, at least one heat source and at least one pair of rolling balls. The heat source is used to heat the passageway. The pair of rolling balls is movably contained in two rails, so as to facilitate movement of the passageway to different test zones.

Abstract: Thermal control units (TCU) for maintaining a set point temperature on an IC device under test (DUT) are provided. The units include a pedestal assembly comprising a heat-conductive pedestal, a fluid circulation block, a thermoelectric module (Peltier device) between the heat-conductive pedestal and the block for controlling heat flow between the pedestal and fluid circulation block, and a force distribution block for controllably distributing a z-axis force between different pushers of the TCU. Alternatively, instead of a thermoelectric module, a heater can provide heat to the DUT. Optionally, a swivelable temperature-control fluid inlet and outlet arms may be provided to reduce instability of the thermal control unit due to external forces exerted on the TCU such as by fluid lines attached to the fluid inlet and outlet arms. Also optionally, an integrated means for abating condensation on surfaces of the TCU during cold tests may be provided.

Abstract: A method for quasi-static testing a magnetic recording head read sensor is described. The method includes applying a first voltage to a heater in the magnetic recording head and measuring an output of the magnetic recording head read sensor while applying the first voltage to the heater and recording the measured output as a first set of measurements. The method further includes applying a second voltage to the heater in the magnetic recording head and measuring the output of the magnetic recording head read sensor while applying the second voltage to the heater and recording the measured output as a second set of measurements. The first and second sets of measurements are then compared.

Abstract: A system for testing electronic device includes an electronic device, a temperature detecting module, a testing instrument and a testing computer. The testing electronic includes a main board and a power supply. The main board includes a slot and a card inserted in the slot. A plurality of dummy loads is located on the card. The slot includes at least one voltage interface. The power supply includes at least one power wire electrically connected to the at least one voltage interface. The temperature detecting module detects temperature signals of the plurality of dummy loads. The testing instrument is electrically connected to the at least one power wire to test current signals or power signals of the at least one power wire. The testing computer receives and displays the temperature signals, the current signals and the power signals.

Abstract: A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.

Abstract: A controller controls switching of IGBT devices of an inverter according to the desired output of the permanent magnet motor. The controller includes: a magnet temperature detection device that detects the magnet temperature of the permanent magnet motor based on the output of a temperature sensor; a setting device that sets a threshold value of the magnet temperature corresponding to the desired output of the permanent magnet motor, based on a predetermined relation between the output from the permanent magnet motor and a critical temperature, up to which demagnetization in the permanent magnet motor is not caused; and a carrier frequency control device that, when the magnet temperature detected by the magnet temperature detection device exceeds the threshold value, changes the carrier frequency, at which the IGBT devices are switched, such that a ripple current superimposed on a motor current that flows through the permanent magnet motor is reduced.

Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.

Abstract: A test slot assembly is provided for testing a storage device. The test slot assembly is configured to receive and support a storage device, or a storage device supported by a storage device transporter. The test slot assembly also includes a conductive heating assembly. The conductive heating assembly is arranged to heat a storage device by way of thermal conduction.

Abstract: A plurality of devices under test (DUT) are arranged in a strip tester having a temperature controlled heater block. Each DUT has a respective set of electrical test probes and a thermally conductive test probe for electrically and thermally coupling, respectively, of the strip tester to the DUTs. Temperature measurement of each of the plurality of DUTs is performed by a temperature measuring device. The temperature measuring device can be part of the test board of the strip tester and will be in thermal communications with the DUT through the thermally conductive test probe, or temperature of the DUT can be measurement with an RTD embedded in the thermally conductive test probe, thereby providing faster thermal response time.

Abstract: Thermal control units (TCU) for maintaining a set point temperature on an IC device under test (DUT) are provided. The units include a pedestal assembly comprising a heat-conductive pedestal, a fluid circulation block, a thermoelectric module (Peltier device) between the heat-conductive pedestal and the block for controlling heat flow between the pedestal and fluid circulation block, and a force distribution block for controllably distributing a z-axis force between different pushers of the TCU. Optionally, a swivelable temperature-control fluid inlet and outlet arms may be provided to reduce instability of the thermal control unit due to external forces exerted on the TCU such as by fluid lines attached to the fluid inlet and outlet arms. Also optionally, an integrated means for abating condensation on surfaces of the TCU during cold tests may be provided.

Abstract: System for remote measuring a physical variable comprising an RF transceiver arranged for transmitting an RF signal and for receiving a reflection signal derived from the transmitted signal. An RF transponder comprises a dielectric material having a dielectric property which is dependent on the physical variable according to a first function. The dielectric material is exposed to the physical variable to be measured. The transponder is arranged to receive the signal transmitted by the transceiver and to reflect a reflection signal, or the second and/or higher harmonics of it, which is dependent on the actual dielectric property. Processing means are provided for comparing the signal transmitted by the transceiver and the reflection signal received from the transponder and for converting the comparison result, e.g. the phase shift, into a value which is representative for the physical variable to be measured. The transponder may be e.g. a patch antenna.

Abstract: Methodologies and test configurations are provided for testing thermal interface materials and, in particular, methodologies and test configurations are provided for testing thermal interface materials used for testing integrated circuits. A test methodology includes applying a thermal interface material on a device under test. The test methodology further includes monitoring the device under test with a plurality of temperature sensors. The test methodology further includes determining whether any of the plurality of temperature sensors increases above a steady state.

Abstract: A current sensor is disclosed. The current sensor includes a leadframe having a die paddle, a portion of the die paddle being configured as a resistive element through which current can flow, and an integrated circuit (IC) die attached and thermally coupled to the die paddle. The IC die includes a current sensing module configured to measure a voltage drop across the resistive element and convert the voltage drop measurement to a current measurement signal and a temperature compensation module electrically coupled to the current sensing module. The temperature compensation module is configured to adjust the current measurement signal to compensate for temperature-dependent changes in the resistive element. The temperature compensation module includes a temperature-sensitive element, with a portion of the temperature-sensitive element located directly over a portion of the resistive element.

Abstract: Embodiments of probe cards and methods for fabricating and using same are provided herein. In some embodiments, an apparatus for testing a device (DUT) may include a probe card configured for testing a DUT; a thermal management apparatus disposed on the probe card to heat and/or cool the probe card; a sensor disposed on the probe card and coupled to the thermal management apparatus to provide data to the thermal management apparatus corresponding to a temperature of a location of the probe card; a first connector disposed on the probe card and coupled to the thermal management apparatus for connecting to a first power source internal to a tester; and a second connector, different than the first connector, disposed on the probe card and coupled to the thermal management apparatus for connecting to a second power source external to the tester.

Abstract: A testing device of semiconductor devices includes a temperature detector detecting temperatures of semiconductor devices, and a temperature control unit controlling the temperatures of the semiconductor devices based on a detected temperature, in which the temperature control unit includes thermal heads cooling or heating the semiconductor devices, solution pipes through which solutions set to different temperatures flow, and a channel switching part switching whether or not to make the solution flow through the thermal head, and when a test is conducted, the solution flown through the thermal head is switched according to heating amount of the semiconductor device.

Abstract: A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.

Abstract: Self-heating integrated circuits are provided. In one embodiment, a self-heating integrated circuit comprises a drive circuit configured to drive a device and a controller configured to selectively operate the drive circuit in a first mode or a second mode. In the first mode, the controller is configured to operate the drive circuit to drive the device and, in the second mode, the controller is configured to operate the drive circuit to heat the integrated circuit to a target temperature.

Abstract: A testing system for a PSU includes a test chamber and a control device. The test chamber includes a first partition with the PSU accommodated therein and a second partition with an electric load accommodated therein. The PSU is electrically connected to the electric load. The control device includes a microcontroller unit (MCU). The MCU is connected to a setting circuit and a temperature sensing circuit. The setting circuit is configured to set one of predetermined parameters. The temperature sensing circuit is capable of sensing temperature in the test chamber. The MCU is capable of automatically controlling a predetermined temperature in the test chamber and presetting a test time for testing the PSU.

Abstract: A probe card assembly can include an electrical interface to a test system for testing electronic devices such as semiconductor dies. The probe card assembly can also include probes located at a first side of the probe card assembly. The probes, which can be electrically connected to the electrical interface, can be configured to contact terminals of the electronic devices in the test system while the probe card assembly is attached to the test system. The probe card assembly can be configured to impede thermal flow from the probe card assembly to the test system at places of physical contact between the probe card assembly and the test system while the probe card assembly is attached to the test system.

Abstract: A system includes a first module, a second module, and a third module. The first module determines a first temperature and a first power dissipation value of a thermistor based on a resistance of a first resistor connected in series with the thermistor. The second module, after disconnecting the first resistor and connecting a second resistor in series with the thermistor, determines a second temperature and a second power dissipation value of the thermistor based on a resistance of the second resistor. The third module determines a thermal dissipation factor based on the first and second temperatures and the first and second power dissipation values, and corrects temperature sensed by the thermistor based on the thermal dissipation factor.

Abstract: An apparatus is provided and includes a thermally isolated device under test to which first and second voltages are sequentially applied, a local heating element to impart first and second temperatures to the device under test substantially simultaneously while the first and second voltages are sequentially applied, respectively and a temperature-sensing unit to measure the temperature of the device under test.

Abstract: A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

Abstract: A thermal control unit with a heat pipe that conducts heat away from a device under test during burn-in. The heat pipe has a heater that allows control of the rate at which heat is transferred from the DUT to the heat pipe. A sensor and controller are provided to control the heat in response to the measured temperature of the DUT. The sensor and controller control the heater to maintain the surface temperature of the DUT within a specified range.

Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Abstract: The present invention relates to electromigration testing and evaluation methods and apparatus for a device under test with an interconnect structure. The method comprises forcing the occurrence of a step resistance-increase of the interconnect structure due to electromigration in the first layer and subsequently subjecting the interconnect structure to at least three respective predetermined stress conditions while concurrently measuring a test quantity indicative of an electrical resistance of the interconnect structure. The method allows performing an electromigration test in much shorter time than known electromigration testing methods, without loss of information or accuracy. It is therefore possible to accelerate the optimization of the interconnect manufacturing process so that the conductor electromigration kinetics remains compatible with a required product lifetime.

Abstract: Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

Abstract: A burn-in system (10) includes an enclosure (12) defining a burn-in chamber (14). The enclosure (12) is configured to be mounted on a burn-in board (34) over a burn-in socket (36). A heating element (16) is configured to generate heat within the burn-in chamber (14) and a temperature sensor (18) is configured to sense a temperature within the burn-in chamber (14). An opening (24) is formed in the enclosure (12) for receiving a fluid (26). A controller (20) is configured to control the heating element (16) and fluid flow into the enclosure (12) in response to the temperature sensed by the temperature sensor (18).

Abstract: A temperature regulation plate 106 is divided into at least two areas, a heater 408 for applying a temperature load in correspondence with such areas and its control system are divided and controlled independently to set temperatures, and a cooling source is controlled by comparing the measurements from temperature sensors 409 arranged in respective areas for controlling the heater 408 and switching the measurement for calculating the control output sequentially thus reducing variation in in-plane temperature of a wafer due to heating when an electric load is applied. Since consumption and burning of a probe are prevented, highly reliable wafer level burn-in method and apparatus can be provided.

Abstract: A method of controlling a temperature of a test slot in a disk drive testing system includes regulating temperature changes of a subject test slot based on one or more operating conditions of one or more other test slots neighboring the subject test slot.

Abstract: A burn-in system (10) includes an enclosure (12) defining a burn-in chamber (14). The enclosure (12) is configured to be mounted on a burn-in board (34) over a burn-in socket (36). A heating element (16) is configured to generate heat within the burn-in chamber (14) and a temperature sensor (18) is configured to sense a temperature within the burn-in chamber (14). An opening (24) is formed in the enclosure (12) for receiving a fluid (26). A controller (20) is configured to control the heating element (16) and fluid flow into the enclosure (12) in response to the temperature sensed by the temperature sensor (18).