Burn-in Patents (Class 324/750.05)
  • Patent number: 10592331
    Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Clark N. Vandam, Balkaran Gill, Junho Song, Suriya Ashok Kumar, Kasyap Pasumarthi
  • Patent number: 10495687
    Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiang-Ruei Su, Liang-Chen Lin, Chia-Wei Tu
  • Patent number: 10405777
    Abstract: Representative apparatus, method, and system embodiments are disclosed for non-invasive detection an ingested battery or magnet in a human or other animal subject. The various apparatus embodiments include one or more Hall effect sensors, arranged in a hand-held embodiment or arranged along a flexible strip having an adhesive. A calibration may be determined or reference or calibration field measurements may be generated. A flexible strip is arranged, or the hand-held embodiment is moved, over the esophagus of the subject to generate target magnetic field measurements. The presence of an ingested battery or magnet is detected when one or more target magnetic field measurements (or gradient) is or are greater than or equal to a first predetermined threshold, or when a sign reversal occurs for a difference between target and reference measurements. The various apparatus and system embodiments may also include a monitor for signal processing and display of results.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 10, 2019
    Assignees: Northwestern University, Ann and Robert H. Lurie Children's Hospital of Chicago
    Inventors: Bharat Bhushan, Claus-Peter Richter, Jonathan Ida
  • Patent number: 10241156
    Abstract: A method and system for re-using the electrical energy of an electronic component under test. The method and system includes combining a first direct current voltage output of an electronic component under test with a second direct current voltage of a device. The combined first direct current voltage and second direct current voltage are regulated to create a power. The power functions a system application. At least one metric of the electronic component under test is monitored.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc Coq, Randhir S. Malik
  • Patent number: 10236077
    Abstract: According to one embodiment, a screening method includes performing a first screening operation on a memory device at a first temperature to detect a defect in magnetoresistive effect elements of the memory device, replacing a first magnetoresistive effect element that is determined as defective in the first screening operation by substituting a second magnetoresistive effect element disposed in a redundancy area of the memory device for the first magnetoresistive, and performing a second screening operation on the memory device at a second temperature higher than the first temperature if the first screening operation detects a defect. Each of the first screening operation and the second screening operation includes writing data into the magnetoresistive effect element, reading data from the magnetoresistive effect element after the writing, and determining a magnetoresistive effect element is defective when the data as written does not match the data as read.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: March 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yosuke Kobayashi, Katsuya Nishiyama
  • Patent number: 10231303
    Abstract: A light emitting diode lamp receiving a contactless burning signal includes at least a light emitting diode and a light emitting diode driving apparatus. The light emitting diode driving apparatus includes a burning signal detector, an address burning controller, an address memory and a light emitting diode driving circuit. The burning signal detector wirelessly receives a wireless address signal from outside. The burning signal detector converts the wireless address signal into a local address signal. The burning signal detector transmits the local address signal to the address burning controller. The address burning controller burns the local address signal into the address memory, so that the address memory stores a local address data.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: March 12, 2019
    Assignee: SEMISILICON TECHNOLOGY CORP.
    Inventor: Wen-Chi Peng
  • Patent number: 10210062
    Abstract: A data storage system comprises a primary storage system comprising an array of drives and a storage controller comprising a stack of storage components. A storage component of the stack operates a data redundancy scheme for the primary storage system. The storage controller stores a set of data on the primary storage system, detects a failure on one or more drives and determines a set of addresses defining data that cannot be completely repaired. Starting with the storage component operating the data redundancy scheme, each storage component queries the storage component directly above with the set of addresses for the data that cannot be completely repaired, obtaining, from one or more storage components, the data that cannot be completely repaired. This obtained data is used to repair the data on the primary storage system with the data from the one or more storage components.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Ian Boden, Gordon D. Hutchison, Lee J. Sanders
  • Patent number: 10120026
    Abstract: A chip is provided that includes an integrated circuit including a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains. The chip further includes an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 6, 2018
    Assignee: Lantiq Beteiligungs-GmbH & Co. KG
    Inventors: Himanshu Kukreja, Shakil Ahmad
  • Patent number: 10103121
    Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 16, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 10102092
    Abstract: A testing method for testing a plurality of devices under test (DUT) includes transmitting first testing routine signals from a first backend controller to a testing front end module via a wired data connection between the first backend controller and a first testing signal interface of the testing front end module, transmitting second testing routine signals from a second backend controller to the testing front end module via a wired data connection between the second backend controller and a second testing signal interface of the testing front end module, prioritizing one of the first and second testing routine signals according to predefined priority criteria in the testing front end module, and generating testing signals in the testing front end module on the basis of the prioritized testing routine signals.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: October 16, 2018
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Jens Volkmann, Thomas Lutz, Walter Schmitz
  • Patent number: 10094871
    Abstract: An electronic-component testing device capable of achieving efficient heat-releasing from a self-heating electronic component and efficiently performing a desired test while maintaining the temperature of the electronic component in a predetermined range higher than ordinary temperature.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masakazu Itakura, Tetsuo Kawasaki
  • Patent number: 10078111
    Abstract: A handler includes a loading unit transporting substrates and sockets coupled to the substrates, a test unit including a printed circuit board, the sockets being mounted on the printed circuit board, and latches fixing the sockets to the printed circuit board, and an unloading unit unloading the substrates and the sockets from the test unit.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guiheum Choi, Hogyung Kim, Younggil Lee
  • Patent number: 9991610
    Abstract: A pair of solder bonding portions to be solder-bonded onto the printed wiring board and a contact portion to contact the different conductive member or the like are coupled by a pair of flat spring portions. The respective flat spring portions protrude from side surfaces of mutually opposed corners of the contact portion. Sections following protruded sections of the respective flat spring portions are bent so as to wind in the same direction around a pillar-shaped space obtained by projecting the contact portion downward, and the flat spring portions reach the corresponding solder bonding portions. When the contact portion is pressed by the conductive member, the contact portion and the solder bonding portions remain parallel to each other, whereby the contact member can be successfully flattened toward the printed wiring board. At this point, outward deformation of the flat spring portions is inhibited.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 5, 2018
    Assignee: KITAGAWA INDUSTRIES CO., LTD.
    Inventor: Tomohisa Kurita
  • Patent number: 9910085
    Abstract: A laminate bond strength detection apparatus is provided. The laminate bond strength detection apparatus includes first circuit elements affixable to a printed circuit board (PCB), a housing having a coefficient of thermal expansion (CTE) mismatched from that of the PCB, second circuit elements affixable to the housing and configured to be laminated to a surface of the PCB, connectors and circuitry. The connectors respectively connect pairs of the first and second circuit elements and are breakable during CTE mismatch inducing heat processing resulting in the corresponding second circuit element becoming delaminated from the surface. The circuitry is coupled to the first and second circuit elements and configured to determine a number of broken connectors following the heat processing and to calculate a laminate bond strength of the PCB from the number of broken connectors.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen M. Hugo, Theron L. Lewis
  • Patent number: 9880199
    Abstract: A probe for automatic test equipment (ATE) includes: an outer shroud including a course alignment feature configured to receive a target device and to guide the target device into an interior of the outer shroud, where the target device includes exposed electrical leads; and an inner structure that is at least partly inside the outer shroud. The inner structure includes electrical contacts for making an electrical connection to the exposed electrical leads, and also includes a fine alignment feature configured to guide the target device towards the electrical contacts to make the electrical connection.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 30, 2018
    Assignee: Teradyne, Inc.
    Inventor: Valquirio N. Carvalho
  • Patent number: 9874605
    Abstract: To electrically connect a device under test mounted on a device holder and a socket of a test apparatus with accuracy. Provided is a device holder that retains a device, the device holder including: an inner unit that mounts the device; and an outer unit that retains the inner unit such that the inner unit is relatively movable, wherein the inner unit switches whether to lock the outer unit relative to the inner unit or to release the lock. Also, the inner unit and the outer unit of the device holder are provided.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 23, 2018
    Assignee: ADVANTEST CORPORATION
    Inventors: Mitsunori Aizawa, Yuya Yamada
  • Patent number: 9799579
    Abstract: A semiconductor assembly includes a first semiconductor substrate having a first main surface and a second main surface and a second semiconductor substrate having a first main surface and a second main surface. The first main surface of the first semiconductor substrate faces the second main surface of the second semiconductor substrate. Further, the semiconductor assembly includes a plurality of first electrodes disposed on the first main surface of the first semiconductor chip and a plurality of second electrodes disposed on the second main surface of the second semiconductor chip, wherein the first electrodes are aligned with and connected by interconnects to the second electrodes. An electrically conducting layer perforated by holes is disposed between and fixed to the first semiconductor substrate and the second semiconductor substrate, wherein the interconnects penetrate the holes. The electrically conducting layer is electrically connected to a function test electrode of the semiconductor assembly.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies AG
    Inventor: Dietrich Bonart
  • Patent number: 9793239
    Abstract: Various semiconductor workpieces with selective backside metallizations and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor workpiece that has multiple dies. A backside metallization is fabricated on a first die of the dies but not on a second die of the dies.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 17, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Z. Su, Michael S. Alfano, Bryan Black
  • Patent number: 9720013
    Abstract: A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: August 1, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pin-Cheng Huang, Yi-Che Lai
  • Patent number: 9676619
    Abstract: The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 13, 2017
    Assignee: MEMSIC SEMICONDUCTOR (WUXI) CO., LTD.
    Inventors: Yang Zhao, Piu Francis Man, Leyue Jiang, Haidong Liu, Bin Li
  • Patent number: 9658286
    Abstract: An assembly strip test method and adapter allows for the concurrent loading of multiple assembly strips for testing in a concurrent and/or round-robin fashion in a strip tester. The test method and adapter allows the multiple assembly strips to be loaded into a strip tester in a single load cycle, reducing assembly strip load cycle overhead. Signals generated by test probes can be used to select between the loaded assembly strips for testing via the strip tester. Parallel coupling between corresponding pins of corresponding integrated circuits of different assembly strips allows a single test probe to be used as stimulus or monitor for two or more assembly strips. In certain configurations a stackable assembly strip test adapter is used. In other configurations the integrated circuits include at least part of the assembly strip selection decoding logic.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 23, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Wei Keong Chan
  • Patent number: 9652028
    Abstract: A device for reconfigurable power conversion includes a plurality of power-consuming modules adapted to receive a plurality of electrical voltages, and a power converter module including a plurality N of power stages, each of which includes a power output which is adapted to supply one of the plurality of electrical voltages and adapted to be coupled with at least one of the others of the power outputs off the power converter module. Also included is a backplane including a plurality of power rails, each of which is adapted to distribute one of the plurality of electrical voltages from the power converter module to the plurality of power-consuming modules. The power converter module further includes a programmable converter controller which is adapted to reversibly configure the plurality of power stages.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas C. Doering, Rihards Dziedatajs
  • Patent number: 9640619
    Abstract: A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips, fixing the plurality of first semiconductor chips on a fixation member, measuring a breakdown voltage of each of the first semiconductor chips while immersing at least the first semiconductor chips in inert liquid, and after the step of measuring a breakdown voltage of each of the first semiconductor chips, providing a plurality of second semiconductor chips each having each of the first semiconductor chips fixed on the fixation member, by cutting the fixation member.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 2, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Mitsuhiko Sakai
  • Patent number: 9606616
    Abstract: A device for reconfigurable power conversion includes a plurality of power-consuming modules adapted to receive a plurality of electrical voltages, and a power converter module including a plurality N of power stages, each of which includes a power output which is adapted to supply one of the plurality of electrical voltages and adapted to be coupled with at least one of the others of the power outputs off the power converter module. Also included is a backplane including a plurality of power rails, each of which is adapted to distribute one of the plurality of electrical voltages from the power converter module to the plurality of power-consuming modules. The power converter module further includes a programmable converter controller which is adapted to reversibly configure the plurality of power stages.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas C. Doering, Rihards Dziedatajs
  • Patent number: 9575112
    Abstract: A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Wook Oh, Chin Kim, Sunhom Steve Paak, Jae-Seok Yang
  • Patent number: 9535113
    Abstract: A method, apparatus and computer program product for testing semiconductor products that combines multiple techniques. Depending on the requirements, different ones of the techniques are emphasized over the other techniques. The testing applies a technique to achieve a higher single defect acceleration parameter at the expense of a second parameter, thus enabling acceleration of defects that require higher voltage or higher temperature than a traditional “Burn In” can achieve, which defects would otherwise go unaccelerated. The method manages the adaptation of the different techniques, e.g., how it decides to favor one technique over the other, and how it carries out the favoring of one or more particular techniques in a given test situation. Thus, acceleration to defectivity (defect type and quantity) may be tailored in real time by uniquely leveraging the duration spent in a given section of a process flow based on the prevalence of unique defect types.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: David A. Grosch, Gregory V. Miller, Brian C. Noble, Ann L. Swift, Joel Thomas, Jody J. Van Horn
  • Patent number: 9536617
    Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: January 3, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma
  • Patent number: 9525098
    Abstract: A solar cell and a method of manufacturing a solar cell are disclosed. The solar cell includes forming a first doped region of a first conductive type and a second doped region of a second conductive type opposite the first conductive type on a semiconductor substrate of the first conductive type; forming a passivation layer on the semiconductor substrate to expose a portion of each of the first and second doped regions; and forming a first electrode electrically connected to the first doped region and a second electrode electrically connected to the second doped region, wherein the forming of the first and second electrodes includes forming a metal seed layer directly contacting the first doped region and a metal seed layer directly contacting the second doped region, and forming a conductive layer on the metal seed layer of each of the first and second electrodes.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: December 20, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Sungeun Lee, Youngho Choe
  • Patent number: 9506984
    Abstract: Some forms relate to a SOC testing apparatus. The example SOC testing apparatus includes an input interface and a protocol decode agent that receives transmission signals through the input interface. The protocol decode agent generates testing stimuli for a SOC based on the transmission signals. The SOC testing apparatus further includes an output interface and a test vector generator that receives the testing stimuli from the protocol decode agent and supplies the testing stimuli as digital signals to the output interface. The protocol decode agent decodes the traffic received from the input interface. The protocol decode agent then determines the correct testing stimuli to be applied to the SOC. The protocol decode agent may be a software model of the IO protocol being used to interact with the DUT. The protocol decode agent may determine what type of protocol is included in the signals received from the SOC.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Paraag Vaishampayan, Mehul Sagar, Chong Yih Khoo
  • Patent number: 9385261
    Abstract: A solar cell and a method of manufacturing a solar cell are disclosed. The solar cell includes forming a first doped region of a first conductive type and a second doped region of a second conductive type opposite the first conductive type on a semiconductor substrate of the first conductive type; forming a passivation layer on the semiconductor substrate to expose a portion of each of the first and second doped regions; and forming a first electrode electrically connected to the first doped region and a second electrode electrically connected to the second doped region, wherein the forming of the first and second electrodes includes forming a metal seed layer directly contacting the first doped region and a metal seed layer directly contacting the second doped region, and forming a conductive layer on the metal seed layer of each of the first and second electrodes.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: July 5, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Sungeun Lee, Youngho Choe
  • Patent number: 9291673
    Abstract: A semiconductor apparatus includes: an output timing test unit configured to edge-trigger a pad output data applied from an input/output pad at a first timing and output the edge-triggered pad output data as output timing test data, during an output timing test mode, and a test output unit configured to receive the output timing test data and output the received output timing test data to a probe pad.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventor: Ki Up Kim
  • Patent number: 9291643
    Abstract: A current applying device is provided in which a contact body which surface-contacts with an inspection target body makes contact with the surface of the inspection target body uniformly; current can be favorably applied from the contact body to the inspection target body; and the contact body alone can be replaced. A probe device 1 for applying current by being in pressure-contact with the power semiconductor H includes: a contact body 2 which surface-contacts with the power semiconductor H; and a plurality of electrically-conductive two-tier springs 31 which press the contact body 2 onto the power semiconductor H; the contact body 2 and the plurality of electrically-conductive two-tier springs 31 are separate bodies, and the plurality of electrically-conductive two-tier springs 31 electrify the contact body 2 while providing pressing force F to each of a plurality of sections of the contact body 2.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 22, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Shigeto Akahori, Hiroyuki Yamagishi, Satoshi Hasegawa, Yoko Yamaji, Nobuo Kambara, Shinyu Hirayama
  • Patent number: 9276335
    Abstract: An electronic assembly includes a circuit board that serves as both a mechanical attachment point and signal conduit for electronic components. The circuit board includes at least two modular card connector assemblies disposed on opposing surfaces of a mounting region of the circuit board. Pin sets of the modular card connector assemblies are connected together via corresponding through holes extending between the opposing surfaces in the mounting region. Further, pins of one or both the modular card connector assemblies may be connected to other electronic components disposed at the circuit board via lateral traces. One or both of the modular card connector assemblies can comprise a modular card socket to removably couple with a modular card. Alternatively, one or both of the modular card connector assemblies comprises a pin interface assembly that is integral to or otherwise fixedly attached to the modular card.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 1, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jean-Philippe Fricker
  • Patent number: 9243894
    Abstract: A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift ?D between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift ?D is corrected (step S17).
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 26, 2016
    Assignee: BONDTECH CO., LTD.
    Inventor: Akira Yamauchi
  • Patent number: 9229041
    Abstract: An automatic test system includes a mechanical frame, a test device mounted to the mechanical frame for testing the electrical performance and the mechanical performance of the connector, a packing device mounted to the mechanical frame for packing the connector which is completed to be tested, a transmission device mounted to the mechanical frame for transmitting the connector to each workstation of the test device and the packing device, a moving device mounted to the mechanical frame for moving the connector to each workstation of the test device and the packing device corresponding to the transmission device, and a control system electrically connected with and controlling the test device, the packing device, the transmission device and the moving device for completing the transmission, test and packing action of the connector.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: January 5, 2016
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Han Wei Wang, Jung Kuang Liu
  • Patent number: 9164142
    Abstract: An approach is provided in which a system under test is subjected to thermal cycling that include transferring the system under test between two different environments that generate two different ambient temperatures. In turn, a test system tests the electronic assembly in response to the electronic assembly being subjected to the thermal cycles.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: October 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Marc Coq, Richard J. Fishbune
  • Patent number: 9153491
    Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Rickie C. Lake
  • Patent number: 9121901
    Abstract: An apparatus includes a plurality of test heads to which probe cards are electrically connected; a wafer tray which is able to hold a semiconductor wafer; and an alignment apparatus which positions the semiconductor wafer held on the wafer tray relatively with respect to the probe card so as to make the wafer tray face the probe card. The wafer tray has a pressure reducing mechanism which pulls the wafer tray toward the probe card. The alignment apparatus is configured to be able to move along the array direction of the test heads.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: September 1, 2015
    Assignee: ADVANTEST CORPORATION
    Inventors: Toshiyuki Kiyokawa, Takashi Naito
  • Patent number: 9099547
    Abstract: In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 4, 2015
    Assignee: Infineon Technologies AG
    Inventors: Stefan Martens, Mathias Vaupel
  • Patent number: 9058436
    Abstract: Methods, systems and circuits for reducing aging of at least one component of a data path are disclosed. First data transmitted over a data path may be monitored in an active state to allow generation of second data, where the second data may be transmitted in an inactive state over the data path to improve the balance of any imbalance in the static probability of one logical state versus another caused by transmission of the first data. Portions of data to be transmitted over a data path may be compared to previously-transmitted portions of data to determine a respective data bus inversion (DBI) setting each portion of data, where the DBI settings may be used to increase the toggling of bits of the data path and improve the balance of the static probability of one logical state versus another.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: June 16, 2015
    Assignee: ALTERA CORPORATION
    Inventors: Gordon Chiu, Navid Azizi
  • Patent number: 9055706
    Abstract: A method for integrating a component into a printed circuit board includes the following steps: providing two completed printed circuit board elements, which more particularly consist of a plurality of interconnected plies or layers, wherein at least one printed circuit board element has a cutout or depression, arranging the component to be integrated on one of the printed circuit board elements or in the cutout of the at least one printed circuit board element, and connecting the printed circuit board elements with the component being accommodated in the cutout, as a result of which it is possible to obtain secure and reliable accommodation of a component or sensor in a printed circuit board. Furthermore, a printed circuit board of this type comprising an electronic component integrated therein is provided.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: June 9, 2015
    Assignee: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Johannes Stahr, Markus Leitgeb
  • Patent number: 9046567
    Abstract: An equipment burn-in method, which includes the equipment undergoing treatment in an oven, the oven undergoing cycles including at least one temperature-rise and/or temperature-fall transition, for which ventilation of the equipment is cut off during at least part of a temperature transition of the oven.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: June 2, 2015
    Assignee: AIRBUS OPERATIONS S.A.S.
    Inventor: Stephane Ortet
  • Patent number: 9024647
    Abstract: A method includes performing a burn-in test on an integrated circuit (IC) by removing power from a first component block within the IC and applying a maximum burn-in voltage and temperature to a second component block within the IC.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Arman Vassighi, Victor Zia
  • Patent number: 9000789
    Abstract: A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits, loading test software into the test circuits, performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software, and removing the plurality of semiconductor apparatuses, which have completed the self-tests, from the first test board. Upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-sik Kim, Kil-yeon Kim, Yun-bo Yang, Kui-hyun Ro, Heon-gwon Lee, Young-jae Jung
  • Publication number: 20150061711
    Abstract: An invention employing testing, e.g., overclocking, to determine undesirable conditions in a device under test (DUT) is provided. An exemplary apparatus and method includes artificially aging a known sample microelectronic device (SMD); overclocking the known SMD to specification and/or maximum performance; and collecting a plurality of device data associated with overclocking of each SMD at multiple ageing data points over a predicted aging progression. Another exemplary next step includes overclocking a DUT and collecting device data associated with the overclocked DUT. Another exemplary next step includes comparing the DUT device data with SMD device data to determine, for example, if the DUT has an anomaly or undesirable condition, if the DUT conforms to a manufacturer's specification, if the DUT was made by an original equipment manufacturer, if the DUT is used but represented as new, and/or the DUT has been subjected to damage or stress events exceeding acceptable limits.
    Type: Application
    Filed: August 4, 2014
    Publication date: March 5, 2015
    Inventor: Brett Hamilton
  • Publication number: 20150028908
    Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: Advantest Corporation
    Inventors: Eric KUSHNICK, Mei-Mei SU, Roland WOLFF
  • Patent number: 8937482
    Abstract: Apparatus and method adapted for use with an optionally pre-conditioned air supply that is pressurized, for ramping a component to a temperature setpoint, having a vortex tube, a ventilated mount connected to the vortex tube, a pedestal adapted for thermal connection with the component, and a heat exchanger thermally connected with the pedestal and extending within an inward hollowed and enclosed chamber of the ventilated mount, the chamber having wall thickness and size and having a plurality of smaller apertures, or a single larger aperture, therein, and optionally baffling, so as to be adapted for regulating the airflow through the chamber for effectively ramping the temperature of the component and to maximize noise abatement performance.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 20, 2015
    Assignee: Sensata Technologies, Inc.
    Inventor: Tom Lemczyk
  • Publication number: 20140375345
    Abstract: An burn-in socket electrically connecting an IC package to a PCB, comprises a base, a cover, a plurality of contacts and a block-shaped heat sink. The base defines a receiving space for the IC package. The cover is pin-jointed to one side by a pivot of the base and able to rotate around the pivot. A plurality of contacts are retained in the base and partially exposed in the receiving space. The heat sink is located above the IC package and against to the IC package so as to apply its gravity force to the IC package. Top face of the heat sink is below top face of the cover.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 25, 2014
    Inventor: WEI-CHIH LIN
  • Publication number: 20140354313
    Abstract: A method for temporary electrical contacting of a component arrangement with a plurality of contact surfaces is described. A connection support includes a plurality of connection surfaces, on which contact protrusions are disposed. The connection support and component arrangement are brought together in such a way that the connection surfaces and the associated contact surfaces overlap in a top view and the contact protrusions form an electrical contact with respect to the contact surfaces in order to achieve electrical contacting of the component arrangement. Subsequently the connection support and the component arrangement are separated from each other.
    Type: Application
    Filed: September 12, 2012
    Publication date: December 4, 2014
    Applicant: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Kuehnelt, Roland Enzmann
  • Patent number: 8896335
    Abstract: An apparatus controls a temperature of a device by circulating a fluid through a heat sink in thermal contact with the device. The apparatus includes an adjustable cold input, which inputs a cold portion of the fluid having a first temperature, and an adjustable hot input, which inputs a hot portion of the fluid having a second temperature higher than the first temperature. The apparatus further includes a chamber, connected to the cold input and hot input, in which the cold and hot portions of the fluid mix in a combined fluid portion that impinges on the heat sink. The combined fluid portion has a combined temperature that directly affects a temperature of the heat sink. The cold input and hot input are adjusted to dynamically control the combined temperature, enabling the heat sink temperature to compensate for changes in the device temperature, substantially maintaining a set point temperature of the device.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: November 25, 2014
    Assignee: Advantest Corporation
    Inventors: Larry Stuckey, Anastasios Golnas, Robert Edward Aldaz, David Yu