Abstract: A burn in board test device including: a plurality of devices under test, wherein each of the devices under test includes a burn in device; a plurality of resistors connected to each of the plurality of devices under test; a plurality of device under test switches connected to each of the plurality of resistors; and a device under test tester which is connected a plurality of sub input/output (I/O) channels connected to each of the plurality of device under test switches, and a main I/O channel for connecting the plurality of sub I/O channels to each other to test the plurality of devices under test.

Abstract: A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT; a lid member that covers the DUT and is attached to the carrier body; and an identifier for identifying an individual of the test carrier.

Abstract: The transmission and reception group delay in a front end structure of a mobile device may be determined using closed loop calibration. The closed loop may be a near field radiated closed loop between pairs of antennas in an antenna array of the mobile device. The delay based on time of transmission and time of reception may be measured for a plurality of pairs of antennas, from which the transmit and receive group delay within a single path may be determined. The propagation delay of the signal between antennas may be included in the group delay calibration for increased accuracy. In another implementation, a conducted closed loop, e.g., in the transceiver or in a radio frequency switching network may be used to calibrate the group delay. Pre-characterization of the delay caused by components between the closed loop and antennas may be included in the group delay calibration for increased accuracy.

Abstract: A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Abstract: A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

Abstract: A tester apparatus is described. Various components contribute to the functionality of the tester apparatus to facilitate movement of a wafer pack holding a vacuum without human oversight. These functionalities include a latch system to keep the wafer pack intact and a pressure sensing system to detect and relay a pressure in the wafer pack.

Abstract: A real-time clock device includes a package that houses a resonator, an oscillation circuit, a clocking circuit, and a functional circuit, and on which external terminals are formed.

Abstract: The present disclosure related to a stacker of an electric device test hander comprising an upper stacker and a lower stacker. Stacker modules provided in the upper stacker can be opened and closed by being moved horizontally from the frame, and each of stacker modules can give and receive a plurality of user trays to and from the lower stacker in closed position. According to present disclosure when goods are being transferred to and from the outside, the user trays can move freely between the loading parts disposed on the upper and lower sides. Thus, the dependence on the visitation cycle of an external robot and the replacement amounts of the user trays can be lowered to improve ease of operation.

Abstract: A two part patient monitoring device includes an activator module and a sensor device. The activator module includes a non-galvanic data port that creates a communication path with a non-galvanic data port on the sensor device. The activator module includes power contact pads that are each at least partially surrounded by a bias ring. A bias voltage is applied to the bias rings and a processor or circuit in the activator module monitors the voltage on the bias ring to detect a leakage current. The sensor module includes power contact pins that engage the power contact pads to transfer power from the activator module to the sensor device. Each of the contact pins are surrounded by a seal member such that the connection between the power contact pins and the power contact pads is protected from debris and/or moisture.

Abstract: The present application provides a testing system. The testing system includes a chip socket and a probe. The chip socket includes a pedestal and a fastener. The pedestal is configured to accommodate a chip to be tested. The fastener includes a top body and a base body. The top body includes a probing window surrounded by a plurality of side walls, wherein the probing window has a first end at an outer surface of the top body and a second end at an inner surface of the top body, a first angle between a first side wall of the plurality of side walls and the outer surface is less than 90 degrees, and a first opening area at the first end of the probing window is larger than a second opening area at the second end of the probing window.

Abstract: A method of testing a semiconductor package is provided. The method includes forming a first metallization layer, wherein the first metallization layer includes a first conductive pad electrically connected to a charge measurement unit and a charge receiving unit; performing a first test against the charge measurement unit through the first conductive pad to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer, wherein a portion of the first conductive pad is exposed from the second dielectric layer.

Abstract: An example test system includes a test socket for testing a DUT, a lid for the test socket, and an actuator configured to force the lid onto the test socket and to remove the lid from the test socket. The actuator includes an upper arm to move the lid, an attachment mechanism connected to the upper arm to contact the lid, where the attachment mechanism is configured to allow the lid to float relative to the test socket to enable alignment between the lid and the test socket, and a lower arm to anchor the actuator to a board containing the test socket. The actuator is configured to move the upper arm linearly towards and away from the test socket and to rotate the upper arm towards and away from the test socket.

Abstract: A method includes providing a test structure above a tester, wherein the test structure includes a load board including a first and second connectors, a first socket electrically connected to the first and second connectors of the load board, and a second socket electrically isolated from the first connector of the load board and electrically connected to the second connector of the load board. A first and second semiconductor dies are disposed respectively on the first and second sockets. A test signal to the first semiconductor die and the second semiconductor die through the second connector of the load board are simultaneously applied by using the tester. A first signal of the first semiconductor die through the first connector is read by using the tester. Whether the first semiconductor die is disturbed by the second semiconductor die is determined according to the first signal.

Abstract: Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances.

Abstract: A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.

Abstract: A mechanism is provided for automatically detecting, diagnosing, transporting, and repairing devices having failed during burn-in testing. Embodiments provide a system that monitors devices undergoing burn-in testing and detecting when a device or a component within a device fails the burn-in test. Embodiments can then alert burn-in-rack monitor personnel of the device failure. Embodiments can concurrently determine the nature of the failure applying a machine learning-based prediction model against log files associated with the failed device. The diagnosis along with a recommended repair strategy can be provided to the repair center as an aid in accelerating the repair process. In addition, the diagnosis can be used to order parts for the repair from a parts depot. In this manner, embodiments can reduce the time for detection, diagnosis, and repair of the failed device.

Abstract: A device maintenance apparatus includes a test executor configured to cause a device to output an output signal based on a test pattern that changes the output signal output from the device with an elapse of time, and a change instructor configured to issue a change instruction for changing at least one of a progress of an output of the output signal based on the test pattern and an output value of the output signal to the test executor in accordance with an instruction input while the test executor causes the device to execute the output of the output signal.

Abstract: A burn-in board management system includes a production burn-in apparatus and a burn-in board status computer. The production burn-in apparatus is configured to test a plurality of integrated circuit devices mounted in slots of a burn-in board and comprising a first controller configured to generate a first burn-in board status map, wherein the first controller is further configured to suspend the burn-in board when the first burn-in board status map of the burn-in board demonstrates that more than a threshold percentage of the slots of the burn-in board are determined to be malfunctioned. The burn-in board status computer is communicably connected with the first controller of the production burn-in apparatus and configured to receive the first burn-in board status map.

Abstract: A system includes a platform and a contactor. The platform has a side configured to support a frame with a carrier structure and electronic devices each having first and second sides and a terminal, the first side positioned on the carrier structure, and the terminal exposed in a first portion of the second side. The contactor has first and second sides, a contact and a heater. The contact is exposed on the first side of the contactor to contact the terminal in a first portion of the second side of a selected one of the electronic devices, and the heater is exposed on the first side of the contactor to apply heat to a second portion of the second side of the selected one of the electronic devices.

Abstract: A circuit measuring device and a method thereof are provided. A voltage source supplies a common voltage such that a calibration current having a preset current value flows from a current-voltage converter to a final test machine. The current-voltage converter converts the calibration current into a calibration voltage. At this time, a voltage sensing component senses a voltage between an input terminal and an output terminal of the current-voltage converter to output sensed calibration data. The current-voltage converter converts a tested current outputted by a tested circuit into a tested voltage. At this time, the voltage sensing component senses the voltage between the input terminal and the output terminal of the current-voltage converter to output actual sensed data. When the final test machine determines that a difference between the sensed calibration data and the actual sensed data is larger than a threshold, the tested circuit is adjusted.

Abstract: This invention provides a method for mounting an electroacoustic component on a PCB and an electroacoustic component structure, so as to improve the problem that the traditional electroacoustic component affects the electrical characteristics due to the high temperature baking action in a reflow oven. The method comprises a step of separating and constructing a housing of the electroacoustic component. The housing comprises a shell seat and a base seat, the shell seat is provided with a plurality of sound producing components, and the base seat is provided with at least two conducting terminals for adhering the base seat to the PCB. The conducting terminals on the base seat and the at least two contacts on the PCB are adhered to each other and electrically connected in the reflow oven, and then the shell seat and the base seat are combined to make the shell seat and the base seat with the PCB combined outside the reflow oven into a single body to form an electroacoustic component that is mounted on the PCB.

Abstract: Heat spreaders for use in semiconductor device testing, such as burn-in testing, are disclosed herein. In one embodiment, a heat spreader is configured to be coupled to a burn-in testing board including a plurality of sockets. The heat spreader includes a base portion and a plurality of protrusions extending from the base portion. When the heat spreader is coupled to the burn-in testing board, the protrusions are configured to extend into corresponding ones of the sockets to thermally contact semiconductor devices positioned within the sockets. The heat spreader can promote a uniform temperature gradient across the burn-in board during testing of the semiconductor devices.

Abstract: A chip tray kit and a chip testing apparatus are provided. The chip testing apparatus includes the chip tray kit. The chip tray kit includes a tray, a plurality of chip fixing members, and a plurality of auxiliary insertion members. The tray includes a plurality of tray thru-holes, the chip fixing members are detachably fixed to the tray, and the chip fixing members are correspondingly arranged in the tray thru-holes. Each of the auxiliary insertion members is detachably fixed to a side of the chip fixing member, a portion of each of the auxiliary insertion members is arranged in a fixing thru-hole of the chip fixing member, and each of the auxiliary insertion members can limit a movement range of a chip in a chip accommodating slot of the chip fixing member.

Abstract: A burn-in board capable of realizing a uniform temperature distribution inside a burn-in board is provided. A burn-in board includes: a plurality of sockets; a burn-in board body including an upper surface for mounting the sockets thereon and a lower surface on the side opposite to the upper surface; a reinforcement frame contacting the lower surface; a bottom cover contacting the reinforcement frame; a heat conduction plate interposed between the burn-in board body and the bottom cover; and a heat conduction sheet thermally connecting the burn-in board body to the heat conduction plate, in which the reinforcement frame presses the heat conduction plate toward the heat conduction sheet.

Abstract: A feedback burn-in device of a burn-in oven includes at least one burn-in rack disposed in the burn-in oven, at least one burn-in board, and at least one feedback burn-in unit. The burn-in rack is formed, in a top thereof, with at least one horizontal ventilation passage in communication with an interior of the burn-in rack. The horizontal ventilation passage has an end connected to at least one negative pressure zone or heat dissipation blower of the burn-in oven. The burn-in board is disposed in the interior of the burn-in rack. The burn-in board is connected to a socket to which at least one tested IC is connectable. The feedback burn-in unit is connected to the socket and the burn-in board.

Abstract: A testing equipment includes a testing platform and a component carrying device including a carrying arm, a vacuum suction unit, a working bottom cover and a fluid transmission assembly. The carrying arm lifts and carries a device under test (DUT) onto the testing platform. The vacuum suction unit removably sucks to the DUT. The working bottom cover includes a cover body and an elastic airtight ring. The cover body is connected to the carrying arm, and the elastic airtight ring is fixedly disposed on the cover body for hermetically covering the DUT, so that a liquid filling space is collectively formed by the cover body and the DUT. The fluid transmission assembly extends into the liquid filling space for continuously passing a working liquid to the DUT and withdrawing the working liquid back away from the liquid filling space for thermally exchanging with the DUT.

Abstract: Embodiments include a method of stress testing an electronics package with components that include a visual indicator. In an embodiment, the method comprises populating a plurality of components on an electronics package. In an embodiment, the plurality of components each comprise a visual indicator that is responsive to heat. In an embodiment, the method further comprises stress testing the electronics package and categorizing the plurality of components based on the visual indicators. In an embodiment, the method may further comprise modifying the plurality of components.

Abstract: An electronic component presser is included in an electronic component testing apparatus used to test a device under test (DUT). The electronic component testing apparatus includes an electronic component handler, an electronic component tester, and a first socket. The electronic component presser connects to the electronic component handler and to the electronic component tester. The electronic component presser includes: a holding plate that holds the DUT that has been carried to the holding plate by a contact arm of the electronic component handler; a transport unit that moves the DUT between the holding plate and the first socket; a pusher that presses the DUT that has been disposed on the first socket; and an antenna unit comprising a measurement antenna that faces a device antenna of the DUT disposed on the first socket.

Abstract: Techniques and mechanisms for mitigating damage to voltage regulator (VR) circuitry of a packaged device. In an embodiment, the VR circuitry comprises a circuit leg between a first node and a second node. During a burn-in process, the VR circuitry provides a regulated output voltage to a load circuit via the first node, wherein the output voltage is based on a supply voltage received via the second node. While the VR circuitry provides the regulated output voltage to the load circuit, a supply current is provided to the load circuit via a path which is independent of any leg which is between the first node and the second node. In another embodiment, an integrated circuit (IC) chip of the packaged device comprises the load circuit, and the leg further comprises an off-chip coil structure which is distinct from the IC chip.

Abstract: A process and system for testing includes: arranging devices in a temperature-controlled environment; applying a negative gate bias voltage (Vgs) to the devices; applying a drain voltage (Vds) to the devices; measuring currents and/or voltages of the devices to generate device test data; determining a failure of one or more of the devices based on the device test data generated from the device currents and/or the voltages to generate failure data; and outputting the failure data for the of devices.

Abstract: A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.

Abstract: An electrical-test apparatus is provided, which includes a plurality of tester interconnect structures cantilevered from a first side of a substrate. A base may be coupled to a second side of the substrate via one or more interconnect layers. The tester interconnect structures may contact corresponding interconnect structures of a device under test (DUT). In an example, the substrate is laterally movable relative to the DUT along a plane of the substrate, upon contact between the tester interconnect structures and the interconnect structures of the DUT.

Abstract: An ID chip socket according to an embodiment disclosed herein includes: a contactor configured to be fixed to an upper side of the frame; a socket-conductive part penetrating the contactor in a vertical direction and configured to enable electrical connection in the vertical direction; an ID chip fixed to an upper side of the socket-conductive part and electrically connected to the socket-conductive part; and a cover configured to cover an upper surface of the ID chip and to be fixed to at least one of the contactor and the frame.

Abstract: An apparatus for burning in electronic components, which includes a plurality of assemblies placed in a holder, each assembly comprising a printed circuit board on which are placed sockets intended to receive electronic components and a burn-in driver. The holder is at room temperature, and each assembly comprises a single chamber that is regulated to a temperature T°>80° C., in which chamber at least four sockets are placed. The printed circuit board forming one wall of the chamber, the burn-in driver is soldered directly to the printed circuit board on the side exterior to the chamber, with a single burn-in driver per chamber, and the assembly furthermore comprises means for dissipating only the thermal energy of operation of the burn-in driver.

Abstract: A method for assessing reliability of an electronic component under downhole vibration conditions include designing a set of vibration test conditions and conduct failure analysis. The vibration test conditions include the natural vibration frequency, the overstress limit of the test vehicle, and the step stress profile for testing the test vehicle. The failure analysis of the failed electronic component includes the step of measuring an electrical resistance of the failed electronic component without a vibration load. When the electrical resistance of the failed electronic component remains large, the failed electronic component is cross-sectioned. Finally, the cross-sectioned electronic component is examined to identify a failure mode.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: There is provided a substrate inspection apparatus capable of inspecting the electrical characteristics of a packaged semiconductor device in a mounting environment. A prober includes a test box, a probe card and a package inspection card. A packaged device is attached to the package inspection card. A test board of the test box and a card board of the package inspection card reproduce the mounting environment in which a wafer-level system-level test is performed.

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Abstract: Techniques (implemented in circuit arrangements, methods, computer instructions) are disclosed which permit digital pre-distortion for amplifiers. A common signal source provides a common analog signal from a digital input signal; a plurality of amplifiers amplifies a split signal which is a split version of the common analog signal; a built-in test circuit is configured to provide distortion information associated to distortion affecting the amplifier. The common signal source implements a signal conditioner to perform, in a signal path of the digital input signal, a feed-forward pre-distortion of the digital input signal according to a pre-distortion relationship mapping the digital input signal onto a pre-distorted version. The signal conditioner is configured to adjust the pre-distortion relationship in dependence on the distortion information.

Abstract: A production process analysis method for stabilizing the quality of the products or services. A production process analysis method includes: a step for identifying a good lot included in a group determined to be the most excellent with respect to each of a plurality of states constituting a production process; a step for classifying, in the case where at least one good lot is not shared among the plurality of states, the plurality of states into an arbitrarily selected selection state and other non-selection states, and determining again a highest-ranking group in the non-selection state that includes the good lot in the selection state as the most excellent group; and a step for identifying factors that characterize the group determined as the most excellent.

Abstract: A test adapter apparatus comprising at least one device under test, DUT, holder adapted to hold a device under test, DUT and adapted to be plugged in into a docking station of said test adapter apparatus, wherein the docking station has RF and data interfaces used for connecting at least one external test device through said docking station with the device under test, DUT, held by said device under test holder.

Abstract: A method for testing a network device using a variable traffic burst profile includes providing for user selection of at least one type of simulated traffic to be transmitted to a network device under test (DUT). The method further includes receiving user input regarding selection of the type of simulated traffic. The method further includes providing for user selection of a transmission rate for transmitting the simulated traffic to the DUT. The method further includes receiving user input regarding selection of the transmission rate. The method further includes transmitting the simulated traffic to the DUT according to the selected traffic type, the selected transmission rate, and a variable traffic burst profile.

Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

Abstract: A method of testing a device under test, the device under test comprising a scan chain having a number of storage elements. The method determines a representation of toggling events in a test sequence, where the test sequence is for testing the scan chain. The method also selectively times input of a bit sequence, corresponding to the test sequence, to a first storage element in the number of storage elements, and through the scan chain, in response to the determining step.

Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

Abstract: Aspects of the embodiments are directed to a microfluidic chip and methods of making the same. The microfluidic chip can include a sensor device residing on the microfluidic chip, the sensor-side comprising a chemical sensor and the backside including a backside electrode, the chemical sensor electrically coupled to the backside electrode by a via; a microfluidics channel in the microfluidic chip, the sensor-side of the sensor device facing the microfluidics channel; and a metal contact electrically connected to the backside electrode.

Abstract: Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Abstract: In one or more embodiments, one or more systems, methods, and processes determine an address of a memory medium of an information handling system associated with an exception; determine respective address spaces of the device drivers loaded in the memory medium; determine an address space of address spaces that includes the address associated with the exception; determine a device driver of the device drivers based at least on the address space; query the device driver for an identification of the device driver; determine if the device driver provides the identification of the device driver; if the device driver provides the identification of the device driver, output the identification of the device driver and exception information associated with the exception; and if the device driver does not provide the identification of the device driver, search for identification information of the device driver within the address space.

Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.

Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.