Semiconductor Wafer Patents (Class 324/762.05)
  • Patent number: 10809294
    Abstract: A drive unit of a stage device includes a boxy body having a rectangular shape in a plan view, a base, a pair of X-axis linear motors, and a pair of Y-axis linear motors. An X-axis stator is disposed on each of two mutually opposing X-axis-direction side walls of the boxy body, wherein magnetic attractions that draw respective X-axis rotors toward the X-axis stator side (Y-axis direction) cancel out each other between the pair of X-axis linear motors. A Y-axis stator is disposed on the inside of each of two mutually opposing Y-axis wall members, wherein magnetic attractions that draw respective Y-axis rotors toward the Y-axis stator side (X-axis direction) cancel out each other between the pair of Y-axis linear motors.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 20, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tomoya Endo
  • Patent number: 10761133
    Abstract: A crack detection system and an apparatus equipped with a crack detection circuit, including a main body, and a detection control circuit and a detection coil disposed on the main body. The main body includes a top surface, a bottom surface, and a side surface coupled between the top surface and the bottom surface. The detection coil is distributed on an edge of the main body and disposed surrounding the side surface. Two ends of the detection coil are electrically coupled to the detection control circuit to form a closed-loop detection circuit. The detection circuit is configured to detect a crack in an edge region of the main body. The detection coil includes a plurality of detection sections sequentially coupled from head-to-tail, and adjacent detection sections are not collinear.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: September 1, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Si, Haohui Long, Jianping Fang, Runqing Ye, Weiqiang Hong, Yunfei Wang, Taixiang Liu
  • Patent number: 10629588
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Patent number: 10496505
    Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 3, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsuan Hsu, Ying-Yen Chen, Cheng-Yan Wen, Chia-Tso Chao, Jih-Nung Lee
  • Patent number: 10418474
    Abstract: A high electron mobility transistor (HEMT) includes a semiconductor structure including a cap layer and a channel layer forming a heterojunction, such that a two dimensional electron gas is formed at the interface of cap layer and the channel layer. The HEMT also includes a set of electrodes including a source electrode, a drain electrode, and a gate electrode deposited on the cap layer. The gate electrode is arranged between the source and the drain electrode along the length of the HEMT. The thickness of the cap layer at least under the gate electrode is varying along the width of the HEMT.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 17, 2019
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Nadim Chowdhury
  • Patent number: 10340127
    Abstract: Systems and methods for determining wafer bias are described. One of the methods includes detecting output of a generator to identify a generator output complex voltage and current (V&I). The generator is coupled to an impedance matching circuit and the impedance matching circuit is coupled to an electrostatic chuck (ESC). The method further includes determining from the generator output complex V&I a projected complex V&I at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC. The operation of determining of the projected complex V&I is performed using a model for at least part of the path. The method includes applying the projected complex V&I as an input to a function to map the projected complex V&I to a wafer bias value at the ESC model.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 2, 2019
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker
  • Patent number: 10290477
    Abstract: Systems and methods of monitoring a discharge in a plasma process are disclosed. The methods include supplying the plasma process with a periodic power supply signal, determining a first signal waveform in a first time interval within a first period of the power supply signal, determining a second signal waveform in a second time interval within a second period of the power supply signal, the second time interval being at a position within the second period corresponding to a position of the first time interval within the first period, comparing the second signal waveform with a reference signal waveform to obtain a first comparison result, determining that the first comparison result corresponds to a given first comparison result, and in response, time-shifting one of the second signal waveform and the reference signal waveform, and comparing the time-shifted signal waveform with the non-time-shifted signal waveform to obtain a second comparison result.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 14, 2019
    Assignee: TRUMPF Huettinger Sp. z o. o.
    Inventors: Andrzej Gieraltowski, Adam Grabowski, Piotr Lach, Marcin Zelechowski
  • Patent number: 10041994
    Abstract: A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 7, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Wei-Ting Chien, Yueqin Zhu, Yongliang Song, Yong Zhao
  • Patent number: 10026661
    Abstract: Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyosig Won, DaiJoon Hyun, Kwangok Jeong
  • Patent number: 9960770
    Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: May 1, 2018
    Assignee: SK hynix Inc.
    Inventors: Jeong Tae Hwang, Jin Youp Cha, Young Sik Heo
  • Patent number: 9939486
    Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jifeng Chen, Dirk Pfeiffer, Thomas M. Shaw, Peilin Song, Franco Stellari
  • Patent number: 9874601
    Abstract: Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jifeng Chen, Dirk Pfeiffer, Thomas M. Shaw, Peilin Song, Franco Stellari
  • Patent number: 9811627
    Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chin Hou, Sandeep Kumar Goel, Yun-Han Lee
  • Patent number: 9719870
    Abstract: A read circuit of an electrical signal produced by a POSFET device comprising a transconductance amplifier connected at an inverting input thereof to the output of the POSFET device; and at least one neuron connected at the output to the transconductance amplifier. The transconductance amplifier is adapted to: receive a signal coming from the POSFET device representative of a force or pressure exerted on the POSFET device, and produce at the output at least one current signal representative of the force or the pressure. The at least one neuron is adapted to receive said at least one current signal and to produce at least one output signal, said at least one output signal being a pulse train having a frequency proportional to said at least one current signal produced by the transconductance amplifier.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 1, 2017
    Assignee: FONDAZIONE ISTITUTO ITALIANO DI TECNOLOGIA
    Inventors: Stefano Caviglia, Chiara Bartolozzi, Maurizio Valle
  • Patent number: 9703919
    Abstract: A method of generating a set of defect candidates for a wafer is disclosed. The wafer comprises at least one die manufactured according to a mask, and the mask being prepared by combining a plurality of layout areas. The method includes receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer and determining a boundary region on the semiconductor wafer. The method further includes creating an exclusion region from the boundary region, the exclusion region having a first set of defects in the potential defects of the semiconductor wafer, and creating filtered defect information by removing the first set of defects from the initial defect information.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsin Hsieh, Tsung-Hsien Lee
  • Patent number: 9612259
    Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 4, 2017
    Assignee: Translarity, Inc.
    Inventors: Aaron Durbin, David Keith, Morgan Johnson
  • Patent number: 9564376
    Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Cheng Tsao, Cheng-Hung Wang, Chun-Chieh Lin, Hsiu-Hsiung Yang, Yu-Pin Tsai
  • Patent number: 9535090
    Abstract: An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe board spaced from the wiring base plate with a first surface thereof opposed to the wiring base plate and having a wiring path corresponding to the wiring path and probes provided on a second surface of the probe board to be connected to the wiring path and enabling to respectively contact connection pads of a semiconductor wafer on the chuck top, and an electric connector connecting the wiring base plate to the probe board by low heat conduction supporting members and decreasing heat conduction therebetween and electrically connecting the wiring paths.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Tatsuo Inoue, Hidehiro Kiyofuji, Osamu Arai
  • Patent number: 9404940
    Abstract: An adapter as disclosed herein includes at least one transmission path providing an electrical connection between the probing end and the head connection end. The adapter includes a flexible tab-board adapter associated with the probing end of the transmission path, the flexible tab-board adapter for contacting at least one signal testing point. The adapter may further include at least one compensating network positioned substantially near the probing end, the at least one compensating network configured to compensate for parasitics of the adapter.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: August 2, 2016
    Assignee: TELEDYNE LECROY, INC.
    Inventors: Julie A. Campbell, Lenny Rayzman, Albert Sutono
  • Patent number: 9230871
    Abstract: A test key structure includes a plurality of transistors formed on a scribe line of a wafer and arranged in a 2*N array having 2 columns and N rows. The transistors arranged in the 2*N array respectively includes a gate, a source, a drain, and a body. All of the sources of the transistors arranged in the 2*N array are electrically connected to each other.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Kuo Wang, Chun-Liang Hou, Wen-Jung Liao
  • Patent number: 9087805
    Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: James V. Crain, Jr., Mark C. H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw, David B. Stone
  • Patent number: 9075107
    Abstract: A method for accurately determining the sheet resistance and leakage current density of a shallow implant in a semiconductor substrate surface includes making one or more four-point resistance measurements with an induced current below 100 ?A on the semiconductor surface with a plurality of electrode spacing sets, at least one set defining an electrode separation distance less than 100 ?m. The sheet resistance and implant leakage are determined through fitting the measured data to theoretical data to within a predetermined error margin.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: July 7, 2015
    Assignee: Capres
    Inventor: Christian L. Petersen
  • Patent number: 9041424
    Abstract: The wafer inspection interface 18 includes a probe card 20 having a multiple number of probes 25; a fixing ring 21 configured to hold the probe card 20; a chuck top 23 disposed to face the probe card 20 with a wafer W therebetween; an outer seal ring 24 provided to hermetically seal an outer space 27 surrounded by the fixing ring 21, the probe card 20 and the chuck top 23; an outer depressurization path 29 through which the outer space 27 is depressurized; an inner seal ring 26 provided to hermetically seal an inner space 28 surrounded by the probe card 20 and the wafer W; and an inner depressurization path 30 through which the inner space 28 is depressurized. Further, the inner space 28 may be surrounded by the outer space 27, and the wafer W is disposed within the inner space 28.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: May 26, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroshi Yamada
  • Publication number: 20150115994
    Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
  • Patent number: 9003249
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9000785
    Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics SA
    Inventors: Clement Charbuillet, Patrick Scheer
  • Patent number: 9000798
    Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Long Chen, Chien-Chih Liao, Tseng Chin Lo, Hui-Yun Chao, Ta-Yung Lee, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20150084668
    Abstract: A semiconductor device includes a test control unit suitable for activating an on-die termination signal in response to a control signal activated in a test mode, and a data mask pad suitable for pull-down driving a data mask signal when the on-die termination signal is activated.
    Type: Application
    Filed: December 4, 2013
    Publication date: March 26, 2015
    Applicant: SK hynix Inc.
    Inventor: Jae Woong YUN
  • Patent number: 8988097
    Abstract: A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 24, 2015
    Assignee: RF Micro Devices, Inc.
    Inventor: Andrew P. Ritenour
  • Patent number: 8975910
    Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Benjamin A. Himmel, Chandrasekharan Kothandaraman, Norman W. Robson
  • Patent number: 8970240
    Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 3, 2015
    Assignee: Cascade Microtech, Inc.
    Inventors: Kenneth R. Smith, Mike Jolley, Eric Strid, Peter Hanaway, K. Reed Gleason, Koby L. Duckworth
  • Publication number: 20150048862
    Abstract: A method and apparatus for detecting substrate arcing and breakage within a processing chamber is provided. A controller monitors chamber data, e.g., parameters such as RF signals, voltages, and other electrical parameters, during operation of the processing chamber, and analyzes the chamber data for abnormal spikes and trends. Using such data mining and analysis, the controller can detect broken substrates without relying on glass presence sensors on robots, but rather based on the chamber data.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 19, 2015
    Inventors: Shuo NA, Kelby YANCY, Chunsheng CHEN, Ilias ILIOPOULOS
  • Patent number: 8952716
    Abstract: A method of detecting a defect of a semiconductor device includes forming test patterns and unit cell patterns in a test region a cell array region of a substrate, respectively, obtaining reference data with respect to the test patterns by irradiating an electron beam into the test region, obtaining cell data by irradiating the electron beam into the cell array region, and detecting defects of the unit cell patterns by comparing the obtained cell data with the obtained reference data.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Min Cho, Dong-Ryul Lee
  • Patent number: 8947118
    Abstract: In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Ronald Andrew Michallick, Michael Nolan Jervis, Rex Warren Pirkle
  • Patent number: 8941401
    Abstract: A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: January 27, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Publication number: 20150015299
    Abstract: Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces.
    Type: Application
    Filed: June 19, 2014
    Publication date: January 15, 2015
    Inventor: Morgan T. Johnson
  • Patent number: 8932884
    Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Noah D. Zamdmer
  • Patent number: 8928346
    Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: January 6, 2015
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SAS
    Inventors: Sergio Tenucci, Alberto Pagani, Marco Spinetta, Bernard Ranchoux
  • Patent number: 8922227
    Abstract: Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor Inc.
    Inventors: Chad S. Dawson, Bernhard H. Grote, Woo Tae Park
  • Patent number: 8907697
    Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: December 9, 2014
    Assignee: Teseda Corporation
    Inventors: Jack Frost, Joseph M. Salazar
  • Patent number: 8901949
    Abstract: There is provided a probe card comprising a plurality of probe tips, each being ball-shaped or pillar-shaped and having a top end in contact with each of target chip pads to be tested; a first space converting unit; a second space converting unit; a frame configured to support the second space converting unit; an interposer unit; and a circuit board.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Gigalane, Co., Ltd.
    Inventors: Duk Kyu Kwon, Kyu Han Lee, Yong Goo Lee
  • Patent number: 8896338
    Abstract: A method for characterizing the electronic properties of a semiconductor sample by exploiting transients in measured photoconductance, the transients being induced by illuminating the semiconductor sample with a small probing illumination that is superimposed over a larger background illumination. In one embodiment, a pulse-type probing illumination is utilized, with either the intensity of the probing illumination being gradually reduced or the intensity of the background illumination being gradually increased until the measured photoconductance rise and decay in the sample are substantially exponential. In another embodiment, a continuous probing illumination with a sinusoidally-modulated intensity is utilized, the modulated intensity of the probing illumination being gradually adjusted until the measured photoconductance is linearly dependent thereupon.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: November 25, 2014
    Inventor: Emil Kamieniecki
  • Patent number: 8896339
    Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Jun Takaso
  • Patent number: 8890560
    Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventor: Erdem Kaltalioglu
  • Patent number: 8880967
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8872536
    Abstract: An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Babak Ehteshami
  • Patent number: 8866507
    Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Jibin Zou, Runsheng Wang, Jiewen Fan, Changze Liu, Yangyuan Wang
  • Patent number: 8851358
    Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Tomokazu Saito, Seito Moriyama
  • Patent number: 8847615
    Abstract: A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 30, 2014
    Assignee: Shanghai Xinhao (Bravechips) Micro Electronics Co. Ltd.
    Inventors: Kenneth ChengHao Lin, Hongxi Geng, Haoqi Ren, Bingchun Zhang, Changchun Zhen
  • Patent number: 8841933
    Abstract: A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: Oliver D. Patterson