Abstract: A wafer inspection device, which inspects the electrical properties of a semiconductor wafer on which a semiconductor integrated circuit is formed, and the wafer inspection device has: a holding mechanism for holding a probe card; a wafer stage that holds the semiconductor wafer on the upper surface and is movably provided; and a pressing mechanism that are held and press the wafer stage against the probe card. The wafer stage is provided on the outer periphery with a seal ring. The seal ring forms a sealed space in a state where the wafer and the probe card are brought close to each other by contacting the probe card and is provided in such a manner as to reduce the pressure of the sealed space.

Abstract: A wafer test probe for testing integrated circuitry on a die is disclosed. The wafer test probe includes a membrane core. The wafer test probe also includes circuitry within the membrane core. The circuitry within the membrane core includes at least one portion of an inductor. The wafer test probe further includes a probe tip.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

Abstract: A short dummy test structure is disclosed, including a grounded shield layer above a substrate, at least two signal test pads, and a signal transmission line above the grounded shield layer and between the two signal test pads, wherein the signal transmission line is electrically coupled to the grounded shield layer. In one embodiment, the signal transmission line has a smaller total length than a total length of a corresponding signal transmission line and a device-under-test (DUT) of a test structure including the DUT. A de-embedding apparatus and method of de-embedding utilizing such a short dummy test structure are also disclosed.

Abstract: A voltage driver is provided having an input to receive test parameters from a microcontroller. The voltage driver having a first amplifier to provide an input to a first switch, based on the test parameters. The first switch having an output to a first connector such as a probe adapted to be connected to a device under test or DUT. A second switch having an input from a second connector to the device under test, the output of the second switch connected to a ground. A third switch has an input connected to the second switch input, the third switch having an output connected to the first connector to the device under test, wherein the first switch is open, and the second and third switch are closed to set the first connector and the second connector to ground. A buffer is provided such that the microcontroller is sets the test parameters in the first voltage driver, the first voltage driver is adapted to provide test data to the buffer.

Abstract: There is provided a method of measuring a leakage current or a dielectric breakdown voltage of a semiconductor wafer that has a base wafer and a buffer layer formed on the base wafer. The method includes providing, on the buffer layer, a plurality of electrodes including a hole injection electrode made of a material that injects a hole into the buffer layer when an electric field is applied thereto, measuring an electric current flowing through a pair of electrodes or a voltage between the electrodes when a voltage or an electric current is applied to the pair of electrodes, the electrodes including at least one hole injection electrode, and measuring a leakage current or a dielectric breakdown voltage caused by hole migration in the semiconductor wafer based on the current flowing through the pair of electrodes or the voltage generated between the pair of the electrodes.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: Detecting and/or mitigating the presence of particle contaminants in a MEMS device involves converting benign areas in which particles might become trapped undetectably by electric fields during test to field-free regions by extending otherwise non-functional conductive shield and gate layers and placing the same electrical potential on the conductive shield and gate layers. Particle contaminants can then be moved into detection locations remote from the potential trap areas and having particle detection structures by providing some mechanical disturbance.

Abstract: A method of testing a semiconductor device includes a conductive foreign matter test step of measuring the resistance value between the first and second conductive patterns to determine whether conductive foreign matter is present between the first and second conductive patterns, a first open circuit test step of measuring the resistance value between two points on the first conductive pattern to determine whether there is an open circuit in the first conductive pattern, and a second open circuit test step of measuring the resistance value between two points on the second conductive pattern to determine whether there is an open circuit in the second conductive pattern. The measurement of the resistance value in each of the test steps is accomplished by pressing probes vertically against the first conductive pattern or the second conductive pattern or both.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: A semiconductor chip includes a semiconductor chip body having a first surface on which pad parts are formed and an opposing second surface. Through-electrodes may be connected to the pad parts and formed to pass through the semiconductor chip body. Determination units may be connected to the through-electrodes and may be enabled to determine whether the pad parts and the through-electrodes are electrically connected with each other.

Abstract: A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.

Abstract: Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A collection optics having variable magnification, and which enable changing magnification without stopping the spray cooling. The variable magnification is provided by a turret that carries several objectives of different magnifications. A frame is provided above the turret, wherein the spray cooling is provided. By rotating the turret and changing its elevation, different objectives of the turret can be “docked” to a docking port within the frame.

Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: The present disclosure provides a method for testing a semiconductor device. The method includes providing a testing unit and an electronic circuit coupled to the testing unit and applying a first electrical signal to the testing unit. The method includes sweeping a second electrical signal across a range of values, the second electrical signal supplying power to the electronic circuit, wherein the sweeping is performed while a value of the first electrical signal remains the same. The method includes measuring a third electrical signal during the sweeping, the measured third electrical signal having a range of values that each correspond to one of the values of the second electrical signal. The method includes adopting an optimum value of the second electrical signal that yields a minimum value of the third electrical signal. The method includes testing the testing unit while the second electrical signal is set to the optimum value.

Abstract: Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

Abstract: Provided are an apparatus and a method of testing a semiconductor device. A horizontal maintaining unit provided inside a test head applies load to a probe card in a direction perpendicular to the probe card to hold the probe card in a horizontal state. Probe needles of the probe card are uniformly placed on a central region of pads of the semiconductor device, thereby providing an apparatus and a method of testing a semiconductor device capable of improving productivity and reducing a yield loss of a test process.

Abstract: A measurement terminal is arranged at an edge of a semiconductor wafer to be apart from a gate electrode and a source electrode formed in a surface portion on one side in a thickness direction of a semiconductor wafer so that an electrode contact portion is in contact with a drain electrode on the other side in the thickness direction of the semiconductor wafer and that a terminal contact portion is exposed to the one side in the thickness direction of the semiconductor wafer. A probe terminal is brought into contact with the terminal contact portion of the measurement terminal and the probe terminal is brought into contact with the gate electrode and the source electrode, to thereby measure electrical characteristics of a MOSFET.

Abstract: Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001) Ga face, being the substrate principal face, of inversion domains whose surface area where the polarity in the [0001] direction is inverted with respect to the principal domain (matrix) is 1 ?m2 or more being D cm?2; and a step of growing on the GaN substrate principal face an at least single-lamina semiconductor layer to form semiconductor devices in which the product Sc×D of the area Sc of the device principal faces, and the density D of the inversion domains is made less than 2.3.

Abstract: The present disclosure provides a semiconductor test system. The semiconductor test system includes a wafer stage to hold a wafer having a plurality of light emitting devices (LEDs); a probe test card operable to test each test field of the wafer; and a light detector integrated with the probe test card to collect light from a LED of the wafer.

Abstract: In an embodiment, a plurality of semiconductor chip portions is provided with respect to each reticle unit in a semiconductor wafer. Each of the semiconductor chip portions is provided with a first identification code generation circuit to generate a first identification code, and a switching circuit. The switching circuit controls connection with outside. Each of second identification code generation circuits is provided on dicing line areas within each reticle unit, and generates a second identification code to select the corresponding reticle unit. Coincidence detection circuits are provided on the dicing line areas. Each of the coincidence detection circuits determines whether or not the corresponding first and second identification codes and a chip select signal coincide with each other. Bus lines are provided on the dicing line areas. One ends of the bus lines are connected to the circuits, and the other ends are connected to test pads.

Abstract: An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.

Abstract: A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads.

Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.

Abstract: A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: A wafer inspection apparatus that performs surface inspection and internal inspection of solar cells using a single apparatus. The wafer inspection apparatus includes a loading unit configured to allow a cassette to be lifted up or lowered by an elevator. A surface inspection unit includes a plurality of stages, thus performing surface inspection of each wafer using a first vision module. A wafer transfer unit has a rotatably installed center portion and has both ends provided with adsorption parts. An internal inspection unit is configured such that a conveyor is installed to allow the wafer to be transferred, thus performing internal inspection of the transferred wafer through a second vision module. An unloading unit enables wafers having completed the internal inspection to be sequentially loaded onto the unloading unit. A control unit controls a series of wafer inspection procedures.

Abstract: A wafer inspection device, which inspects the electrical properties of a semiconductor wafer on which a semiconductor integrated circuit is formed, and the wafer inspection device has: a holding mechanism for holding a probe card; a wafer stage that holds the semiconductor wafer on the upper surface and is movably provided; and a pressing mechanism that are held and press the wafer stage against the probe card. The wafer stage is provided on the outer periphery with a seal ring. The seal ring forms a sealed space in a state where the wafer and the probe card are brought close to each other by contacting the probe card and is provided in such a manner as to reduce the pressure of the sealed space.

Abstract: A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines.

Abstract: An abnormality detecting unit includes a monitoring unit for monitoring an operation from a wafer deviation starting point to a transfer gate valve opening point after performing a plasma process on the wafer and specifying the operation as a wafer deviation operation; an acquisition unit for acquiring a high frequency signal of at least one of a progressive wave and a reflection wave outputted from a directional coupler between a high frequency power supply for applying a high frequency power into a processing chamber and a matching unit or between a lower electrode as a mounting table for mounting thereon the wafer and the matching unit during the wafer deviation operation; an analysis unit for analyzing a waveform pattern of the high frequency signal; and an abnormality determination unit for determining whether there is an abnormal electric discharge based on an analysis result of the waveform pattern.

Abstract: A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.

Abstract: A manufacturing method for probe card according to the present invention includes following processes. A film is formed on the surface of a circuit board. A connecting terminal and joint member are formed by etching the film, and the surface of the joint member is polished. An inspection contacting structure is assembled. The inspection contacting structure is moved proximity to a circuit board. The lower surface of a contactor and joint member are attached so as to contact the front end of a probe penetrating and passing through the contactor to the connecting terminal.

Abstract: A probe apparatus for probing a device on a semiconductor wafer to be tested by a testing equipment is provided. The probe apparatus includes a replaceable probe tile removably mounted in a probing location on a base plate. The probe tile is configured into a self-contained assembly which includes a chassis body containing a plurality of probes for probing devices on a wafer, a dielectric block for supporting the probes, and a wireguide for guiding a plurality of cables from the testing equipment into the chassis body. A wafer station having replaceable base plates and replaceable probe tiles are also provided.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of test structures located on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: Disclosed is a photoinduced carrier lifetime measuring method capable of obtaining photoinduced carrier effective lifetime of a semiconductor substrate with high accuracy regardless of the surface state of the sample. The method includes the steps of: irradiating a microwave onto a semiconductor substrate while periodically pulse-irradiating an induction light onto the semiconductor substrate; detecting the microwave transmitted through the semiconductor substrate or reflected by the semiconductor substrate; and obtaining the effective lifetime of photoinduced carriers generated in the semiconductor substrate by the pulse irradiation of the induction light, based on an irradiation duration Ti and a non-irradiation duration T2 when performing the induction light pulse irradiation and an integrated value of each microwave intensity obtained by the detection.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: Disclosed is a method for operating a test apparatus in which the testing efficiency is drastically increased. The test apparatus has a plurality of stages for testing wafers by using operation buttons displayed on the operating screens of each of a plurality of monitors. Exclusion condition buttons for excluding operation buttons are set in at least one monitor using exclusion condition data prepared by combining data required to perform various functions of the test apparatus and an exclusion condition pattern prepared by combining the exclusion condition of the exclusion condition data into data for deciding whether the operating button configured to operate each function can be pressed or not. Also, display of the screen that satisfies the exclusion condition for at least one monitor is prevented.

Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

Abstract: A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: To analyze an electric component in depth, provision is made to submit the aforementioned component to focused laser radiation. It is shown that by modifying the altitude of the focus in the component, some internal parts of the aforementioned component can be characterized more easily.

Abstract: A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine.

Abstract: Provision of a probe device, a processing device and a probe test capable of performing an efficient wafer probe test. A probe device, comprising a plurality of measuring stages to which a plurality of probe cards for inspecting semiconductor wafers are connected, respectively; a first conveying portion for conveying a semiconductor wafer to a first measuring stage to which a first probe card is connected; a first inspection control portion for controlling the inspection of the semiconductor wafer by the first probe card; a receiving portion for receiving stage information including information showing nonuse of the first measuring stage from a processing device; a second conveying portion for conveying the semiconductor wafer to a second measuring stage, to which a second probe card different from the first probe card is connected, according to the received stage information; and a second inspection control portion for controlling the inspection of the semiconductor wafer by the second probe card.