Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.

Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.

Abstract: A method and apparatus for detecting substrate arcing and breakage within a processing chamber is provided. A controller monitors chamber data, e.g., parameters such as RF signals, voltages, and other electrical parameters, during operation of the processing chamber, and analyzes the chamber data for abnormal spikes and trends. Using such data mining and analysis, the controller can detect broken substrates without relying on glass presence sensors on robots, but rather based on the chamber data.

Abstract: A method of detecting a defect of a semiconductor device includes forming test patterns and unit cell patterns in a test region a cell array region of a substrate, respectively, obtaining reference data with respect to the test patterns by irradiating an electron beam into the test region, obtaining cell data by irradiating the electron beam into the cell array region, and detecting defects of the unit cell patterns by comparing the obtained cell data with the obtained reference data.

Abstract: In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.

Abstract: A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.

Abstract: Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces.

Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.

Abstract: Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output.

Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.

Abstract: There is provided a probe card comprising a plurality of probe tips, each being ball-shaped or pillar-shaped and having a top end in contact with each of target chip pads to be tested; a first space converting unit; a second space converting unit; a frame configured to support the second space converting unit; an interposer unit; and a circuit board.

Abstract: A method for characterizing the electronic properties of a semiconductor sample by exploiting transients in measured photoconductance, the transients being induced by illuminating the semiconductor sample with a small probing illumination that is superimposed over a larger background illumination. In one embodiment, a pulse-type probing illumination is utilized, with either the intensity of the probing illumination being gradually reduced or the intensity of the background illumination being gradually increased until the measured photoconductance rise and decay in the sample are substantially exponential. In another embodiment, a continuous probing illumination with a sinusoidally-modulated intensity is utilized, the modulated intensity of the probing illumination being gradually adjusted until the measured photoconductance is linearly dependent thereupon.

Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.

Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.

Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.

Abstract: A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.

Abstract: A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology.

Abstract: A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer.

Abstract: An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

Abstract: A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

Abstract: An integrated circuit has a first independent power domain having a first power domain bus electrically connected to first functional blocks and a first power pad electrically connected to the first power domain bus and a second independent power domain having a second power domain bus electrically connected to second functional blocks and a second power pad electrically connected to the second power domain bus. A test element is between the first power domain bus and the second power domain bus.

Abstract: Techniques disclosed herein stress a dielectric layer until a pre-catastrophic, stress induced leakage current (SILC) condition is detected. When the pre-catastrophic SILC condition is detected, the stress is removed to prevent catastrophic failure of the dielectric and its associated device. Because these techniques prevent catastrophic failure of the dielectric layer, engineers can carry out physical failure analysis of the device, which is now known to have some type of defect due to detection of the pre-catastrophic SILC condition. In this way, the techniques disclosed herein allow engineers to more quickly determine an underlying cause of a defect so that yields can be kept at optimal levels.

Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

Abstract: A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided.

Abstract: The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer.

Abstract: Disclosed are a testing device and a testing method thereof. The testing device includes a frame, a flexible multi-layer substrate and at least one electrical testing point. The frame is positioned corresponding to a chip. At least one electrical connecting point is formed on a surface of the chip. The flexible multi-layer substrate is fixed in the frame. The electrical testing point is corresponding to the electrical connecting point and formed on an upper surface of the flexible multi-layer substrate for contacting the electrical connecting point and performing an electrical test to the chip. Furthermore, the electrical connecting point or the electrical testing point is a bump.

Abstract: A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.

Abstract: The present invention discloses a structure and a method for determining a defect in integrated circuit manufacturing process. Test keys are designed for the structure to be the interlaced arrays of grounded and floating conductive cylinders, and the microscopic image can be predicted to be an interlaced pattern of bright voltage contrast (BVC) and dark voltage contrast (DVC) signals for a charged particle beam imaging system. The system can detect the defects by comparing patterns of the detected VC signals and the predicted VC signals.

Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.

Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Abstract: A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.

Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.

Abstract: A system and method is provided for correcting alignment of a product on a tool and, more particularly, to a system and method for correcting alignment of a wafer on a chuck of a tool. The system is a tool including at least one contact near a circumference of the tool and a grounded contact proximate to the at least one contact.

Abstract: A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus.

Abstract: A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate.

Abstract: A semiconductor device includes; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and generating a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, such that the level of the test current is defined by the level of the bias current.

Abstract: Provided is a method for evaluating defects in a wafer. The method for evaluating the wafer defects includes preparing a wafer sample, forming an oxidation layer on the wafer sample, measuring a diffusion distance of a minority carrier using a surface photovoltage (SPV), and determining results of a contamination degree.

Abstract: A semiconductor apparatus (IPD) includes a set value storage unit that stores a set value determined based on an initial characteristic value of the IPD, and a detector that detects characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the set value stored in the set value storage unit. Further, a method of detecting characteristic degradation of a semiconductor apparatus (IPD) includes storing a set value determined based on an initial characteristic value of the IPD, and detecting characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the stored set value.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract: An apparatus and method for conducting electrical testing of probes is disclosed. Probes may also be tested for deflection and loading hysteresis.

Abstract: The present idea refers to a needle head, its use in a probe arrangement, and a method for electrically contacting multiple electronic components. The needle head comprises a body with a lower surface, needle electrodes emerging from the lower surface, and multiple outlets arranged in the lower surface. A channel is arranged between an inlet in the body and the outlets for conveying a medium from the inlet to the outlets. By this means, electronic components arranged in close distance under the lower surface of the needle head are directly exposed to the medium which provides a test environment during a test of the electronic components.