Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.

Abstract: A disclosed logic gate including a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor and also includes a resistance device connected in series with a source or a drain of at least one of the p-channel MOS transistor and the n-channel MOS transistor, a switching device connected in parallel with the resistance device and configured to switch on and off, and a switching control circuit configured to control the switching on and off of the switching device according to an output signal output from the CMOS circuit.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: An output circuit including an input terminal; an output terminal; a PMOS transistor connected with a positive side of a power voltage and the output terminal; a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage, wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor.

Abstract: An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mode. Accordingly, the semiconductor memory device including the output driver can have high test efficiency, since the number of test pins utilized during a test operation can be selectively reduced for low frequency tests.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable keeper circuit. The keeper can be used to compensate for a wide range of leakage corners where the internal storage is located. The adaptive keeper circuit not only increases the robustness of the storage node against leakage caused by process variation but also improves the overall performance of the static storage device connected to the node.

Abstract: A chopper circuit has a delay circuit that delays a received control signal and a difference detection circuit that detects a difference between a control signal delayed by the delay circuit and the received control signal. A first threshold based on which the delay circuit checks a change in the received control signal and a second threshold based on which the difference detection circuit checks a change in the received control signal are realized with a common threshold.

Abstract: A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors.

Abstract: A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit.

Abstract: Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit exchanges signals with another electronic device via a signal transmission line. The interface circuit includes a switch for pulling up the signal transmission line and a switch for pulling down the signal transmission line. While a pull-up or pull-down is performed, the interface circuit detects the potential level of the signal transmission line to determine whether the signal transmission line is pulled down or pulled up by the other electronic device. If the signal transmission line is not pulled down/pulled up by the other electronic device, the interface circuit exercises pull-down/pull-up control.

Abstract: An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.

Abstract: An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node high when the approximately symmetric clock signal is low, and discharges the pre-charged node to a low state if the logic function evaluates when the approximately symmetric clock signal is high, and keeps the pre-charged node high if the logic function fails to evaluate when the approximately symmetric clock signal is high, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is high.

Abstract: A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

Abstract: A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

Abstract: A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a first circuit module and a second circuit module. A first tail current source is coupled to the first circuit module. A second tail current source is coupled to the second circuit module. A first switch is coupled between the power supply node and the first tail current source. A second switch is coupled between the power supply node and the second tail current source, wherein the first switch is triggered to deactivate the first circuit module when the second circuit module is operating and the second switch is triggered to deactivate the second circuit module when the first circuit module is operating.

Abstract: A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

Abstract: A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transconductance amplifier device, and a third MOS transistor (M5, M8) as a folded cascode device. The first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage. The first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage. The buffer circuit has a very low input capacitance where the input capacitance does not vary with the buffer input voltage and other operating conditions, such as fabrication process, temperature and power supply voltage variations.

Abstract: A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low, and pulls a pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The mux pulls a feedback node high if the pre-discharged node goes high during the evaluation window, and pulls the feedback node low if the pre-discharged node is low during the evaluation window. The output stage is coupled to the pre-discharged node and the feedback node. The output stage provides an output signal based on states of the pre-discharged and the feedback nodes.

Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

Abstract: A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-commutative binary functions are designed by using the switching model. Latches can be realized by individually controlled gates sometimes with inverters. Optical and electro-optical latches are disclosed. The application of transmission gates to realize latches is also disclosed.

Abstract: The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic block during an evaluation phase; and, a feedback path arranged between the outputs and the dynamic current source which is responsive to a difference between the outputs. The simplicity of generating the low swing, achieved by the feedback which may be implemented by only two transistors, is in contrast with the complexity introduced by some methods used by other logic styles for achieving low swing.

Abstract: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: The use of an alternating current (ac) source to power logic circuitry can support satisfactory device performance for a variety of applications, while enhancing long-term stability of the circuitry. For example, when organic thin film transistor (OTFT)-based logic circuitry is powered by an ac power source, the logic circuitry exhibits stable performance characteristics over an extended period of operation. Enhanced stability may permit the use of OTFT logic circuitry to form a variety of circuit devices, including inverters, oscillators, logic gates, registers and the like. Such circuit devices may find application in a variety of applications, including integrated circuits, printed circuit boards, flat panel displays, smart cards, cell phones, and RFID tags. In some applications, the ac-powered logic circuitry may eliminate the need for ac-dc rectification components, thereby reducing the manufacturing time, expense, cost, complexity, and size of the component carrying the circuitry.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.

Abstract: A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle.

Abstract: In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit.

Abstract: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. For a homogeneous graft, the third transistor network has a complementary structure to the transistors between the intermediate node and the central node, is of the same transistor type as the given transistor network, and has inverted inputs relative to the transistors between the intermediate node and the central node. The third transistor network (the graft network) provides a second logic output to the logic circuit.

Abstract: Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract: A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance with logic. A footer device enables and disables the logic network. A keeper device is coupled to the dynamic node for retaining a charge state of the dynamic node while awaiting the logic network to operate in accordance with the logic. A test mode selection device is coupled to the dynamic node and is configured to enable a latch in the test mode. A phase selection device is configured to receive at least a wait signal and to enable selection of at least a precharge phase for charging the dynamic node to a voltage level, a write phase for generating a value to the latch based on the logic and the voltage level of the dynamic node, and a wait phase for enabling reading the value. The selection is based, at least partially, on the wait signal state.

Abstract: Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. First and second MOS transistors are each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.

Abstract: A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter comprises a delay element and a coincidence detector element for detecting coincidence of an input signal to the delay element and an output of the delay element. The delay elements may comprise stacked inverter circuits or stacked NAND gates.

Abstract: A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.

Abstract: An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-charges a pre-charged node high when the symmetric clock signal is low and opens an evaluation window when the pulsed clock signal goes high, and pulls the pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The output stage provides an output signal based on states of the pre-charged node and a second preliminary output node.

Abstract: A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.

Abstract: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor.

Abstract: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.

Abstract: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2 . . . XN) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.

Abstract: It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

Abstract: A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.

Abstract: A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant switch level; a second inverter stage providing a variable switch level that depends of the signal level of the input pad and comparing the constant switch level of the first inverter stage with the variable switch level of the second stage and providing an output signal at an output terminal thereof if the variable switch level of the second stage is greater than the constant switch level; and an additional circuit clement connected in series with the second inverter for decreasing the switch level of the second inverter stage.

Abstract: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.