Cmos Patents (Class 326/121)
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Patent number: 8653856Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.Type: GrantFiled: September 16, 2011Date of Patent: February 18, 2014Assignees: Texas Instruments Incorporated, Texas Instruments Deutschland GmbHInventors: Oliver Piepenstock, Andreas Bock, Bhavesh G. Bhakta
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Patent number: 8653857Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.Type: GrantFiled: May 5, 2009Date of Patent: February 18, 2014Assignee: Tela Innovations, Inc.Inventor: Scott T. Becker
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Patent number: 8629693Abstract: Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.Type: GrantFiled: May 2, 2012Date of Patent: January 14, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Inukai
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Patent number: 8593179Abstract: An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential.Type: GrantFiled: September 23, 2011Date of Patent: November 26, 2013Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Tomita
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Patent number: 8575963Abstract: A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.Type: GrantFiled: March 23, 2011Date of Patent: November 5, 2013Assignee: Fairchild Semiconductor CorporationInventor: Tyler Daigle
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Patent number: 8493774Abstract: A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality of bit-line transistors associated with a plurality of physically adjacent memory cells to a read bit-line. In response to an associated memory cell within the memory storing a first value, each of the plurality of read bit-line transistors turns on and provides a path to ground thereby causing a first output value to be output on the read bit-line. In response to all of the plurality of memory cells storing a second value, the plurality of read bit-line transistors turn off thereby preventing a path to ground and a second output value is output on the read bit-line.Type: GrantFiled: June 17, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Jente B. Kuang, Rahul M. Rao
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Patent number: 8487656Abstract: A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power terminal for receiving a plurality of logic signals. A first clock transistor is coupled between a second power terminal and the dynamic node for receiving a clock signal. A second clock transistor is in series with the N channel stack, between the dynamic node and a second power terminal, and for receiving the clock signal. An inverter circuit has an input coupled to the dynamic node and an output. A keeper transistor has a control electrode coupled to the output of the inverter circuit, a first current electrode coupled to the dynamic node, and a second current electrode. A plurality of P channel transistors, which are coupled in parallel, are coupled between the keeper transistor and the second power terminal and are for receiving the plurality of logic signals.Type: GrantFiled: May 31, 2012Date of Patent: July 16, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, George P. Hoekstra
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Patent number: 8487657Abstract: A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals. A P channel clock transistor is coupled between a second power supply terminal and the dynamic node is for receiving a clock signal. An N channel clock transistor is in series with the N channel stack and is between the dynamic node and the first power supply terminal is for receiving the clock signal. A keeper transistor has a first current electrode coupled to the dynamic node, a second current electrode coupled to a second power supply terminal, and a control electrode. A static logic circuit has an output for providing an output responsive to a state of the logic signals. The output is coupled to the control electrode of the keeper transistor.Type: GrantFiled: May 31, 2012Date of Patent: July 16, 2013Assignee: Freescale Semiconductor, Inc.Inventors: George P. Hoekstra, Ravindraraj Ramaraju, Maciej Bajkowski
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Patent number: 8482316Abstract: Circuits, methods, and systems are presented for managing current leakage in an electronic circuit. One circuit includes a keeper circuit, and a controller. The keeper circuit supplies current to a leaker circuit, which is experiencing current leakage, to compensate for the current leakage. Further, the controller provides to the keeper circuit a control signal that is based on the current leakage. The control signal has a cycle equal to the cycle of a clock signal, and the control signal is a pulse having a first value during a first period, and a second value during a second period of the pulse. The keeper circuit provides a current to the leaker circuit during the first period and the keeper circuit withholds the current to the leaker circuit during the second period, where the durations of the first period and the second period are based on the current leakage.Type: GrantFiled: March 2, 2012Date of Patent: July 9, 2013Assignee: Oracle International CorporationInventors: Zhen Wu Liu, Shree Kant, Heechoul Park
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Patent number: 8461877Abstract: A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates.Type: GrantFiled: July 1, 2011Date of Patent: June 11, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Kyle S. Viau, James Vinh
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Patent number: 8421503Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.Type: GrantFiled: March 2, 2010Date of Patent: April 16, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8405421Abstract: A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.Type: GrantFiled: May 30, 2012Date of Patent: March 26, 2013Inventors: Alexander Mikhailovich Shukh, Tom A. Agan
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Patent number: 8384439Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.Type: GrantFiled: November 30, 2009Date of Patent: February 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-chul Park, I-hun Song, Young-soo Park, Kee-won Kwon, Chang-jung Kim, Kyoung-kook Kim, Sung-ho Park, Sung-hoon Lee, Sang-wook Kim, Sun-il Kim
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Patent number: 8373443Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.Type: GrantFiled: May 26, 2011Date of Patent: February 12, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Kengo Akimoto, Masashi Tsubuku
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Patent number: 8373438Abstract: Semiconductor industry seeks to replace traditional volatile logic and memory devices with the improved nonvolatile devices. The increased demand for a significantly advanced, efficient, and nonvolatile data retention technique has driven the development of magnetic tunnel junctions (MTJs) employing a giant magneto-resistance (GMR). The present application relates to nonvolatile logic circuits with integrated MTJs and, in particular, concerns a nonvolatile spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct the nonvolatile logic circuits performing NOT, NOR, NAND and other logic functions.Type: GrantFiled: October 27, 2011Date of Patent: February 12, 2013Inventor: Alexander Mikhailovich Shukh
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Patent number: 8351028Abstract: According to an embodiment, a measuring device for measuring a laser beam comprises a magnification lens system with a total of two lenses which are arranged in series in the beam path of the laser beam and whose foci are coinciding, as well as a camera which is arranged behind the two lenses in the focus of the last lens and includes an electronic image sensor which generates an electronic image of the magnified laser beam. The lenses together with the camera are adjustable along the beam path relative to a reference point of the measuring device, for the purpose of locating the beam waist of the laser beam and of determining a diameter profile of the laser beam. The measuring device further comprises an adapter enclosing the beam path for coupling the measuring device to a laser system which provides the laser beam.Type: GrantFiled: September 12, 2008Date of Patent: January 8, 2013Assignee: Wavelight GmbHInventors: Bernd Zerl, Olaf Kittelmann
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Publication number: 20130002303Abstract: A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Kyle S. Viau, James Vinh
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Patent number: 8324940Abstract: An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.Type: GrantFiled: April 13, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
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Publication number: 20120287712Abstract: A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.Type: ApplicationFiled: November 23, 2011Publication date: November 15, 2012Applicant: WINBOND ELECTRONICS CORP.Inventor: Hiroki Murakami
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Patent number: 8294492Abstract: An ultra-low-power transconductance device is provided, (FIG. 1b, FIG. 1c), comprising a series connection of a transistor of a first channel type (A) and a transistor of a second channel type (B), the first channel type having a different polarity than the second channel type. The transistors each have a source, a drain and a gate. The source of the transistor of the first channel type (A) is coupled with the source of the transistor of the second channel type (B) and the drain of the transistor of the first channel type (A) is coupled with the gate of the transistor of the second channel type (B).Type: GrantFiled: April 29, 2008Date of Patent: October 23, 2012Assignee: Universite Catholique de LouvainInventors: David Bol, Denis Flandre, Jean-Didier Legat
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Patent number: 8220947Abstract: A first current source supplies a tail current It to a plurality of differential pairs. A pre-driver outputs gate signals to the gates of transistors of the corresponding differential pair. A pre-driver is configured to switch the state between the enable state and the disable state. In the enable state, the pre-driver outputs the gate signals that correspond to the differential signals. In the disable state, the pre-driver outputs the gate signals having levels which instruct the transistors of the corresponding differential pair to switch off.Type: GrantFiled: October 14, 2009Date of Patent: July 17, 2012Assignee: Advantest CorporationInventors: Yasuyuki Arai, Shoji Kojima
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Patent number: 8217680Abstract: A method of operating inverter may include providing a load transistor and a driving transistor connected to the load transistor wherein at least one of the load transistor and the driving transistor has a double gate structure, and varying a threshold voltage of the at least one of the load transistor and the driving transistor having the double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter.Type: GrantFiled: March 29, 2011Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sangwook Kim, Ihun Song, Changjung Kim, Jaechul Park, Sunil Kim
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Patent number: 8207758Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.Type: GrantFiled: July 1, 2011Date of Patent: June 26, 2012Assignee: The Board of Trustees of the University of ArkansasInventors: Jia Di, Scott Christopher Smith
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Patent number: 8188767Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.Type: GrantFiled: July 7, 2011Date of Patent: May 29, 2012Assignee: Technion Research & Development Foundation Ltd.Inventors: Alexander Fish, Arkadiy Morgenshtein
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Publication number: 20120081151Abstract: An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential.Type: ApplicationFiled: September 23, 2011Publication date: April 5, 2012Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Takashi TOMITA
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Patent number: 8120384Abstract: In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the push-pull output stages are connected to the respective inputs through first resistors and to a common output node through second resistors. As a result, a universal circuit element for a multivalued logic element, such as ternary logic or 5-valued logic is provided.Type: GrantFiled: November 22, 2010Date of Patent: February 21, 2012Assignee: Fuzzy Chip Pte. Ltd.Inventor: Viktor Viktorovich Olexenko
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Patent number: 8111089Abstract: A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.Type: GrantFiled: May 24, 2010Date of Patent: February 7, 2012Assignees: Syphermedia International, Inc., Promtek Programmable Memory Technology, Inc.Inventors: Ronald P. Cocchi, James P. Baukus, Bryan J. Wang, Lap Wai Chow, Paul Ouyang
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Patent number: 8059452Abstract: An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.Type: GrantFiled: May 4, 2010Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Publication number: 20110267099Abstract: To include a first inverter that receives an input signal to output an inverted signal, a second inverter that receives the inverted signal to output a first internal signal, and a third inverter that receives the input signal and outputs a second internal signal by using the inverted signal as a power supply. According to the present invention, because a signal on one signal path is used as a power supply of an inverter included in the other signal path, phases of a pair of output signals based on the input signal can be exactly matched without adding a capacitor or a resistor for adjustment.Type: ApplicationFiled: April 11, 2011Publication date: November 3, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Takenori Sato, Hideaki Kato
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Publication number: 20110267107Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.Type: ApplicationFiled: April 28, 2010Publication date: November 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Ming-Chieh HUANG, Bryan SHEFFIELD, Chih-Chang LIN
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Publication number: 20110249489Abstract: An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.Type: ApplicationFiled: April 13, 2010Publication date: October 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
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Patent number: 8036846Abstract: A variable impedance sense (VIS) circuit (400) can detect a drift in the impedance of variable impedance circuits due to changes in operating conditions. Adjustments to binary impedance setting codes are made in response to a detected drift only when such changes do not increase a worst case variation from a target impedance. Adjustments can also be made in response to a detected input offset polarity.Type: GrantFiled: September 28, 2006Date of Patent: October 11, 2011Assignee: Cypress Semiconductor CorporationInventor: Kalyana C. Vullaganti
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Publication number: 20110241731Abstract: Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.Type: ApplicationFiled: June 13, 2011Publication date: October 6, 2011Inventor: Cornelius Christian Russ
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Patent number: 8030971Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.Type: GrantFiled: April 14, 2008Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Meng-Hsueh Chiang, Ching-Te Kent Chuang, Keunwoo Kim
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Publication number: 20110215832Abstract: A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.Type: ApplicationFiled: September 13, 2010Publication date: September 8, 2011Inventor: Michael C. Wang
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Patent number: 8004316Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.Type: GrantFiled: February 1, 2006Date of Patent: August 23, 2011Assignee: Technion Research & Development Foundation Ltd.Inventors: Alexander Fish, Arkadiy Morgenshtein
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Patent number: 7994824Abstract: Logic Gate (100), particularly for integrated circuits including a Boolean network (105) having at least an input (106) and having at least an output node (107) and at least a terminal (108) connected to a first node at fixed potential (109) corresponding to a first logical level of the gate. The gate is characterized by the fact that the output node (107) is connected to a first pair of switches including a first switch (101) and a second switch (102), which are activated alternately, and are connected respectively, by a respective terminal, to the first node (109) at fixed potential and to the output node (107). Between the two switches there is a second pair of switches (103, 104) connected to a second node at fixed potential (110) corresponding to a second logical level of the gate.Type: GrantFiled: November 14, 2008Date of Patent: August 9, 2011Assignee: Fabio Alessio NarinoInventors: Fabio Alessio Marino, Alessandro Paccagnella
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Patent number: 7986167Abstract: Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode.Type: GrantFiled: August 23, 2010Date of Patent: July 26, 2011Assignee: SuVolta, Inc.Inventor: Ashok Kumar Kapoor
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Patent number: 7952392Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.Type: GrantFiled: October 26, 2009Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Kengo Akimoto, Masashi Tsubuku
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Publication number: 20110121861Abstract: In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the push-pull output stages are connected to the respective inputs through first resistors and to a common output node through second resistors. As a result, a universal circuit element for a multivalued logic element, such as ternary logic or 5-valued logic is provided.Type: ApplicationFiled: November 22, 2010Publication date: May 26, 2011Inventor: Viktor Viktorovich OLEXENKO
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Patent number: 7948263Abstract: A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.Type: GrantFiled: March 8, 2010Date of Patent: May 24, 2011Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and TechnologyInventors: Hyung-Ock Kim, Jung-Yun Choi, Bong-Hyun Lee, Mun-Jun Seo, Youngsoo Shin
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Patent number: 7919990Abstract: A semiconductor device of the present invention comprises an SGT based, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column. A second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column.Type: GrantFiled: February 1, 2010Date of Patent: April 5, 2011Assignee: Unisantis Electronics (Japan) Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 7893719Abstract: A digital data transmitting device is disclosed having differential signaling circuitry, a current source controller and a pair of transistor-implemented current sources is disclosed. The current source controller generates a current source control signal based on a detected mode of operation of the differential signaling circuitry. The pair of transistor-implemented current sources selectively generate source currents to adjust the output voltage levels as the differential output terminals in response to the current source control signal. The digital data transmitting device may also include a current bulk biasing circuit that generates a current source bulk biasing signal such that when the differential signaling circuitry is in one mode of operation, the current source bulk biasing signal retards currents leakage across the pair of transistor-implemented current sources.Type: GrantFiled: December 6, 2007Date of Patent: February 22, 2011Assignee: ATI Technologies, ULCInventors: Chihou Lee, Junho Cho
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Patent number: 7876131Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.Type: GrantFiled: September 21, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Kevin John Nowka
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Patent number: 7872503Abstract: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q?) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q?) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).Type: GrantFiled: July 18, 2005Date of Patent: January 18, 2011Assignee: ST-Ericsson SAInventors: Mihai Adrian Tiberiu Sanduleanu, Eduard Stikvoort
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Patent number: 7867858Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.Type: GrantFiled: March 31, 2008Date of Patent: January 11, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Giri Nallapati, Sushama Davar, Robert E. Booth, Michael P. Woo, Mahbub M. Rashed
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Patent number: 7859312Abstract: In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the push-pull output stages are connected to the respective inputs through first resistors and to a common output node through second resistors. As a result, a universal circuit element for a multivalued logic element, such as ternary logic or 5-valued logic is provided.Type: GrantFiled: April 30, 2008Date of Patent: December 28, 2010Assignee: Virtual Pro Inc.Inventor: Viktor Viktorovich Olexenko
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Patent number: 7859308Abstract: Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be processed. The cell contains, between the ground and the output (F) of the cell, at least one first branch including n dual gate N-type MOSFET transistors (M1,M2) in series and n?1 branches in parallel with the first branch, each provided with a dual gate N-type MOSFET transistor (M3), each of the logic functions corresponding to a given configuration of the cell. A specific set of control signals (C1,C2) is applied on the rear gates of at least one portion of the transistors (M2,M3), each control signal (C1,C2) being capable of setting the transistor (M2,M3) to a particular operating mode.Type: GrantFiled: July 11, 2008Date of Patent: December 28, 2010Assignees: Ecole Centrale de Lyon, Centre National de la Recherche Scientifique (CNRS)Inventors: Ian D. O'Connor, Ilham Hassoune
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Patent number: 7830179Abstract: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal.Type: GrantFiled: November 24, 2008Date of Patent: November 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-soon Lim, Chan-kyung Kim
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Patent number: 7804331Abstract: A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state.Type: GrantFiled: June 2, 2008Date of Patent: September 28, 2010Assignee: NEC Electronics CorporationInventor: Hideki Sugimoto